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Crystal Clock Oscillators
91SMOP (+3.0V, +3.3V or +5V PROGRAMMABLE MODELS)
91SMOP
STANDARD SPECIFICATIONS
STANDARD SPECIFICATIONS
STANDARD SMD CLOCK OSCILLATORS
using PLL technology
| Item | Specifications | ||||
| Generic part number | 91SMOP※1 | ||||
| Frequency range | 1.000 MHz to 200.000 MHz | 1.000 MHz to 80.000 MHz | |||
| Frequency stability (-20˚C to ＋75˚C) over all conditions | 91SMOP(A) : ±100 ppm 91SMOP(B) : ±50 ppm | 91SMOP(J) : ±100 ppm 91SMOP(K) : ±50 ppm | |||
| Operating Conditions Operating temperature Input voltage (VDD) | -20˚C to ＋75˚C ＋3.0V ±10%, ＋3.3V ±10% or ＋5V ±10% | ||||
| Tri-state control (Option1) OE control voltage (Pin#1)/(Pin#3) OPEN→Output VIH→Output VIL→High Impedance※2 (※2) Internal crystal oscillation to continue. Tri-state control (Option2) | ＋3.0V & ＋3.3V models SMI P/N ＋3.0V & ＋3.3V models SMI P/N | ||||
| VIH : ＋2.2 VDD min. VIL : ＋0.5 VDD max. | 91SMOP(3VA)OE 91SMOP(3VB)OE | VIH : ＋2.2 VDD min. VIL : ＋0.5 VDD max. | 91SMOP(3VJ)OE 91SMOP(3VK)OE | ||
| ＋5V models | SMI P/N | ＋5V models | SMI P/N | ||
| VIH : ＋4.0 VDD min. VIL : ＋0.5 VDD max. | 91SMOP(5VA)OE 91SMOP(5VB)OE SMI P/N | VIH : ＋4.0 VDD min. VIL : ＋0.5 VDD max. | 91SMOP(5VJ)OE 91SMOP(5VK)OE SMI P/N | ||
| Stand-by (SB) control voltage (Pin#1)/(Pin#3) OPEN→Output VIH→Output VIL→High Impedance※3 (※3) Internal crystal oscillation to stop. | ＋3.0V & ＋3.3V models VIH : ＋2.2 VDD min. VIL : ＋0.5 VDD max. | 91SMOP(3VA)SB 91SMOP(3VB)SB | ＋3.0V & ＋3.3V models VIH : ＋2.2 VDD min. VIL : ＋0.5 VDD max. | 91SMOP(3VJ)SB 91SMOP(3VK)SB | |
| ＋5V models | SMI P/N | ＋5V models | SMI P/N | ||
| VIH : ＋4.0 VDD min. VIL : ＋0.5 VDD max. | 91SMOP(5VA)SB 91SMOP(5VB)SB | VIH : ＋4.0 VDD min. VIL : ＋0.5 VDD max. | 91SMOP(5VJ)SB 91SMOP(5VK)SB | ||
| Absolute Max. Ratings Supply voltage Storage temperature | -0.5V to ＋7.0V DC -55˚C to ＋125˚C | ||||
| Input current (Pin#1=Open or VIH) | ＋3.0V ±10% | 30 mA max. | 20 mA max. | ||
| ＋3.0V ±10% | 30 mA max. | 20 mA max. | |||
| ＋5V ±10% | 50 mA max. | 30 mA max. | |||
| Stand-by current※3(option) | 50μA max. (VDD = ＋3.0V & Pin #1=VIL) | ||||
| Output (-20˚C to ＋75˚C) Symmetry Rise and fall times "0" level "1" level Load | 45% to 55% at 50%VDD level (1.00MHz to 80.00MHz) 40% to 60% at 50%VDD level (80.00MHz to 200.00MHz) 5 ns max. (20%VDD to 80%VDD level) VOL : 10%VDD max. (1.00MHz to 130.00MHz) VOL : 20%VDD max. (130.00MHz to 200.00MHz) VOH : 90%VDD min. (1.00MHz to 130.00MHz) VOH : 80%VDD min. (130.00MHz to 200.00MHz) | ||||
| 15 pF max. (CMOS) | 50 pF max. (CMOS) | ||||
| Disable delay time | 100 ns max. | ||||
| Enable delay time | 150 ns max.(OE models) 10 ms max.(Stand-by models) | ||||
| Startup time | 10 ms max. | ||||
| Jitter (pSp-p) | 100, 200, 250 max. (depending on frequencies) | ||||
| Aging (non operating) | ±5 ppm max. at ＋25˚C ±3˚C for first year | ||||
| Reflow condition | ＋250˚C ±10˚C for 10 seconds ＋170˚C ±10˚C for 1 to 2 minutes (preheating) | ||||
91SMOP
7.0±0.2 #4 #3
#1 #2
1.4 3.68 1.4 #1 #2
5.08 #4 #3
PIN CONNECTION 1 "L" OPEN or "H" 2 GND 3 Z OUTPUT 4 V Z : high impedance
OUTPUT WAVEFORM
TR TF V
V ("1"Level)
90% or 80% V 50% V 10% or 20% V
V ("0"Level)
OV DC
GND t T Symmetry=t/T×100(%)
TEST CIRCUIT
Test Point
SOLDERING PATTERN
PACKAGE DATA
TAPE SPECIFICATIONS
| PPaacckkaaggee IItteemm | 9911SSMMOOPP |
| Lid | Ceramic |
| Base | Ceramic |
| Sealing | Glass |
| Terminal | Tungsten (metalized) |
| Terminal plating | Gold / Nickel (surface) / (under) |
| RoHS | Compliant |
| A | B C D F | J L M Reel Dia. | Qty/Reel |
| 7.4 | 5.4 16.0 7.5 8.0 1 | .5 0.3 1.9 180 | 1000pcs |
(※1) Final exact part number to be determined with frequency, frequency stability, operating temperature and input voltage. e.g. 91SMOP(3.3VA)SB 200.000 MHz. (※2) Internal crystal oscillation to continue(Pin #1=VIL). (※3) Internal crystal oscillation to be halted(Pin #1=VIL).