9014 FAIRCHILD

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Fairchild QFET for Synchronous Rectification DC to DC Converters by K.S. Oh July, 2000 Rev. B, July 2000 1. Introduction Fairchild is currently developing and marketing a new QFET series that has improved RDS(on), gate charge, and switching speed characteristics. The superior features of these QFETs are very useful for increasing the efficiency of low output voltage power supplies, making it spe- cially appropriate for computer microprocessor power supply applications which require high efficiency. This application note describes the use of a Fairchild QFET (FQP60N03L ) in the power sup- ply (DC-DC converter) of computer microprocessors. Chapter 2 describes QFET’s organiza- tional features and the improvements in its electrical characteristics based on these features. Chapter 3 outlines the required input voltage and current based on the latest trends in micro- processors, and describes the optimum DC-DC converter circuit configuration that will meet these input conditions. The synchronous rectification DC-DC converter introduced in Section 3-1, which increases the overall efficiency by converting the loss due to the forward voltage drop of the rectifier diode to the MOSFET’s low R DS(on) loss, is explained in detail in the main body of this note. Lastly, Chapter 4 describes an example of a synchronous rectification DC- DC converter design that uses the Fairchild PWM control IC RC5058, and the loss and effi- ciency associated when FQP60N03L is used. 2. QFET Figure 2-1. Comparison of a QFET and a Conventional MOSFET Structure Poly N- epi. N+ substrate Conventional (Cellular) Poly P+ N+ N+ substrate N- epi. QFET (Stripe)

Rev. B, July 2000 3. Synchronous Rectification DC to DC Converter Recent increases in computer microprocessor processing speed have demanded lower oper- ating voltages. A broad range of input voltages and currents are required by Intel microproces- sors with processing speeds that range from 233-1000MHz. Tables 3-1 and 2 list voltage and current specifications recommended by Intel Corp for the Celeron™ and Pentium® III proces- sors. (Refer to Intel VRM 8.4 DC-DC Converter Design Guidelines) The DC-DC converter responsible for supplying only the microprocessor input voltage and current recommended in Tables 3-1 and 2, used in the computer motherboard, is required to output high quality DC voltage almost free of ripples. Because of system characteristics, a step-down DC-DC converter that employs feedback control through the PWM controller is generally used. Figure 3-1 shows the basic circuit of a step-down (Buck topology) DC-DC con- Table 3-1. Pentium® III processor (> 2.0V) Voltage and Current Specifications Symbol Parameter Processor core frequency [MHz] Min. Typ. Max. Unit VccCORE VCC for processor core <600 600 / 600B 2.00 2.05 V VccCORE static tolerance at processor connector pins on system board -0.070 0.070 V VccCORE transient tolerance at processor connector pins on system board -0.140 0.140 V IccCORE Current for VccCORE 600 / 600B 550 533B 500 450 17.8 17.0 16.7 16.1 14.5 A Icc SGNTCORE I CC for Stop-Gain VccCORE 1.68 A IccDSLPCORE I CC for Deep-Sleep VccCORE 0.50 A dIccCORE/dt I CC slew rate 20 A/ µs Table 3-2. Pentium® III processor (<1.7V) Voltage and Current Specifications Symbol Parameter Processor core frequency [MHz] Min. Typ. Max. Unit VccCORE VCC for processor core All SECC2 1.65 V All PC-GPA 1.60 VccCORE static tolerance at processor connector pins on system board All SECC2 -0.080 0.040 V All FC-PGA -0.080 0.040 Vcc CORE transient tolerance at processor connector pins on system board All SECC2 -0.080 0.050 V All FC-PGA -0.130 0.080 IccCORE Current for VccCORE 700-733 600-667 500-550 14.6 13.3 11.0 A IccSGNTCORE I CC for Stop-Gain VccCORE 2.5 A IccDSLPCORE I CC for Deep-Sleep VccCORE 2.2 A dIccCORE/dt I CC slew rate 20 A/ µs

Rev. B, July 2000 verter used to supply power to the microprocessor. Section 3-2 briefly explains the operation of a Buck converter. Figure 3-1. Step-down (Buck) DC-DC Converter 3-1. Efficiency of Buck Converter In order to increase the overall efficiency, it is important to reduce the loss generated in each component, as much as possible, in low output voltage power supplies. Equation (3-11) in Section 3-2 shows the reduction in system efficiency due to the loss associated with semicon- ductor components such as the switch MOSFET (Q1) and freewheeling diode (D). If the free- wheeling diode (D) is substituted with the MOSFET (Q2), the semiconductor component loss can be reduced because the loss from the diode's forward voltage drop is greater than the loss from the MOSFET’s R DS(on). This effect is represented by the following equation. First, assume the following conditions: output current Iout=18[A], duty ratio D=0.49, freewheeling (Schottky) diode's forward voltage drop VD=0.52[V] (the typical value when iF=18[A], TJ=100[°C] in MBRD835L data sheet Figure 2), and MOSFET RDS(on)=14.70[mΩ ] (the typical value when VGS=10[V], TJ=100[°C] in Figure 2-3). Then, the freewheeling diode (D) loss can be calculated by the following equation (3-1): If substituted with the MOSFET (Q2), the MOSFET (Q2) loss is calculated by equation (3-2) as follows. The calculation results of equations (3-1) and (3-2) verify the increase in efficiency if the free- wheeling diode (D) is substituted with a MOSFET(Q2). This method is called synchronous rec- tification, and the MOSFET, a synchronous rectifier (Q2). Figure 3-2 is a remodeling of the circuit shown in Figure 3-1 employing synchronous rectification. If the Schottky diode (D2) is used in parallel with the synchronous rectifier (Q2) in this circuit, the inductor (L2) current that previously flowed through the parasitic diode of the synchronous rectifier (Q2) starts flowing through the faster and low loss Schottky diode (D2) during the switching dead time of the two MOSFET’s (Q1, Q2). This flow pattern makes the circuit more efficient. PWM Control IC Switch MOSFET (Q1) (L2) DC Input (Vin) (C2) RL Freewheeling Diode (D) PV DIout 1D–()=

4.77 W[]=

PI out 1D–()[] RDS on()=

2.43 W[]=

Rev. B, July 2000 A DC-DC converter is primarily used to obtain a specific DC voltage from any DC voltage. The output to input voltage ratio of the Buck converter is described as follows. First, assume an ideal circuit, where the losses associated with each portion of the circuit have been ignored. Because L2 current i L(t1)and iL(t3) must be equal, as shown in Figure 3-4, equation 3-3 is derived as follows: Equation (3-4) can be obtained from Equation (3-3): When this is divided into Q1’s on and off periods, the following can be derived: The left hand side of Equation (3-5) represents the integral of L2 voltage with respect to time during Q1’s on period and the right hand side represents the integral of L2 voltage with respect to time during Q1’s off period. When this equation is applied to the Buck converter, the follow- ing equation is derived. The V in - Vout of the left hand side of the equation represents the L2 voltage in the (DTs) period when Q1 is on, and Vout of the right hand side represents the L2 voltage in the ((1 - D)Ts) period when Q2 is off. Equation 3-6 can be reduced to the following to calculate the output to input voltage ratio. Equation (3-7) shows the output to input voltage ratio for an ideal case. However, the forward voltage drop component of the switch MOSFET Q1 and the freewheeling diode D exists in an actual system operating environment. Figure 3-5. Equivalent circuit of an ON and OFF Step-down (Buck) Converter, which accounts for the forward voltage drop of the switch MOSFET(Q1) and the freewheeling diode (D) L---- vL t() td ∫ iL t()d vL t() td vL t() td ∫–= Vin Vout–() DTs Vout 1D–() Ts……… 36–()= Where T s period= + -vds Vin ids(t) Vout iL(t) [Ton] Iout Vout Iout +iL(t) iD(t)Vin vD [Toff]

Rev. B, July 2000 Equation (3-8) can be obtained as in Equation (3-6) by referring to Figure 3-5: Equation (3-9) represents this equation with respect to Vout: Rearranging the above equation (3-9) in terms of D, The efficiency (η) can be obtained from equation (3-11) using the input to output current ratio, Iin/Iout=D, and equation (3-10): As shown by equations (3-9) and (3-11), the forward voltage drop of the switch MOSFET and the freewheeling diode reduces the output voltage and the entire system efficiency. Besides these factors, the inductor coil resistance and the capacitor ESR also drop the efficiency. Hence, a low coil resistance inductor and low ESR capacitors must be used. In the case of the capacitor, it is advantageous to use several capacitors in parallel. A high quality output DC voltage with low ripple, if possible, is considered the best. The follow- ing is a description of the Buck converter output voltage ripple. Figure 3-6. Inductor Current Ripples appear in the output voltage as the L2 current ripple component, ∆iL charges and dis- charges C2 as illustrated in Figure 3-6. C2 is charged during the period when iL(t) is greater than Iout. The charge (∆Q) that flows into C2 at this time divided by the value of C2 (C) is the output voltage ripple component. First, the following equation calculates the ∆iL in Figure 3-6: Vin vds t()– Vout–() DTs Vout vD t()+() 1D–() Ts………… 38–()= Vout DVin Dvds t() vD t() 1D–()+[] … 39–()–= D Vout vD t() 1D–()+ η Vout Iout VinIin Vout Vin Vin v ds t()– iL(t) ∆iL/2 Ts/2 ∆iL iL=Iout t t1 t2 t3 ∆ iL DTs Vin Vout–

Rev. B, July 2000 ∆Q, the portion indicated by the thick line in Figure 3-6, can be calculated as a triangular area of ∆iL/2 in height and Ts/2 in width. The following equation is derived when equation (3-12) is substituted into equation (3-13), where the peak-to-peak output voltage ripple component is ∆vout: where: As shown by equation (3-14), the output voltage ripple can be reduced, if fs is increased or if it is designed so that fc becomes fc<<fs. 4. Synchronous Rectification DC-DC Converter Design 4-1. Design Example The design in Figure 4-1 outputs the processor core voltage VccCORE (1.3[V] ~ 3.5[V]), Vtt ter- mination (1.5[V]), Vclock (2.5[V]), and Vagp (Selectable 1.5[V] / 3.3[V]) using the Fairchild PWM control IC RC5058. Of these outputs, only VccCORE is output by the synchronous rectification DC-DC converter and the remaining outputs are output through the linear regulator. This sec- tion describes the calculations for the input (L1) / output (L2) inductor and input (C1) / output (C2) capacitor for the synchronous rectification DC-DC converter design shown in Figure 4-1. The following initial design conditions are set. s = 310[kHz]

  • V DS(on) = 0.37[V] (Q1’s on-state drain-to-source voltage = Iout × RDS(on))
  • ∆iL < 2[A]: set it to twice the value of the minimum output current to operate in the continuous mode.
  • V out = 2.0[V]: refer to table 3-1.
  • Output voltage ripple ∆vout < 0.04[V]: set within ±1[%] of Vout = 2.0[V]
  • Input voltage ripple ∆vin < 0.5[V]: set within ±5[%] of Vin = 5[V]
  • Input current I in = 8.47[A]: set to 85% efficiency at max load condition (Vin = 5[V], Vout = 2.0[V], Iout = 18[A]). ∆ Q 1 2---  ∆ iL  Ts ∆ vout ∆ Q D1 D–() VinTs fs ----- ……… 31 4–()=== fc 2π LC fs: switching frequency D0 . 4 9 Vout VD+ =

Rev. B, July 2000 Figure 4-1. Synchronous Rectification DC-DC Converter using the PWM Control IC RC5058 1) L1/L2 design (1) Output Inductor, L2 The output inductor must be designed so that it operates in a continuous mode having no dis- continuous interval in the output inductor current to stabilize frequency and optimize load reg- ulation. When Q1 is on, the voltage at both terminals of L2 is V L=Vin - VDS(on) - Vout. L2 can be calcu- lated with the following equation (4-1). (2) Input Inductor, L1 Used after the 5V terminal to eliminate the switching noise caused by the input ripple current, a L1 of 1.3µH is generally sufficient. Care must be taken not to make L1 too large because an excessively large input inductor can restrict the current change rate at the converter input, which in turn, can weaken the converter transient response characteristics. +12V Vcc VID0 VID1 VID2 VID3 VID4 +5V +3.3V +3.3V +3.3V +5V VCCA VTTG HDRV LODRV VFB GNDP GNDA DROOP VTTFB VCKG VCKFB AGPG AGPFB 17PWRGD AGPTYP VTTP ILIM RC5058 SW E/SS 4.7 0.1uF 0.1uF 1.3uH 8.2K Q24.7 1200uF×5 + 1uF 4.7uF 1000uF 1000uF 1000uF 1500uF×10 5.1 3.92K SW 1uF Schottky diode 2.5uH 10K PWRGD VID[0..4] ENABLE/SS FQP60N03L L2 C2 VccCORE Vtt Vclock Vagp Vin VDS on() Vout–– ∆ iL

Rev. B, July 2000 2) C1/C2 design (1) Output Capacitor, C2 C2 can be calculated from equation (4-2), which is derived from equations (3-13) (output volt- age ripple calculation equation) and (3-14). A capacitor with low ESR should be used, if possible, to minimize the ESR loss. The maximum ESR of C2 can be calculated from equation (4-3) below. C2 is set with a value much greater than the minimum value, and connected in parallel to reduce the output voltage ripple and ESR. (2) Input Capacitor, C1 In order to reduce ESR, C1, which is used as the input low pass filter, should be designed in parallel, if possible. The following equation (4-4) shows the calculation for C1. 4-2. Power Loss Analysis The losses generated mainly in the synchronous rectification DC-DC converter in Figure 4-1 are as follows:

  • MOSFET conduction losses: I 2RDS(on)
  • Inductor equivalent resistance DC losses
  • PCB copper losses
  • MOSFET gate-charge losses
  • Diode-conduction losses
  • Transition losses of power MOSFET
  • Capacitor ESR losses
  • Losses due to the PWM control IC Among the losses, conduction losses (I 2RDS(on)), gate-charge losses, and transition losses are specifically associated with the MOSFET and can be represented by the following equa- tion. ∆ iL 8fs∆ vout 2A[] ESR ∆ Vout ∆ iL

0.04 V[]

∆ vin 8.47 A[] 1.58 µ secsecsecsec[]×

Rev. B, July 2000 Conduction losses (Pc) This loss is defined as the loss generated between the drain and source during the MOSFET on period and can be easily calculated with equation P=I2R, where the current, I, is the RMS value of Iout, , and the resistance, R, is R DS(on). The conduction loss can be calculated with equation (4-5) as follows. where RDS(on) is determined by the gate-source drive voltage and junction temperature Gate-charge losses (Pg-c) The gate-charge loss is defined as the loss generated during charging and discharging of Ciss for driving the MOSFET. The gate-charge loss can be calculated from equation (4-6). where VGS: Gate drive voltage Qg: Total gate charge at VGS Transition losses (Pt) This loss is defined as the loss generated between the drain and source during the transition period when an on MOSFET turns off or an off MOSFET turns on. The equation to calculate this loss can be derived from the method of calculating the triangular area where v ds(t) and ids(t) overlap at on and off transition, as shown in Figure 4-2. Figure 4-2. Transition Waveform of MOSFET for inductive loads where Pt(on): Turn-on transition loss Pt(off): Turn-off transition loss ids(on): Maximum value of the drain-to-source current at turn-on ids(off): Maximum value of the drain-to- source current at turn-off tt(on): Turn-on transition time tt(off): Turn-off transition time Iout D() Pc Iout D() t tt(on) vds(on) vds(t)&ids(t) vds(max) vds(t) ids(on) ids(t) vds(on) tt(off) vds(t) ids(off) t Pt Pto n() Pto f f()+= vds max() ids on() tto n() i+ ds off() tto f f()() fs[]

Rev. B, July 2000 Equations (4-5), (4-6) and (4-7) show that the MOSFET used in the DC-DC converter needs low RDS(on), low Qg, and fast switching speed characteristics in order to increase the system efficiency. Now let's calculate the losses using the measured data, after having applied FQP60N03L to Q1 and Q2, as shown in Figure 4-1, and where the test conditions are input voltage = 5V, out- put voltage = 2V, and load current = 7A. (1) Q1 (2) Q2 The R DS(on) value used in the above calculation was taken from the Figure 2-3 graph, and it corresponds to the RDS(on) value when the MOSFET temperature has reached saturation after 1 hour of set operation. Q2 transition loss is almost zero because there is almost no current flowing between Q2's drain and source during the transition period, but rather most of the cur- rent flows through D2, which forms a current pass during dead time. The waveforms in Figure 4-3 are of currents flowing between the drain and source of Q1 and Q2 MOSFETs. Pto f f() Pt Pto n() Pto f f()+= PQ1 Pc Pgc– Pt++= 2241.82 mW[]= PQ2 Pc Pgc–+= 183.83 mW[]= *Ptotal PQ1 PQ2+=

Rev. B, July 2000 The reason that the efficiency of the 1.550V output voltage is less than that of the 2.000V out- put voltage, as shown in Figure 4-4, is largely due to inductor loss. The efficiencies above can change depending on the diode forward voltage drop, inductor equivalent resistance, capacitor ESR and the PCB layout. Two suggestions are made by POWER PLANES of the Fairchild Application Bulletin AB-11 (PC Board Layout Checklist: DC- DC Converters) for the layout to minimize the loss, that is, 1) High currents are located on planes, not traces 2) and an internal power plane connects the source of the highside MOS- FET, the inductor, and the flyback Schottky diode (or the drain of the lowside MOSFET) together. 5. Conclusions The computer microprocessor power supply (DC-DC converter) is operated at 200[kHz]~400[kHz] high frequency to supply high-quality DC low voltage required by the com- puter microprocessor. However, operating at high frequencies can increase the loss, empha- sizing the need to increase the efficiency. As shown by the MOSFET loss calculation (gate- charge loss, transition loss or switching loss), high efficiency can be obtained if a small gate- charge and a fast switching speed MOSFET are used, the higher the frequency of operation. Furthermore, a product with a low R DS(on) is required to reduce the MOSFET conduction loss, the more serious obstacle when supplied with a high load current. The FQP60N03L developed by Fairchild is a QFET 30V product with improved RDS(on), gate charge, and switching speed characteristics which offers a higher level of set efficiency as described in Section 4-2. References 1. Hee Jun Kim, "Switch Mode Power Supply,” Seong An Dang, 1993 2. Mohan, Undeland, Robbins, "Power Electronics," John Wiley & Sons, Inc., 1995 3. George Chryssis, "High-frequency Switching Power Supplies: Theory and Design," McGraw-Hill, Inc., 1992 4. PWM Control IC RC5058 Data sheet, "High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage Platforms," Fairchild

©2000 Fairchild Semiconductor International Rev. B, July 2000 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ E 2CMOS™ FACT™ FACT Quiet Series™ FAST FASTr™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILDíS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.