89HPES12N3A

89HPES12N3A RENESAS

Document overview

• Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
• PDF pages: 32

Technical content

Features

◆ High Performance PCI Express Switch – Twelve 2.5Gbps PCI Express lanes – Three switch ports – Upstream port configurable up to x4 – Downstream ports configurable up to x4 – Low-latency cut-through switch architecture – Support for Max Payload Sizes up to 2048 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 1.1 compliant ◆ Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Ability to load device conf iguration from serial EEPROM ◆ Legacy Support – PCI compatible INTx emulation – Bus locking ◆ Highly Integrated Solution Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twelve 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed) ◆ Reliability, Availability, and Serviceability (RAS) Features – Supports ECRC and Advanced Error Reporting – Internal end-to-end parity protecti on on all TLPs ensures data integrity even in systems t hat do not implement end-to-end CRC (ECRC) – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC and server motherboards Block Diagram Figure 1 Internal Block Diagram

12 PCI Express Lanes

One x4 Upstream Port and Two x4 Downstream Ports 3-Port Switch Core Frame Buffer Scheduler Multiplexer/Demultiplexer Transaction Layer Data Link Layer Route Table Port Arbitration Scheduler SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer/Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer/Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer 89HPES12N3A Data Sheet 12-lane 3-Port PCI Express® Switch

2 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet ◆ Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Supports PCI Power Management Interface specificat ion (PC I-PM 1.1)

• Supports device power management states: D0, D3 hot and D3cold – Unused SerDes are disabled ◆ Testability and Debug Features – Ability to read and write any in ternal register via the SMBus ◆ Eight General Purpose Input/Output Pins – Each pin may be individually co nfigured as an input or output – Each pin may be individually co nfigured as an interrupt input – Some pins have selectable alternate functions ◆ Packaged in 19x19mm 324-ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES12N3A provides the most efficient I/O c onnectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It pr ovides connectivity for up to 3 ports across 12 integrated serial l anes. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification revision 1.1. SMBus Interface The PES12N3A contains two SMBus interfaces. The slave interface provides full access to the confi guration registers in the PES12N3A, allowing every configuration register in the device to be read or written by an external agent. The master inte rface allows the default configura- tion register values of the PES12N3A to be overridden following a reset with values programmed in an exte rnal serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the tw o SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interfac e, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pi ns allow the SMBus address of the serial configuration EEPROM from which data is loaded to be config- ured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1. Bit Slave SMBus Address Master SMBus Address

1 SSMBADDR[1] MSMBADDR[1]

2 SSMBADDR[2] MSMBADDR[2]

3 SSMBADDR[3] MSMBADDR[3]

Table 1 Master and Slave SMBus Address Assignment As shown in Figure 2, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 2(a), the master and slave SMBuses are tied together and the PES12N3A acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES12N3A registers suppor ts SMBus arbitration. In some systems, this SMBus master in terface may be implemented using general purpose I/O pins on a proces sor or micro controller, and may not support SMBus arbitration. To support these systems, the PES12N3A may be configured to operate in a split configuration as shown in Figure 2(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi- master arbitration is never required. The PES12N3A supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. 4 0 MSMBADDR[4]

5 SSMBADDR[5] 1

Table 1 Master and Slave SMBus Address Assignment

4 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12N3A. Some of the functions listed may be multiplexed o nto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Note: In the PES12N3A, the two downstream ports are labeled port 2 and port 4. Signal Type Name/Description PE0RP[3:0] PE0RN[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. PE0TP[3:0] PE0TN[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 0. PE2RP[3:0] PE2RN[3:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE2TP[3:0] PE2TN[3:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 2. PE4RP[3:0] PE4RN[3:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PE4TP[3:0] PE4TN[3:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 4. PEREFCLKP[2:1] PEREFCLKN[2:1] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the dif- ferential reference clock is determined by the REFCLKM signal. REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre- quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz Table 2 PCI Express Interface Pins Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins

5 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output Table 4 General Purpose I/O Pins Signal Type Name/Description CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi- cates that a common clock is being used between the upstream device and the upstream port. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. Table 5 System Pins (Part 1 of 2)

6 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the PES12N3A and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES12N3A executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device opera- tion begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. SWMODE[3:0] I Switch Mode. These configuration pins determine the PES12N3A switch operating mode. These pins should be static and not change after the negation of PERSTN. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0xF Reserved Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins Signal Type Name/Description V DDCORE I Core VDD. Power supply for core logic. VDDIO I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. Table 7 Power and Ground Pins Signal Type Name/Description Table 5 System Pins (Part 2 of 2)

7 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VTTPE I PCI Express Termination Power. VSS I Ground. Signal Type Name/Description Table 7 Power and Ground Pins

8 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Pin Characteristics Note: Some input pads of the PES12N3A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes PCI Express Interface PE0RN[3:0] I CML Serial link PE0RP[3:0] I PE0TN[3:0] O PE0TP[3:0] O PE2RN[3:0] I PE2RP[3:0] I PE2TN[3:0] O PE2TP[3:0] O PE4RN[3:0] I PE4RP[3:0] I PE4TN[3:0] O PE4TP[3:0] O PEREFCLKN[2:1] I LVPECL/ CML Diff. Clock Input Refer to Table 9 PEREFCLKP[2:1] I REFCLKM I LVTTL Input pull-down SMBus MSMBADDR[4:1] I LVTTL Input pull-up MSMBCLK I/O STI 2 pull-up on board MSMBDAT I/O STI pull-up on board SSMBADDR[5,3:1] I Input pull-up SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board General Purpose I/O GPIO[7:0] I/O LVTTL High Drive pull-up System Pins CCLKDS I LVTTL Input pull-up CCLKUS I pull-up MSMBSMODE I pull-down PERSTN I RSTHALT I pull-down SWMODE[3:0] I pull-down Table 8 Pin Characteristics (Part 1 of 2)

9 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up External pull-down 1. Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down. 2. Schmitt Trigger Input (STI). Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes Table 8 Pin Characteristics (Part 2 of 2)

10 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Logic Diagram — PES12N3A Figure 4 PES12N3A Logic Diagram Reference Clocks PEREFCLKP PEREFCLKN PE0TP[0] PE0TN[0] JTAG_TCK GPIO[7:0]

8 General Purpose

PE0RP[0] PE0RN[0] PE0RP[1] PE0RN[1] PE0RP[3] PE0RN[3] PCI Express Switch SerDes Input PE0TP[1] PE0TN[1] PE0TP[3] PE0TN[3] PCI Express Switch SerDes Output ... MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Master SMBus Interface Slave SMBus Interface CCLKUS RSTHALT System Functions JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG VSS SWMODE[3:0] Port 0 Port 0 PE2TP[0] PE2TN[0] PE2RP[0] PE2RN[0] PE2RP[1] PE2RN[1] PE2RP[3] PE2RN[3] PCI Express Switch SerDes Input PE2TP[1] PE2TN[1] PE2TP[3] PE2TN[3] PCI Express Switch SerDes Output ... ...Port 2 Port 2 PE4TP[0] PE4TN[0] PE4RP[0] PE4RN[0] PE4RP[1] PE4RN[1] PE4RP[3] PE4RN[3] PCI Express Switch SerDes Input PE4TP[1] PE4TN[1] PE4TP[3] PE4TN[3] PCI Express Switch SerDes Output ... Port 4 Port 4 PES12N3A CCLKDS PERSTN REFCLKM MSMBSMODE VTTPE

11 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. AC Timing Characteristics Parameter Description Min Typical Max Unit RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. MHz RefclkDC Duty cycle of input clock 40 50 60 % TR, TF Rise/Fall time of input clocks 0.2*RCUI RCUI 3 3. RCUI (Reference Clock Unit Interval) refers to the reference clock period. VSW Differential input voltage swing4 4. AC coupling required. 0.6 1.6 V Tjitter Input clock jitter (cycle-to-cycle) 125 ps RT Termination Resistor 110 Ohms Table 9 Input Clock Requirements Parameter Description Min 1 Typical1 Max1 Units PCIe Transmit UI Unit Interval 399.88 400 400.12 ps TTX-EYE Minimum Tx Eye Width 0.7 .9 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.15 UI TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 90 ps TTX- IDLE-MIN Minimum time in idle 50 UI TTX-IDLE-SET-TO- IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 20 UI TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps PCIe Receive UI Unit Interval 399.88 400 400.12 ps T RX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 UI Table 10 PCIe AC Timing Characteristics (Part 1 of 2)

12 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-IDLE-DET-DIFF- ENTER TIME Unexpected Idle Enter Detect Threshold Integration Time 10 ms TRX-SKEW Lane to lane input skew 20 ns 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[7:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw_13b2 2. The values for this symbol were determined by calculation, not by testing. None 50 —n s Table 11 GPIO AC Timing Characteristics Parameter Description Min 1 Typical1 Max1 Units Table 10 PCIe AC Timing Characteristics (Part 2 of 2) Tpw_13b GPIO (synchronous output) GPIO (asynchronous input)

13 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Figure 5 JTAG AC Timing Waveform Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 5. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, reco mmends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 12 JTAG AC Timing Characteristics Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

14 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Recommended Operating Supply Voltages Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part duri ng power-up to ensure proper func tionality. For the PES12N3A, the power-up sequence must be as follows: 1. V DDI/O — 3.3V 2. V DDCore, VDDPE, VDDAPE — 1.0V 3. V TTPE — 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power le vels. The power-down sequence must be in the rev erse order of the power-up sequence. Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Am bient, 35% total link usage on all ports, typical voltages def ined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerDes LVPECL/CML 3.0 3.3 3.6 V VDDPE PCI Express Digital Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Seri al Data Transmit Termination Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 13 PES12N3A Operating Voltages Grade Temperature Commercial 0 °C to +70°C Ambient Industrial -40 °C to +85°C Ambient Table 14 PES12N3A Operating Temperatures

15 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Thermal Considerations This section describes thermal considerations for the PES12N3A (19mm2 BCG324 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES12N3A switch. Note: The parameter θJA(eff) is not the absolute thermal resistance for the package as defined by JEDEC (JESD-51). Because resistance can vary with the number of board layers, size of the board, and airflow, θJA(eff) is the effective thermal resistance. The values for effective θJA given above are based on a 10-layer, standard height, full length (4.3”x12.2”) PCIe add-in card. Heat Sink Table 17 lists heat sink requirements for the PES12N3A under three common usage scenarios. As shown in this table, a heat sink is not required in most cases. Number of active Lanes per Port Core Supply PCIe Digital Supply PCIe Analog Supply PCIe Termin- ation Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.5V Max 1.575V Typ 3.3V Max 3.6V Typ Power Max Power 4/4/4 mA 723 928 578 693 223 251 291 345 1 1 1.96W 2.6W 4/1/1 mA 618 746 398 458 207 223 142 160 1 1 1.44W 1.8W Table 15 PES12N3A Power Consumption Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oC Maximum for commercial-rated products θJA(effective) Effective Thermal Resistance, Junction-to-Ambient 21.8 oC/W Zero air flow 15.1 oC/W 1 m/S air flow 13.9 oC/W 2 m/S air flow θJB Thermal Resistance, Junction-to-Board 11.4 oC/W θJC Thermal Resistance, Junction-to-Case 5.1 oC/W P Power Dissipation of the Device 2.6 Watts Maximum Table 16 Thermal Specifications for PES12N3A, 19x19 mm BCG324 Package Air Flow Board Size Board Layers Heat Sink Requirement Zero 4.3”x12.2” (standard height, full length form factor) or larger 4 or more No heat sink required Zero Any 6 or more No heat sink required 1 m/S or more Any Any No heat sink required Table 17 Heat Sink Requirements Based on Air Flow and Board Characteristics

16 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Thermal Usage Examples The junction-to-ambient thermal resistance is a measure of a device’s ability to dissipate heat from the die to its surrounding s in the absence of a heat sink. The general formula to determine θJA is: θJA = (TJ - TA)/P Thermal reliability of a device is generally assured when the actual value of TJ in the specific system environment being considered is less than the maximum TJ specified for the device. Using an ambient temperature of 70oC and assuming a system with 1m/S airflow, the actual value of TJ is: TJ(actual) = TA + P * θJA(eff) = 70oC + 2.6W * 9.9W/oC = 96oC The actual TJ of 96oC is well below the maximum TJ of 125oC specified for the device (shown in Table 16). Therefore, no heat sink is needed in this scenario. The formula is also useful from a system design perspective. It can be used to determine if a heat sink should be added to the device based on some desired value of TJ. For example, if for reliability purposes the desired TJ is 100oC, then the maximum allowable TA is: TA(allowed) = TJ(desired) - (P * θJA(effective)) TA(allowed) = 100oC - (2.6W * 9.9W/oC) = 100oC - 26oC = 74oC An appropriate level of increased air flow and/or a heat sink can be added to achieve th is lower ambient temperature Please con tact ssdhelp@idt.com for further assistance.

17 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 mV VTX-DE-RATIO De-emphasized differential output voltage -3 -4 dB VTX-DC-CM DC Common mode voltage -0.1 1 3.7 V VTX-CM-ACP RMS AC peak common mode output volt- age 20 mV VTX-CM-DC- active-idle-delta Abs delta of DC common mode voltage between L0 and idle 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 mV VTX-RCV-Detect Voltage change during receiver detection 600 mV RLTX-DIFF Transmitter Differential Return loss 12 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120 Ω ZOSE Single ended TX Impedance 40 50 60 Ω Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 1200 mV VRX-CM-AC Receiver common-mode voltage for AC coupling 150 mV RLRX-DIFF Receiver Differential Return Loss 15 dB RLRX-CM Receiver Common Mode Return Loss 6 dB ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Ω ZRX-COMM-DC Single-ended input impedance 40 50 60 Ω ZRX-COMM-HIGH- Z-DC Powered down input common mode impedance (DC) 200k 350k Ω VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 mV PCIe REFCLK CIN Input Capacitance 1.5 — pF Table 18 DC Electrical Characteristics (Part 1 of 2)

18 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Other I/Os LOW Drive Output IOL —2 . 5— m A V OL = 0.4v IOH —- 5 . 5— m A V OH = 1.5V High Drive Output IOL —1 2 . 0— m A V OL = 0.4v IOH —- 2 0 . 0— m A V OH = 1.5V Schmitt Trig- ger Input (STI) VIL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Input V IL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Capacitance C IN —— 8 . 5 p F — Leakage Inputs — — + 10 μAV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 μAV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 μAV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Table 18 DC Electrical Characteristics (Part 2 of 2)

19 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet The following table lists the pin numbers and signal names for the PES12N3A device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS E10 V DDPE K1 V DDCORE P10 V DDIO A2 V SS E11 V SS K2 V SS P11 V DDIO A3 PE0RP03 E12 V DDPE K3 V TTPE P12 V DDIO A4 V DDCORE E13 V SS K4 V DDCORE P13 V DDIO A5 PE0TN03 E14 V DDCORE K5 V DDPE P14 V DDIO A6 V DDCORE E15 V DDAPE K6 V SS P15 V SS A7 PE0TP02 E16 V SS K7 V SS P16 V TTPE A8 V DDCORE E17 PE4TP03 K8 V SS P17 V SS A9 PE0RN02 E18 PE4TN03 K9 V SS P18 V DDCORE A10 V DDCORE F1 V DDCORE K10 V SS R1 PE2TN03 A11 PE0RP01 F2 V SS K11 V SS R2 PE2TP03 A12 V DDCORE F3 V DDCORE K12 V SS R3 V SS A13 PE0TP01 F4 V DDAPE K13 V SS R4 V DDIO A14 V DDCORE F5 V SS K14 V SS R5 V SS A15 V DDCORE F6 V DDCORE K15 V DDPE R6 V DDCORE A16 PE0TN00 F7 V SS K16 V TTPE R7 MSMBDAT A17 V SS F8 V DDCORE K17 V SS R8 SSMBADDR_5 A18 V SS F9 V SS K18 V DDCORE R9 NC B1 V DDCORE F10 V DDCORE L1 PE2RN02 R10 SWMODE_2 B2 V DDCORE F11 V SS L2 PE2RP02 R11 RSTHALT B3 PE0RN03 F12 V SS L3 V SS R12 GPIO_04 1 B4 V SS F13 V DDPE L4 V DDPE R13 V DDCORE B5 PE0TP03 F14 V SS L5 V SS R14 V SS B6 V SS F15 V DDIO L6 V DDCORE R15 V DDIO B7 PE0TN02 F16 V SS L7 V DDCORE R16 V SS B8 V SS F17 V SS L8 V DDCORE R17 PE4TP00 B9 PE0RP02 F18 V DDCORE L9 V DDCORE R18 PE4TN00 B10 V SS G1 PE2TP01 L10 V DDCORE T1 V DDCORE B11 PE0RN01 G2 PE2TN01 L11 V DDCORE T2 V SS B12 V SS G3 V SS L12 V DDCORE T3 V SS B13 PE0TN01 G4 V DDPE L13 V DDCORE T4 JTAG_TCK B14 V SS G5 V DDAPE L14 V SS T5 JTAG_TDO B15 V SS G6 V SS L15 V DDPE T6 MSMBADDR_1 B16 PE0TP00 G7 V SS L16 V SS T7 MSMBCLK Table 19 PES12N3A 324-pin Signal Pin-Out (Part 1 of 3)

20 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet B17 V DDCORE G8 V DDIO L17 PE4RP01 T8 SSMBADDR_2 B18 V DDCORE G9 V SS L18 PE4RN01 T9 CCLKDS C1 PE2RP00 G10 V DDIO M1 V DDCORE T10 SWMODE_1 C2 PE2RN00 G11 V SS M2 V SS T11 PERSTN C3 V SS G12 V DDCORE M3 V SS T12 GPIO_03 C4 V DDCORE G13 V SS M4 V DDAPE T13 GPIO_07 1 C5 V SS G14 V DDAPE M5 V SS T14 V SS C6 V TTPE G15 V DDPE M6 V DDCORE T15 REFCLKM C7 V SS G16 V SS M7 V SS T16 V SS C8 V TTPE G17 PE4TN02 M8 V SS T17 V SS C9 V SS G18 PE4TP02 M9 V DDCORE T18 V DDCORE C10 V TTPE H1 V DDCORE M10 V DDCORE U1 PE2RP03 C11 V SS H2 V SS M11 V SS U2 PE2RN03 C12 V TTPE H3 V TTPE M12 V SS U3 V SS C13 V DDCORE H4 V DDAPE M13 V DDCORE U4 JTAG_TDI C14 PE0RP00 H5 V SS M14 V SS U5 JTAG_TMS C15 PE0RN00 H6 V SS M15 V DDAPE U6 MSMBADDR_2 C16 V DDCORE H7 V DDCORE M16 V SS U7 MSMBADDR_4 C17 PE4RN03 H8 V SS M17 V SS U8 SSMBADDR_3 C18 PE4RP03 H9 V DDCORE M18 V DDCORE U9 CCLKUS D1 V DDCORE H10 V DDCORE N1 PE2TP02 U10 SWMODE_0 D2 V SS H11 V SS N2 PE2TN02 U11 NC D3 V SS H12 V DDCORE N3 V TTPE U12 GPIO_00 1 D4 V DDCORE H13 V SS N4 V DDAPE U13 GPIO_02 1 D5 V SS H14 V DDAPE N5 V SS U14 GPIO_06 D6 V DDAPE H15 V DDPE N6 V SS U15 MSMBSMODE D7 V SS H16 V TTPE N7 V SS U16 V SS D8 V DDAPE H17 V SS N8 V SS U17 PE4RN00 D9 V SS H18 V DDCORE N9 V SS U18 PE4RP00 D10 V DDAPE J1 PE2RP01 N10 V SS V1 V DDCORE D11 V SS J2 PE2RN01 N11 V SS V2 V SS D12 V DDAPE J3 V SS N12 V SS V3 PEREFCLKP1 D13 V SS J4 V DDPE N13 V SS V4 PEREFCLKN1 D14 V DDCORE J5 V SS N14 V SS V5 JTAG_TRST_N D15 V SS J6 V DDCORE N15 V DDAPE V6 MSMBADDR_3 D16 V SS J7 V SS N16 V TTPE V7 SSMBADDR_1 D17 V SS J8 V SS N17 PE4TN01 V8 SSMBCLK Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES12N3A 324-pin Signal Pin-Out (Part 2 of 3)

21 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Alternate Signal Functions D18 V DDCORE J9 V DDCORE N18 PE4TP01 V9 SSMBDAT E1 PE2TN00 J10 V DDCORE P1 V DDCORE V10 NC E2 PE2TP00 J11 V SS P2 V SS V11 SWMODE_3 E3 V DDCORE J12 V SS P3 V TTPE V12 V DDIO E4 V SS J13 V DDCORE P4 V SS V13 GPIO_01 1 E5 V DDCORE J14 V SS P5 V DDIO V14 GPIO_05 E6 V SS J15 V DDCORE P6 V DDIO V15 PEREFCLKP2 E7 V SS J16 V SS P7 V DDIO V16 PEREFCLKN2 E8 V DDPE J17 PE4RP02 P8 V DDIO V17 V SS E9 V SS J18 PE4RN02 P9 V DDIO V18 V DDCORE Pin GPIO Alternate U12 GPIO_00 P2RSTN V13 GPIO_01 P4RSTN U13 GPIO_02 IOEXPINTN0 R12 GPIO_04 IOEXPINTN2 T13 GPIO_07 GPEN Table 20 PES12N3A Alternate Signal Functions Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES12N3A 324-pin Signal Pin-Out (Part 3 of 3)

22 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Power Pins VDDCore V DDCore V DDCore V DDIO V DDPE V DDAPE V TTPE A4 F3 L8 F15 E8 D6 C6 A6 F6 L9 G8 E10 D8 C8 A8 F8 L10 G10 E12 D10 C10 A10 F10 L11 P5 F13 D12 C12 A12 F18 L12 P6 G4 E15 H3 A14 G12 L13 P7 G15 F4 H16 A 1 5H 1 M 1 P 8H 1 5G 5 K 3 B1 H7 M6 P9 J4 G14 K16 B2 H9 M9 P10 K5 H4 N3 B17 H10 M10 P11 K15 H14 N16 B18 H12 M13 P12 L4 M4 P3 C4 H18 M18 P13 L15 M15 P16 C13 J6 P1 P14 N4 C16 J9 P18 R4 N15 D1 J10 R6 R15 D4 J13 R13 V12 D14 J15 T1 D18 K1 T18 E3 K4 V1 E5 K18 V18 E14 L6 F1 L7 Table 21 PES12N3A Power Pins

23 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Ground Pins Vss Vss V ss V ss V ss A1 D15 G11 K10 N8 A2 D16 G13 K11 N9 A17 D17 G16 K12 N10 A18 E4 H2 K13 N11 B4 E6 H5 K14 N12 B6 E7 H6 K17 N13 B8 E9 H8 L3 N14 B10 E11 H11 L5 P2 B12 E13 H13 L14 P4 B14 E16 H17 L16 P15 B15 F2 J3 M2 P17 C3 F5 J5 M3 R3 C5 F7 J7 M5 R5 C7 F9 J8 M7 R14 C9 F11 J11 M8 R16 C11 F12 J12 M11 T2 D2 F14 J14 M12 T3 D3 F16 J16 M14 T14 D5 F17 K2 M16 T16 D7 G3 K6 M17 T17 D9 G6 K7 N5 U3 D11 G7 K8 N6 U16 D13 G9 K9 N7 V2 V17 Table 22 PES12N3A Ground Pins

24 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I T9 System CCLKUS I U9 GPIO_00 I/O U12 General Purpose Input/Output GPIO_01 I/O V13 GPIO_02 I/O U13 GPIO_03 I/O T12 GPIO_04 I/O R12 GPIO_05 I/O V14 GPIO_06 I/O U14 GPIO_07 I/O T13 JTAG_TCK I T4 JTAG JTAG_TDI I U4 JTAG_TDO O T5 JTAG_TMS I U5 JTAG_TRST_N I V5 MSMBADDR_1 I T6 SMBus MSMBADDR_2 I U6 MSMBADDR_3 I V6 MSMBADDR_4 I U7 MSMBCLK I/O T7 MSMBDAT I/O R7 MSMBSMODE I U15 System NC R9 PCI Express NC U11 NC V10 PE0RN00 I C15 PE0RN01 I B11 PE0RN02 I A9 PE0RN03 I B3 PE0RP00 I C14 PE0RP01 I A11 PE0RP02 I B9 PE0RP03 I A3 PE0TN00 O A16 Table 23 PES12N3A Alphabetical Signal List (Part 1 of 3)

25 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet PE0TN01 O B13 PCI Express (cont.) PE0TN02 O B7 PE0TN03 O A5 PE0TP00 O B16 PE0TP01 O A13 PE0TP02 O A7 PE0TP03 O B5 PE2RN00 I C2 PE2RN01 I J2 PE2RN02 I L1 PE2RN03 I U2 PE2RP00 I C1 PE2RP01 I J1 PE2RP02 I L2 PE2RP03 I U1 PE2TN00 O E1 PE2TN01 O G2 PE2TN02 O N2 PE2TN03 O R1 PE2TP00 O E2 PE2TP01 O G1 PE2TP02 O N1 PE2TP03 O R2 PE4RN00 I U17 PE4RN01 I L18 PE4RN02 I J18 PE4RN03 I C17 PE4RP00 I U18 PE4RP01 I L17 PE4RP02 I J17 PE4RP03 I C18 PE4TN00 O R18 PE4TN01 O N17 PE4TN02 O G17 PE4TN03 O E18 PE4TP00 O R17 Signal Name I/O Type Location Signal Category Table 23 PES12N3A Alphabetical Signal List (Part 2 of 3)

26 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet PE4TP01 O N18 PCI Express (cont.) PE4TP02 O G18 PE4TP03 O E17 PEREFCLKN1 I V4 PEREFCLKN2 I V16 PEREFCLKP1 I V3 PEREFCLKP2 I V15 PERSTN I T11 System REFCLKM I T15 PCI Express RSTHALT I R11 System SSMBADDR_1 I V7 SMBus SSMBADDR_2 I T8 SSMBADDR_3 I U8 SSMBADDR_5 I R8 SSMBCLK I/O V8 SMBus SSMBDAT I/O V9 SWMODE_0 I U10 System SWMODE_1 I T10 SWMODE_2 I R10 SWMODE_3 I V11 V DDCORE, VDDAPE, VDDIO, VDDPE, VTTPE See Table 21 for a listing of power pins. VSS See Table 22 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 23 PES12N3A Alphabetical Signal List (Part 3 of 3)

27 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet PES12N3A Pinout — Top View 1 2 3 4 5 6 7 8 9 1 01 1 1 21 31 4 1 51 6 Vss (Ground)VDDCore (Power) A B VDDI/O (Power) 17 18 C D E F G H J K L M N P R T U V VTTPE (Power) VDDPE (Power) VDDAPE (Power) Signals No Connection

28 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet

29 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet

30 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet

Revision History

February 8, 2007: Initial publication. April 4, 2007: In Table 3, revised description for MSMBCLK signal. May 30, 2007: Added ZG device revision to Ordering Information. November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements. March 27, 2008: In Table 16, Thermal Specifications, added θJB and θJC parameters and revised the values for θJA. August 7, 2008: Added revision 1ZC to Ordering Information page. February 19, 2009: Added industrial temperature to Table 14 and to Order page. April 9, 2010: Revised package drawing on pages 28 and 29.

31 of 31 April 9, 2010 IDT 89HPES12N3A Data Sheet CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208

Ordering Information

89HPES12N3AZCBC 324-pin BC324 package, Commercial Temp. 89HPES12N3A ZCBCI 324-pin BC324 package, Industrial Temp. 89HPES12N3AZGBC 324-pin BC324 package, Commercial Temp. 89H PES12N3AZGBCI 324-pin BC324 package, Industrial Temp. 89HPES12N3A1ZCBC 324-pin BC324 package, Commercial Temp. 89H PES12N3A1ZCBCI 324-pin BC324 package, Industrial Temp. 89HPES12N3AZCBCG 324-pin Green BC324 package, Commercial Temp. 8 9HPES12N3AZCBCGI 324-pi n Green BC324 package, Industrial Temp. 89HPES12N3AZGBCG 324-pin Green BC 324 package, Commercial Temp. 8 9HPES12N3AZGBCGI 324-pi n Green BC324 package, Industrial Temp. 89HPES12N3A1ZCBCG 324-pin Green BC 324 package, Commercial Temp. 89HPES12N3A1ZCBCGI 324-pin Green BC 324 package, Industrial Temp. NN A AAA NNAN AA A Operating Voltage Device Family Product Package Temp Range H Product Family

89 Serial Switching Product

12N3A 12-lane, 3-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character BCG324 324-ball CABGA, Green BCG AA Device Revision ZC ZC revision ZG ZG revision 1ZC 1ZC revision Blank Commercial Temperature (0°C to +70°C Ambient) I Industrial Temperature (-40° C to +85° C Ambient)

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