AS87C196CB20 INTEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 36
Technical content
Datasheet sections
- 1.0 Introduction
- 2.0 Block Diagram
- 3.0 Process Information
- 4.0 Pin Descriptions
- 5.0 Electrical Characteristics
- 5.1 DC Characteristics
- 5.1.1.1 MODE
- 5.1.1.2 MODE
- 5.2 AC Characteristics
- 5.2.1 Test Conditions
- 5.2.6 Explanation of AC Symbols
- 5.3 EPROM Specifications
- 5.3.1 AC EPROM Programming Characteristics
- 5.3.2 EPROM Programming Waveforms
- 5.4 AC Characteristics - Serial Port - Shift Register Mode
- 5.4.1 A/D Characteristics
- 5.4.1.1 A/D Converter Specification
- 6.0 Datasheet Revision History
87C196CB 20 MHz Advanced 16-Bit CHMOS Microcontroller with Integrated CAN 2.0 Automotive Production Datasheet Product Features J –40°C to +125°C Ambient J High Performance CHMOS 16-Bit CPU J Up to 56 Kbytes of On-Chip EPROM J Up to 1.5 Kbyte of On-Chip Register RAM J Up to 512 Bytes of Additional RAM (Code RAM) J Register-Register Architecture J 8 Channel/10-Bit A/D with Sample/Hold J 38 Prioritized Interrupts J Up to Seven 8-Bit (56) I/O Ports J Full Duplex Serial I/O Port with Dedicated Baud Rate Generator J Interprocessor Communication Slave Port J Oscillator Fail Detection Circuitry J 15 Message Objects of 8 Bytes Data Length J Up to 16 Mbyte Linear Address Space J High Speed Peripheral Transaction Server (PTS) J Two Dedicated 16-Bit High-Speed Compare Registers J 10 High Speed Capture/Compare (EPA) J Full Duplex Synchronous Serial I/O Port (SSIO) J Two Flexible 16-Bit Timer Counters J Flexible 8-/16-Bit External Bus (Programmable) J Programmable Bus (HLD/HLDA) J 1.4 µs 16 x 16 Multiply J 2.4 µs 32/16 Divide J 20 MHz Operation1 1. 16 MHz standard; 20 MHz is speed premium. J Supports CAN (Controller Area Network) Specification 2.0 Order No: 272405-007 August 2004 Notice: This document contains information on products in full production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 87C196CB - Automotive may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation PO Box 5937 Denver CO 80217-9808 call 1-800-548-4725 Copyright © Intel Corporation 1997, 2004 *Third-party brands and names are the property of their respective owners.
17 Slave Programming Mode Data Program Mode with Single Program Pulse .24
18 Slave Programming Mode in Word Dump or Data Verify Mode
19 Slave Programming Mode Timing in Data Program Mode
7 8xC196CB HOLD#/HOLDA# Timings (Ove r Specified Operation Conditions)17 18 10-Bit Mode A/D Characteristics (Usi ng Above Operating Conditions) (1) ....28
1.0 Introduction
Table 1. Device Overview
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2.0 Block Diagram
PWM and PWM toggle mode to be used in conjunction with the EPA, and an A/D scan mode. Figure 1. 87C196CB - Automotive Block Diagram
3.0 Process Information
All thermal impedance data is approximate for static air conditions at 1 W of power dissipation. Handbook (order number 240800) for a description of Intel's thermal impedance test methodology. Figure 2. The 87C196CB - Automotive Family Nomenclature Table 2. Thermal Characteristics
- ΘJA = Thermal resistance between junction and the surrounding environment (ambient) measurements are
taken 1 ft. away from case in air flow environment. ΘJV = Thermal resistance between junction and package face (case).
- All values of ΘJA and ΘJC may fluctuate depending on the environment (with or without airflow, and how
- and device power dissipation at temperature of operation. Typical variations are ± 2°C/W.
- Values listed are at a maximum power dissipation of 1 W.
- To address the fact that many of the package prefix variables have changed, all package prefix variables in
this document are now indicated with an "x".
Figure 3. 84-Pin PLCC xx87C196CB Diagram
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Figure 4. 100-Pin QFP xx87C196CB Diagram
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4.0 Pin Descriptions
Table 3. Pin Descriptions (Sheet 1 of 2) VCC Main supply voltage (+5 V). SS and a 1 MΩ resistor to VCC. If this function is not used, VPP may be tied to VCC. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. XTAL1 Input of the oscillator inverter and the internal clock generator. XTAL2 Output of the oscillator inverter. high for normal operation. RESET# has an internal pullup. 203EH. If not used, this pin should be tied to VSS. May be used by Intel Evaluation boards. = +12.5 V causes execution to begin in the Programming Mode. Selects between PLL mode or PLL bypass mode. This pin must be either tied high or low. and decrements when this pin is low. positive and negative edges of this pin. that of High Speed capture and compare. memory, or for bus sharing. If the pin is high, CPU operation continues in a normal manner. into the bus cycle is controlled by the CCR/CCR1. Also an LSIO if READY is not selected.
during 16-bit external. Also an LSIO pin when not BHE/WRH#. function is a Slave Port Interrupt Output Pin. or LSIO when not used as RD#. pin when not used as WR#/WRL#. Output high during an external memory read indicates the read is an instruction fetch. fetches, during internal EPROM fetches INST is held low. Also LSIO when not INST. select for external memory. ALE/ADV# is active only during external memory accesses. Also LSIO when not used as ALE. multiplexed address/data bus which has strong internal pullups. P2.7/CLKOUT Output of the internal clock generator. The frequency is the oscillator frequency. CLKOUT has a 50% duty cycle. Also LSIO pin when not used as CLKOUT. HLD# signal. Also LSIO when not used as HLDA#. bus. Also LSIO when not used as HLD#. the external bus. Also LSIO when not used as INTOUT#. controller has a pending external memory cycle. Also LSIO when not used as BREQ#. location 203CH. Also LSIO when not used as EXTINT. P2.1/RXD Receive data input pin for the Serial I/O port. Also LSIO if not used as RXD. P2.0/TXD Transmit data output pin for the Serial I/O port. Also LSIO if not used as TXD. T2CLK and T2DIR of the TIMER2 timer/counter. EPROM parts to select the Programming Mode. TXCAN Push-pull output to the CAN bus line. RXCAN High impedance input-only from the CAN bus line. Table 3. Pin Descriptions (Sheet 2 of 2)
Table 4. 87C196CB Memory Map FEFFFFH will Overlay Page 15 (0FH) for CB QFP package-External Memory.
900 Kbytes External Memory
- These areas are mapped internal EPROM if the REMAP bit (CCB2.2) is set and EA# = 5 V. Otherwise they
- Code executed in locations 0000H to 003FFH is forced external.
- Reserved memory locations must contain 0FFH unless noted.
- Reserved SFR bit locations must be written with 0.
- Refer to 8XC196CB Supplement to 8xC196NT User's Manual for SFR, CAN and Paging Descriptions.
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Figure 5. Chip Configuration Registers
1 Wait State
2 Wait States
3 Wait States
Designed to be similar to the 87C196KR bus timing with 1 automatic wait state. See AC Timings section for actual timings data. Mode 3 (KR): Designed to be similar to the 87C196KR bus timing. See AC Timings section for actual timings data.
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5.0 Electrical Characteristics
This includes VPP on ROM and CPU devices. datasheet before finalizing a design. may affect device reliability.
5.1 DC Characteristics
Table 5. DC Characteristics (Under Listed Operating Conditions) (Sheet 1 of 2) 2.Standard Input pins include XTAL1, EA#, RESET# and Port 1/2/5/6 when setup as inputs. 3.All Bidirectional I/O pins when configured as Outputs (Push/Pull). 4.Device is Static and should operate below 1 Hz, but only tested down to 4 MHz. temperature and VREF = VCC = 5 V. 6.Violating these specifications in reset may cause the device to enter test mode (P5.4 and P2.6). 7.When P0 is used as analog inputs, refer to A/D specifications for this characteristic. 8.For temperatures < 100°C typical is 10 µA.
Figure 6. 87C196CB ICC vs Frequency Table 5. DC Characteristics (Under Listed Operating Conditions) (Sheet 2 of 2) 2.Standard Input pins include XTAL1, EA#, RESET# and Port 1/2/5/6 when setup as inputs. 3.All Bidirectional I/O pins when configured as Outputs (Push/Pull). 4.Device is Static and should operate below 1 Hz, but only tested down to 4 MHz. temperature and VREF = VCC = 5 V. 6.Violating these specifications in reset may cause the device to enter test mode (P5.4 and P2.6). 7.When P0 is used as analog inputs, refer to A/D specifications for this characteristic. 8.For temperatures < 100°C typical is 10 µA.
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The 87C196CB - Automotive device has two bus timing modes for external memory interfacing.
5.1.1.1 MODE 3
5.1.1.2 MODE 0
5.2 AC Characteristics
5.2.1 Test Conditions
- Capacitive load on all pins = 100 pF
- Rise and Fall Times = 10 ns
Table 6. AC Characteristics (Over Specified Operating Conditions) (Sheet 1 of 2) 1.Testing performed at 4 MHz, however, the device is static by design and typically operates below 1 Hz. 2.Typical specifications, not guaranteed. 3.Assuming back-to-back bus cycles. operation is selected, add 2TOSC to specification. enables oscillator fail detection.
Table 6. AC Characteristics (Over Specified Operating Conditions) (Sheet 2 of 2) 1.Testing performed at 4 MHz, however, the device is static by design and typically operates below 1 Hz. 2.Typical specifications, not guaranteed. 3.Assuming back-to-back bus cycles. operation is selected, add 2TOSC to specification. enables oscillator fail detection.
Table 7. AC Characteristics (Over Specified Operating Conditions) 1.If Maximum is exceeded, additional wait states will occur. 2.If wait states are used, add 2 TOSC x n, where n = number of wait states.
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Figure 7. 87C196CB - Automotive System Bus Timing If mode 0 operation is selected, add 2 TOSC to this time.
Figure 8. 87C196CB - Automotive Ready Timings (One Wait State) add 2 TOSC to these specifications.
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Figure 9. 87C196CB Buswidth Timings If mode 0 selected, add 2 TOSC to these specifications.
Table 8. 8xC196CB HOLD#/HOLDA# Timings (Over Specified Operation Conditions)
- To guarantee recognition at next clock.
Figure 10. 87C196CB HOLD#/HOLDA# Timings
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Figure 11. Slave Port Waveform - (SLPL = 0) Table 9. Slave Port Timing - (SLPL = 0, 1, 2, 3)
- F OSC = 20 MHz
- T OSC = 60 ns
- Rise/Fall Time = 10 ns
- Capacitive Pin Load = 100 pF 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. SWLWH SRLDV SDVWH SWHQX SRHDZ
Figure 12. Slave Port Waveform - (SLPL = 1) Table 10. Slave Port Timing - (SLPL = 1, 2, 3)
- F OSC = 20 MHz
- T OSC = 60 ns
- Rise/Fall Time = 10 ns
- Capacitive Pin Load = 100 pF 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. Production Datasheet 19 87C196CB - Automotive SLLAX SRLDV SDVWH SWHQX SRHDZ
Table 11. Normal Master/Slave Operation
- Timings are guaranteed by design.
Table 12. Handshake Operation
- This specification refers to input clocks during slave operation. During master operation, the device outputs
a nominal 50% duty cycle clock. Figure 13. Synchronous Serial Port
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Figure 16. Float Test Conditions level occurs with IOL/IOH ≤ 15 mA.
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5.2.6 Explanation of AC Symbols
Table 14. Explanation of AC Symbols
5.3 EPROM Specifications
5.3.1 AC EPROM Programming Characteristics
- Load Capacitance = 150 pF
- T C = 25°C ± 5°C
- V REF = 5.0 V ± 0.25 V
- V CC = 5.0 V ± 0.25 V
- ANGND = 0 V
- V PP = 12.5 V ± 0.25 V
- V SS = 0 V
- F OSC = 5.0 MHz
Table 15. AC EPROM Programming Characteristics (Sheet 1 of 2)
2.Programming Specifications are not tested, but guaranteed by design. 3.This specification is for the word dump mode. For programming pulses use 300 TOSC + 100 µs. Table 16. DC EPROM Programming Characteristics Table 15. AC EPROM Programming Characteristics (Sheet 2 of 2)
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5.3.2 EPROM Programming Waveforms
Figure 17. Slave Programming Mode Data Program Mode with Single Program Pulse Figure 18. Slave Programming Mode in Word Dump or Data Verify Mode with Auto Increment
Figure 19. Slave Programming Mode Timing in Data Program Mode with Repeated Program
5.4 AC Characteristics - Serial Port - Shift Register Mode
- VSS = 0.0 V
- VCC = 5.0 V ±5%
- Load Capacitance = 100 pF
Table 17. Serial Port Timing - Shift Register Mode
Figure 20. Waveform - Serial Port - Shift Register Mode
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5.4.1 A/D Characteristics
as the equation for calculating the total conversion time, T, are shown in Figure 21. Figure 21. AD_TIME 1FAFH:Byte
5.4.1.1 A/D Converter Specification
The specifications given assume adherence to the operating conditions section of this data sheet. started, the device is placed in IDLE mode until the conversion is complete. Table 18. 10-Bit Mode A/D Operating Conditions
- VREF must be within+0.5 V of VCC.
2.The value of AD_TIME is selected to meet these specifications.
Table 19. 10-Bit Mode A/D Characteristics (Using Above Operating Conditions) (1)
0.009 LSB/C (2)
- All conversions performed with processor in IDLE mode.
- These values are expected for most parts at 25°C but are not tested or guaranteed.
- These values are not tested in production and are based on theoretical estimates and/or laboratory test.
- An “LSB”, as used here, has a value of approximately 5 mV
6.Multiplexer Break-Before-Make Guaranteed. 7.Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 8.Resistance from device pin, through internal MUX, to sample capacitor. Table 20. 8-Bit Mode A/D Operating Conditions
- VREF must be within+0.5 V of VCC.
2.The value of AD_TIME is selected to meet these specifications.
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Table 21. 8-Bit Mode A/D Characteristics (Using Above Operating Conditions) (1)
0.003 LSB/C (2)
- All conversions performed with processor in IDLE mode.
- These values are expected for most parts at 25°C but are not tested or guaranteed.
- These values are not tested in production and are based on theoretical estimates and/or laboratory test.
- An “LSB”, as used here, has a value of approximately 5 mV
6.Multiplexer Break-Before-Make Guaranteed. 7.Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 8.Resistance from device pin, through internal MUX, to sample capacitor.
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6.0 Datasheet Revision History
This is the -007 revision of the 87C196CB - Automotive datasheet. The following differences exist between the -008 and the -007 revision. 1. To address the fact that many of the package pr efix variables have changed, all package prefix variables in this document are now indicated with an "x". This is the -006 revision of the 87C196CB - Automotive datasheet. The following differences exist between the -005 and the -006 revision. 2. Table 4 - VOH1: Changed - Max value (was 2, now blank) to Min value (was blank, now 2). This is the -005 revision of the 87C196CB - Automotive datasheet. The following differences exist between the -004 and the -005 revision. 1. Converted to new template. 2. Corrected grammar. 3. Moved first page talbe and text paragraph to Introduction section. 4. Changed operating supply voltage specifications from 10% to 5%. 5. Removed all references to 87C196CA from data sheet. 6. Changed from “Advance Information” to “Production” data sheet. This is the -003 revision of the 87C196CB - Automotive data sheet. The following differences exist between the -002 version and the -003 revision. 1. The data sheet has been revised to ADV ANCE from PRELIMINARY , indicating the specifications have been verified through electrical tests. 2. The 87C196CB 100-ld QFP package and device pinout has been added to the data sheet. 3. The 87C196CB 100-ld QFP device supports up the 16 Mbyte of linear address space. 4. The package thermal characteristics for the PLCC packages was added to the data sheet, for 5. The AN87C196CB pin package diagram was corrected to show EA# as opposed to EA. 6. The REMAP bit function for CCB2 was corrected. Setting this bit to 0 selects EPROM/CODERAM in segment 0FFH only. Setting this bit to 1 selects both segment 0FFH and segment 00H. 7. TRLAZ has been changed to 5 ns from 20 ns. 8. TWLWH for the CA has been changed to TOSC –20 from TOSC –30. 9. TCLGX has been changed to 0 ns min, from TOSC –46 max. 10. . Timing specifications for the SSIO are now added. These timings are currently guaranteed by design. 11. . Added frequency designation to family nomenclature Figure 2. This is the -002 revision of the 87C196CA data sheet. The following difference exist between the -001 version and the -002 revision. 1. This data sheet now includes the specificatio ns for the 87C196CB as well as the 87C196CA.
- ABSOLUTE MAXIMUM RATINGS have been added. 3. Maximum Frequency has been increased to 20 MHz. 4. Maximum ICC has been increased from 75 mA to 100 mA for the CB, 90 mA for the CA. 5. Idle Mode current has been increased to 35 mA from 30 mA for the CB, 40 mA for the CA. 6. Input leakage current for Port 0 (ILI1) was decreased to 1.5 µA from 2.0 µA for the CA. 7. The electrical characteristics for the CAN module were removed. The electrical characteristics for TXCAN and RXCAN are identical to standard port pins. 8. TOSC (1/freq) was modified to reflect 20 Mhz timings. 9. TOFD (Oscillator Fail Detect Specification) for clock failure to RESET pin pulled low, was added to the data sheet (4 µs min, 40 µs max) 10. TWHQX has been increased to TOSC –25 ns min from TOSC –30 ns min. 11. TRXDX has been replaced by TRHDX. TRLAZ has been increased to 20 ns max from 5 ns max. 12. I PP programming supply current has been increased to 200 mA from 100 mA. 13. TCONV Conversion time for 10 bit A/D conversions has been decreased to reflect 20 Mhz operation. 14. RRST was added for the 87C196CA, min = 6 KΩ/max = 65 KΩ. 15. TCLLH–min/max parameters switched to accurately reflect this timing parameter. 16. TRLCL–Separate timings for the 87C196CA vs 87C196CB. TRLCL for the CB is min –8 ns, max +20 ns. For the CA, TRLCL min +4 ns/max +30 ns. 17. TRLRH changed to TOSC –10 ns from TOSC –5 ns. 18. TA VGV added for the 87C196CB. 19. TLLGV added for the 87C196CB. 20. TCLGX added for the 87C196CB. 21. TRLDV–Separate timings for 87C196CB.TRLDV max = TOSC –30 ns. For the 87C196CA, TRLDV max = TOSC – 22 ns. 22. HOLD/HOLDA timings added for the 87C196CB. 23. Slave Port Timings added for the 87C196CB. 24. Separate specifications for TPLPH for the 87C196CB, TPLPH, min = 100 TOSC. For the 87C196CA, TPLPH min = 50 TOSC. 25. Separate specifications for TPLDV for the 87C196CB, TPLDV min = 100 TOSC for the 87C196CA, TPLDV min = 50 TOSC. 26. 8-Bit mode A/D characteristics added.