8741004BGILF

8741004I RENESAS

Document overview

• Manufacturer or author: Integrated Device Technology
• PDF pages: 23

Technical content

Features

• Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs
• One differential clock input pair
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 35ps (maximum)
• Full 3.3V operating supply
• Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs
• -40°C to 85°C ambient operating temperature
• Available in lead-free packages Pin Assignment 24-Lead TSSOP, E-Pad 4.40mm x 7.8mm x 0.925mm package body G Package Top View BW_SEL 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~600kHz (default) 1 = PLL Bandwidth: ~2MHz nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL nc VDDA F_SELA VDD OEA nQB1 QB1 VDDO QB0 nQB0 IREF F_SELB OEB GND GND nCLK CLK 8741004I Data Sheet Differential-to-LVDS/0.7V Differential PCI Express™ Jitter Attenuator

2©2016 Integrated Device Technology, Inc Revision A January 27, 2016 8741004I Data Sheet Block Diagram F_SELA 0 ÷5 (default) 1 ÷4 F_SELB 0 ÷5 (default) 1 ÷4 VCO 490 - 640 MHz Phase Detector M = ÷5 (fixed) QA0 nQA0 QA1 nQA1 Pullup Pullup Pulldown Float Pulldown OEA OEB F_SELA F_SELB BW_SEL CLK nCLK MR IREF Pullup Pulldown Pulldown QB0 nQB0 QB1 nQB1 0 = ~200kHz Float = ~400kHz 1 = ~800kHz

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQA1, QA1 Output Differential ou tput pair. LVDS interface levels. 3, 22 V DDO Power Output supply pins. 4, 5 QA0, nQA0 Output Differential outp ut pair. LVDS interface levels.

6 MR Input Pulldown

are enabled. LVCMOS/LVTTL interface levels.

7 BW_SEL Input Pullup/

Pulldown PLL Bandwidth input. LVCMOS/LVTTL interface levels. See Table 3B. DDA Power Analog supply pin. 10 F_SELA Input Pulldown Frequency select pins for QAx/nQAx outputs. LVCMOS/LVTTL interface levels. See Table 3C. 11 V DD Power Core supply pin.

12 OEA Input Pullup

Output enable for QAx pins. When HIGH, QAx/nQAx outputs are enabled. When LOW, the QAx/nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. 13 CLK Input Pulldown Non-inverting differential clock input. 14 nCLK Input Pullup Inverting differential clock input. 15, 16 GND Power Power supply ground.

17 OEB Input Pullup

Output enable for QBx pins. When HIGH, QBx/nQBx outputs are enabled. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. 18 F_SELB Input Pulldown Frequency select pins for QBx/nQBx outputs. LVCMOS/LVTTL interface levels. See Table 3C.

19 IREF Input A fixed precision resistor (RREF = 475

reference current used for differential current-mode QB0/nQB0 clock outputs. 20, 21 nQB0, QB0 Output Differential ou tput pair. HCSL interface levels. 23, 24 QB1, nQB1 Output Differential ou tput pair. HCSL interface levels.

4©2016 Integrated Device Technology, Inc Revision A January 27, 2016 8741004I Data Sheet Function Tables Table 3A. Output Enable Function Table Table 3C. Frequency Select Table Table 3B. PLL Bandwidth Function Table Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Inputs Outputs OEA OEB QA[0:1]/nQA[0:1] QB[0:1]/nQB[0:1] 0 0 Hi-Z Hi-Z 1 1 Enabled Enabled Inputs DividerF_SEL[A, B] 0 ÷5 (default) 1÷ 4 Input PLL BandwidthBW_SEL 0 ~200kHz Float ~600kHz (default) 1~ 2 M H z Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 32.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.12 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 45 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 80 mA

5©2016 Integrated Device Technology, Inc Revision A January 27, 2016 8741004I Data Sheet Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage OEA, OEB, MR, F_SELA, F_SELB 2V DD + 0.3 V BW_SEL V DD – 0.3 V DD + 0.3 V VIL Input Low Voltage OEA, OEB, MR, F_SELA, F_SELB -0.3 0.8 V BW_SEL -0.3 +0.3 V VIM Input Mid Voltage BW_SEL V DD/2 – 0.1 V DD/2 + 0.1 V IIH Input High Current F_SELA, F_SELB, MR, BW_SEL VDD = VIN = 3.465V 150 µA OEA, OEB V DD = VIN = 3.465V 5 µA IIL Input Low Current MR, F_SELA, F_SELB, VDD = 3.465V, VIN = 0V -5 µA OEA, OEB, BW_SEL V DD = 3.465V, VIN = 0V -150 µA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current CLK V DD = VIN = 3.465V 150 µA nCLK V DD = VIN = 3.465V 5 µA IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA nCLK VDD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, NOTE 2 GND + 0.5 V DD – 0.85 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOD Differential Output Voltage 290 390 490 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.2 1.35 1.5 V VOS VOS Magnitude Change 50 mV

Table 5. 0.7V Differential AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.

7©2016 Integrated Device Technology, Inc Revision A January 27, 2016 8741004I Data Sheet Parameter Measurement Information 3.3V HCSL Output Load AC Test Circuit Differential Input Level Cycle-to-Cycle Jitter 3.3V LVDS Output Load AC Test Circuit Bank Skew LVDS Output Duty Cycle/Pulse Width/Period Measurement Point Measurement Point GND 2pF 2pF IREF VDDA VDD, VDDO 3.3V±5% 3.3V±5% nCLK CLK VDD GND VOS Cross Points V OD tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

nQA[0:1], nQB[0:1] QA[0:1], QB[0:1] 3.3V ±5% VDDA VDD, VDDO tsk(b) nQX0 QX0 nQX1 QX1 Where X is either Bank A or Bank B nQA[0:1], nQB[0:1] QA[0:1], QB[0:1]

8©2016 Integrated Device Technology, Inc Revision A January 27, 2016 8741004I Data Sheet Parameter Measurement Information, continued LVDS Output Rise/Fall Time Differential Output Voltage Setup Differential Measurement Points for Duty Cycle/Period Offset Voltage Setup Differential Measurement Points for Ringback HCSL Differential Measurement Points for Rise/Fall Time 20% 80% 80% 20% tR tF VOD Clock Outputs TSTABLE TSTABLE VRB VRB Q - nQ -150mV VRB = -100mV VRB = +100mV +150mV 0.0V SRCC - SRCT -150mV +150mV 0.0V Fall Edge RateRise Edge Rate

9©2016 Integrated Device Technology, Inc Revision A January 27, 2016 8741004I Data Sheet Parameter Measurement Information, continued Single-ended Measurement Points for Delta Cross Point Differential Measurement Points for Duty Cycle/Period Differential Measurement Points for Rise/Fall Matching nQ Q VCROSS_MEDIAN nQ Q VCROSS_MEDIAN VCROSS_MEDIAN +75mV VCROSS_MEDIAN -75mV tFALL tRISE

protection. A 1k  resistor can be used. pair should either be left floating or terminated. recommend that there is no trace attached. matched load termination of 100 across near the receiver input. it is recommended to terminate the unused outputs. Figure 4. Typical LVDS Driver Termination

of pad pattern for the leads to avoid any shorts. Figure 6. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)

This section provides information on power dissipation and junction temperature for the 8741004I. Equations and example calculations are also provided. The total power dissipation for the 741004I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. and a multi-layer board, the appropriate value is 32.1°C/W per Table 6 below. of board (single layer or multi-layer). Table 6. Thermal Resistance JA for 24 Lead TSSOP, E-Pad, Forced Convection

1. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 8. Figure 8. HCSL Driver Circuit and Termination dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX.

Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP, E-Pad

19©2016 Integrated Device Technology, Inc Revision A January 27, 2016 8741004I Data Sheet Package Outline and Package Dimension Package Outline - G Suffix for 24 Lead TSSOP, E-Pad Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 24 A 1.10 A1 0.05 0.15 A2 0.85 0.90 0.95 b 0.19 0.30 b1 0.19 0.22 0.25 c 0.09 0.20 c1 0.09 0.127 0.16 D 7.70 7.90 E 6.40 Basic E1 4.30 4.40 4.50 e 0.65 Basic L 0.50 0.60 0.70 P 5.0 5.5 P1 3.0 3.2  0° 8°  0.076 bbb 0.10

20©2016 Integrated Device Technology, Inc Revision A January 27, 2016 8741004I Data Sheet

Ordering Information

Table 9. Ordering Information

21©2016 Integrated Device Technology, Inc Revision A January 27, 2016 8741004I Data Sheet Revision History Sheet Rev Table Page Description of Change Date A T3C 4 16 & 17 Added F_SEL Function Table. Power Considerations - updated Power Dissipation section to coincide with updates to the Calculations & Equations section on page 17. 5/29/08 A T9 20 Removed leaded parts from Ordering Information table 11/15/12 A T9 Removed ICS from part numbers where needed. General Description - Deleted ICS chip. Ordering Information - Deleted quantity from tape and reel. Deleted LF note below table. Updated header and footer. 1/27/16

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