ICS8440259D-45 RENESAS

Document overview

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Technical content

FEMTOCLOCK™ CRYSTAL/LVCMOS-TO- LVDS/LVCMOS FREQUENCY SYNTHESIZER ICS8440259D-45 IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 1 ICS8440259DK-45 REV. A FEBRUARY 26, 2009 nQ0 nQ1 nQ2 nQ3 nQ4 Phase Detector VCO 490-680MHz OSC REF_CLK F_SEL nPLL_BYPASS XTAL_IN XTAL_OUT Pulldown 25MHz ÷32 ÷25 Pulldown Pullup GENERAL DESCRIPTION The ICS8440259D-45 is a 9 output synthesizer optimized to generate Gigabit and 10 Gigabit Ethernet clocks and is a member of the HiPerClockS™ family of high performance clock solutions from IDT. Using a 25MHz, 18pF parallel resonant crystal, the device will generate both 156.25MHz, 125MHz and 3.90625MHz clocks with mixed LVDS and LVCMOS/LVTTL output levels. The ICS8440259D-45 uses IDT’s 3 rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS8440259D-45 is packaged in a small, 5mm x 5mm VFQFN package that is optimum for applications with space limitations.

FEATURES

  • One differential LVDS output at 156.25MHz or 125MHz Four differential LVDS outputs at 125MHz Three LVCMOS/LVTTL single-ended outputs at 125MHz One LVCMOS/LVTTL single-ended output at 3.90625MHz
  • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input and PLL bypass from a single select pin
  • VCO range: 510MHz - 650MHz
  • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.34ps (typical), LVDS output
  • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.31ps (typical), LVDS output
  • Full 3.3V supply mode
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package HiPerClockS™ ICS PIN ASSIGNMENT BLOCK DIAGRAM V DDO_LVCMOS GND VDDO_LVCMOS GND nQ0 GND nQ1 VDDO_L VDS nQ2 GND nQ3 VDDO_LVDS nQ4 GND VDD VDDA nPLL_BYPASS VDD F_SEL REF_CLK XTAL_IN XTAL_OUT GND ICS8440259D-45 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS

IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 3 ICS8440259DK-45 REV. A FEBRUARY 26, 2009 ICS8440259D-45 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to V DDO_LVCMOS + 0.5V Outputs, IO (LVDS) Continuous Current 10mA Surge Current 15mA Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 37°C/W (0 mps) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_LVCMOS = VDDO_LVDS = 3.3V ± 5%,T A = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DD egatloVylppuSeroC5 31.33 .35 64.3V V ADD egatloVylppuSgolanAV DD 53.0–3 .3V DD V V ,SOMCVL_ODD V SDVL_ODD egatloVylppuStuptuO5 31.33 .35 64.3V I DD tnerruCylppuSrewoP 811A m I ADD tnerruCylppuSgolanA 53A m I SOMCVL_ODD tnerruCylppuStuptuOSOMCVL 01A m I SDVL_ODD tnerruCylppuStuptuOSDVL 061A m TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnI 2V DD 3.0+V V LI egatloVwoLtupnI 3.0-8 .0V I HI tnerruChgiHtupnI )DP(KLC_FERV DD V= NI V564.3=0 51A µ )UP(SSAPYB_LLPnV DD V= NI V564.3=5 A µ I LI tupnIt nerruCwoL )DP(KLC_FERV DD V,V564.3= NI V0=5 -A µ )UP(SSAPYB_LLPnV DD V,V564.3= NI V0=0 51-A µ V HO ;egatloVhgiHtuptuO 1ETON 8Q:5QI HO Am21-=6 .2V V LO ;egatloVwoLtuptuO 1ETON 8Q:5QI LO Am21=5 .0V 05htiwdetanimretstuptuO:1ETON Ω Vot SOMCVL_ODD ,noitamrofnItnemerusaeMretemaraPeeS.2/ .margaidtiucriCtseTdaoLtuptuO

TABLE 5. CRYSTAL CHARACTERISTICS TABLE 6. AC CHARACTERISTICS, VDD = VDDO_LVCMOS = VDDO_LVDS = 3.3V ± 5%,T A = 0°C TO 70°C

IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 5 ICS8440259DK-45 REV. A FEBRUARY 26, 2009 ICS8440259D-45 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 125MHZ (LVDS @ 3.3V) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz

IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 6 ICS8440259DK-45 REV. A FEBRUARY 26, 2009 ICS8440259D-45 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 156.25MHZ (LVDS @ 3.3V) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz

IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 7 ICS8440259DK-45 REV. A FEBRUARY 26, 2009 ICS8440259D-45 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 125MHZ (LVCMOS @ 3.3V) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz

IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 8 ICS8440259DK-45 REV. A FEBRUARY 26, 2009 ICS8440259D-45 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT PARAMETER MEASUREMENT INFORMATION VDD, VDDO_LVDS VDDA SCOPE Qx LVCMOS GND 1.65V±5% -1.65V±5% VDD, VDDO_LVCMOS 1.65V±5% VDDA RMS PHASE JITTER Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS 15pF 15pF VDD, VDDO_LVDS VDDA 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT WITH 18pF LVDS OUTPUT RISE/FALL TIME 20% 80% 80% 20% tR tF VOD nQ0:nQ4 Q0:Q4 30% 70% 70% 30% tR tF VOD nQ0:nQ4 Q0:Q4 LVDS OUTPUT RISE/FALL TIME

IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 9 ICS8440259DK-45 REV. A FEBRUARY 26, 2009 ICS8440259D-45 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER 100 out out LVDSDC Input VOD/Δ VOD VDD OFFSET VOLTAGE SETUP DIFFERENTIAL OUTPUT VOLTAGE SETUP out out LVDSDC Input ➤ VOS/Δ VOS VDD PARAMETER MEASUREMENT INFORMATION, CONTINUED LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD tPW tPERIOD tPW tPERIOD odc = x 100% nQ0:nQ4 tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q5:Q8 Q0:Q4 LVCMOS OUTPUT RISE/FALL TIME 20% 80% 80% 20% tR tF Q5:Q8

IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 10 ICS8440259DK-45 REV. A FEBRUARY 26, 2009 ICS8440259D-45 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8440259D-45 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA, VDDO_LVDS and V DDO_LVCMOS should be individually con- nected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illus- trates this for a generic V DD pin and also shows that V DDA re- quires that an additional 10 Ω resistor along with a 10µF by- pass capacitor be connected to the V DDA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING

FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) the package to maximize the thermal/electrical performance. for the leads to avoid any shorts. conduct from the surface of the PCB to the ground plane(s). power dissipation as well as electrical conductivity requirements. recommended to determine the minimum number needed. solder between the exposed pad/slug and the thermal land. These recommendations are to be used as a guideline only. Enhance Leadframe Base Package, Amkor Technology. FIGURE 4. TYPICAL LVDS DRIVER TERMINATION are used, it is recommended to terminate the unused outputs.

100 Ohm Differential Transmission Line

IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 13 ICS8440259DK-45 REV. A FEBRUARY 26, 2009 ICS8440259D-45 FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8440259D-45. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS840259D-45 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVDS Output Power Dissipation

  • Power (core, LVDS) = V DD_MAX * (I DD + I DDO_LVDS + I DDA ) = 3.465V * (118mA + 160mA + 35mA) = 1084.545mW LVCMOS Output Power Dissipation
  • Power (LVCMOS, no-load) = V DD_MAX * I DDO_LVCMOS = 3.465V * 10mA = 34.65mW
  • Output Impedance R OUT Power Dissipation due to Loading 50 Ω to V DDO Output Current I OUT = VDDO_MAX / [2 * (50 Ω + ROUT)] = 3.465V / [2 * (50 Ω + 25Ω)] = 23.1mA
  • Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 25 Ω * (23.1mA) 2 = 13.3mW per output
  • Total Power Dissipation on the R OUT Total Power (ROUT) = 13.3mW * 4 = 53.2mW
  • Dynamic Power Dissipation at 125MHz Power (125MHz) = C PD * Frequency * (V DDO)2 = 15pF * 125MHz * (3.465V) 2 = 22.5mW per output Total Power (125MHz) = 22.5mW * 3 = 67.5mW
  • Dynamic Power Dissipation at 3.9MHz Power (3.9MHz) = CPD * frequency * (V DDO)2 = 15pF * 3.90625MHz * (3.465V) 2 = 0.7mW per output Total Power Dissipation
  • Total Power = Power (core, LVDS) + Power (LVCMOS-no load) + Total Power (R OUT) + Total Power (125MHz) + Total Power (3.9MHz) = 1240.595mW

TABLE 7. THERMAL RESISTANCE θ θθ θθJA FOR 32-LEAD VFQFN, FORCED CONVECTION In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 7. flow, and the type of board (multi-layer).

TABLE 8. θ

TABLE 9. PACKAGE DIMENSIONS is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front pa ge.

TABLE 10. ORDERING INFORMATION

FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

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San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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