83C51KB INTEL
Document overview
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Technical content
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have minor varia- tions to this specification known as errata. COPYRIGHT © INTEL CORPORATION, 1996 March 1996 Order Number: 272800-001 83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER The 83C51KB is a highly integrated keyboard microcontroller for the standard and advanced desktop keyboard industry. The integration of external components into the microcontroller reduces overall keyboard control system manufacturing cost in terms of the number of components used, the amount of PCB space required, reduced inventory, and a reduction in required assembly activities. In addition, the integration reduces the number and amount of software routines needed for signal debounce and input status poll operation. There is a resultant reduction in CPU overhead as well as on-chip memory requirements. The 83C51KB product line is manufactured with Intel state of the art complimentary high-performance metallic oxide semiconductor (CHMOS) design rules. ■ Direct Drive LED Outputs — Four Pins (P3.7:4) — 13 mA Typical Current Sink Capability ■ 20 pF Cap On-chip for RC Resonator — Frequency Selectable (4-6 MHz) ■ 8 Dedicated Key Scan Input (KSI) Pins — Schmitt-trigger Inputs — External Interrupt — Level Detect Interrupt Mode for Automatic Power-down Exit ■ 16 Dedicated Key Scan Output (KSO) Pins with Quasi-bidirectional Port Drivers — No External Resistor Required — Located on P0.7:0 and P2.7:0 ■ 4-Kbyte On-chip ROM Memory ■ 128-byte On-chip RAM Memory ■ Clock/Data Drivers to Motherboard — Strong Pullup Drivers for Keyboard Cable Communication — 8X42 Compatible Interface — Selectable external interrupt for Clock ■ ONCE mode (On-chip Emulation) ■ Power-on Reset Mode — Automatic Operation ■ 5 Volt D.C. Operation ■ Reduces Manufacturing Cost by Reducing Overall Component Count ■ Configurable Timer (16 bit or 2 by 8 Bit) ■ Uses Industry Standard Design Tools ■ Control Oriented Instruction Set ■ Industry Standard Architecture
Figure 1. 83C51KB Block Diagram
1.0 TEMPERATURE RANGE
2.0 PROCESS INFORMATION
thermal impedance test methodology. Table 1. Thermal Characteristics
Figure 2. 83C51KB 40-pin DIP Diagram Table 2. 83C51KB Nomenclature Definitions
4 Kbytes ROM
Table 3. 83C51KB Memory Map 0000H 4-Kbyte on-chip code memory array.
- The special function registers (SFRs) are accessible by direct addressing only.
- Data in this area is accessible by indirect addressing only.
- RD#/WR# active for these external data addresses.
- PSEN# active for the external code addresses.
- Addresses 20H through 2FH are bit addressable.
5.0 SIGNAL DESCRIPTION
Table 4. 40-pin DIP Signals Arranged by Name
Table 5. 40-pin DIP Signals Arranged by Pin Number
9 RST 29 PSEN#
Table 6. 83C51KB Signal Description Keyboard Scan Inputs. Application specific keyboard signals. alternate functions are not available for keyboard applications. No Connection Signal. This signal is to be unconnected. P1.7:0 I/O Port 1. This is an 8-bit quasi-bidirectional I/O port (see KSI signals). standard MCS 51 microcontrollers. They are not used for these functions in keyboard applications.
memory fetch operations. It is not available for keyboard applications. RD# † O Read . Read signal output for external data memory read operations. It is not available for keyboard applications. mode returns the chip to normal operation. This signal is input only. WR# † O Write. Write signal output for external data memory write operations. It is not available for keyboard applications. standard MCS 51 microcontrollers. They are not used for these functions in keyboard applications.
83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
6.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS † Ambient Temperature under Bias: Voltage on Any Pin to V NOTE: Maximum power dissipation is based on package heat-transfer limitations, not device power consumption. OPERATING CONDITIONS TA (Ambient Temperature Under Bias): NOTICE : This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. †WARNING: Stressing the device beyond the “Absolute Max- imum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Condi- tions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
Figure 3. RCIN Frequency NOTE: RC resonator accuracy is ± 5% at fixed VCC and temperature using a 1% external precision resistor.
Figure 4. RC Oscillator
Table 7. D.C. Characteristics
- Typical values are obtained using VCC =5.0V, TA=25°C and are not guaranteed.
- Under steady state (non-transient) conditions, IOL must be externally limited as follow:
to sink current greater than the listed test conditions.
- Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed
desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic.
- Capacitive loading on Ports 0 and 2 cause the V
specification when the address lines are stabilizing.
Table 7. D.C. Characteristics (Continued)
- Typical values are obtained using VCC =5.0V, TA=25°C and are not guaranteed.
- Under steady state (non-transient) conditions, IOL must be externally limited as follow:
to sink current greater than the listed test conditions.
- Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed
desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic.
- Capacitive loading on Ports 0 and 2 cause the V
specification when the address lines are stabilizing.
Figure 5. External Clock Drive
- Typical values are obtained using VCC =5.0V, TA=25°C and are not guaranteed.
- Under steady state (non-transient) conditions, IOL must be externally limited as follow:
to sink current greater than the listed test conditions.
- Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed
desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic.
- Capacitive loading on Ports 0 and 2 cause the V
specification when the address lines are stabilizing.
0.7 VCC
Table 8. A.C. Characteristics (Note 1, 2)
- Rise time and fall time = 20ns for external clock drive
POR timing begins when the voltage exceeds the VPOR crossover voltage.
83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
6.3 External Program Memory Read Cycle Waveform
6.4 External Program Memory Read Cycle External Data Memory Read Cycle Waveform
PSEN# TLLAX TLHLL TAVIV TPXIZ PORT 0 A8 - A15PORT 2 A8 - A15 A0 - A7 A0 - A7 Instruction In TLLIV TPLIV TLLPL TAVLL TPLPH TPXIX TPLAZ A4254-01 A4255-01 ALE PSEN# TLLAX TLHLL TAVDV TRHDZ PORT 0 P2.0 - P2.7 or A8 - A15 from DPHPORT 2 A8 - A15 from PCH A0-A7 from RI or DPL A0 - A7 from PCLData In TWHLH RD# TRHDX TAVWL Instr. In TRLDVTAVLL TLLWL TLLDV TRLRH TRLAZ
6.5 External Data Memory Read Cycle External Data Memory Write Cycle Waveform
Figure 6. External Data Memory Write Cycle
6.6 Testing Characteristics
Figure 7. Float Waveforms
Table 9. 83C51KB Signature Byte Values a min of VIH for a logic 1 and VOL for a logic 0.