Power Management

82P33714

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The 82P33714 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) provides tools to manage timing references,

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Selected specification: Renesas Technology Corp

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Online Datasheet

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82P33714 RENESAS

Document overview

Manufacturer or author: IDT
PDF pages: 63

Technical content

Datasheet sections

Features

Differential reference inputs (IN1 to IN4) accept clock frequencies between 1 PPS and 650 MHz
Single ended inputs (IN5 to IN6) accept reference clock frequencies between 1 PPS and 162.5 MHz
Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any clock reference input
Reference monitors qualify/disqualify references depending on activ- ity, frequency and LOS pins
Automatic reference selection state machines select the active refer- ence for each DPLL based on the refer ence monitors, priority tables, revertive and non-revertive settings and other programmable settings
Fractional-N input dividers enable the DPLLs to lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI, and GNSS fre- quencies
Any reference inputs (IN1 to IN6) can be designated as external sync pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select- able reference clock input
FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses that are aligned with the selected ex ternal input sync pulse input and frequency locked to the associated reference clock input
DPLL1 can be configured with bandwidths between 0.09 mHz and 567 Hz
DPLL1 locks to input references with frequencies between 1 PPS and

650 MHz

DPLL2 locks to input references with frequencies between 8 kHz and
DPLL1 complies with ITU-T G.8262 for Synchronous Ethernet Equip- ment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC); and Telcordia GR-253-CORE / GR-1244-CORE for Stratum 3 and SONET Minimum Clock (SMC)
DPLL1 generates clocks with PDH, TDM, GSM, CPRI/OBSAI, 10/100/

1000 Ethernet and GNSS frequencies; thes e clocks are directly avail-

DPLL2 generates N x 8 kHz clocks up to 100 MHz that are output on OUT9 and OUT10
APLL1 and APLL2 are connected to DPLL1
APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or SONET/SDH frequencies
Any of eight common TCXO/OCXO frequencies can be used for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
The I2C slave, SPI or the UART interface can be used by a host pro- cessor to access the control and status registers
The I2C master interface can autom atically load a device configura- tion from an external EEPROM after reset
Differential outputs OUT3 to OU T6 output clocks with frequencies between 1 PPS and 650 MHz
Single ended outputs OUT1, OUT2, OUT7 and OUT8 output clocks with frequencies between 1 PPS and 125 MHz
Single ended outputs OUT9 and OUT10 output clocks N*8 kHz multi- ples up to 100 MHz
DPLL1 supports independent programm able delays for each of IN1 to IN6; the delay for each input is pr ogrammable in steps of 0.61 ns with a range of ~±78 ns
The input to output phase delay of DPLL1 is programmable in steps of 0.0745 ps with a total range of ±20 s
The clock phase of each of the output dividers for OUT1 (from APLL1) to OUT8 is individually programmable in steps of ~200 ps with a total range of +/-180°
1149.1 JTAG Boundary Scan
72-QFN green package

Applications

Access routers, edge routers, core routers
Carrier Ethernet switches
Multi-service access platforms
PON OLT
LTE eNodeB
ITU-T G.8264 Synchronous Equi pment Timing Source (SETS)
ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC)
ITU-T G.813 Synchronous Equipment Clock (SEC)
Telcordia GR-253-CO RE/GR1244-CORE Stratum 3 Clock (S3) and SONET Minimum Clock (SMC) Synchronous Equipment Timing Source for Synchronous Ethernet 82P33714 Datasheet

Description

The 82P33714 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE ) provides tools to manage timing refere nces, clock generation and timing paths for SyncE based clocks, per ITU-T G.8264 and ITU-T G.8262. 82P33714 meets the requirements of ITU-T G.8262 for synchronous Ethernet Equipment Clocks (EECs) and ITU-T G.813 for Synchronous Equipment Clocks (SEC). The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces. The 82P33714 accepts four differential reference inputs and two single ended reference inputs that can operate at common GNSS, Ethernet, SONET/SDH and PDH frequencies that range from 1 Pulse Per Second ( PPS) to 650 MHz. The references are continually monitored for loss of sig- nal and for frequency offset per user programmed thresholds. All of the references are available to both Digital PLLs (DPLLs). The active reference for each DPLL is determined by forced selection or by automatic sele ction based on user programmed pr iorities and locking allowance s and based on the reference monitors and LOS inputs. The 82P33714 can accept a clock reference and an associated phase lock ed sync signal as a pair. DPLL1 can lock to the clock ref erence and align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended reference inputs to be configured as sync inputs that can be associated with an y of the other differential or single ended reference inputs. The input sync signals can have a frequency of 1 PPS, 2 kHz, 4 kHz or 8 kHz. This feature enables DPLL1 to phase align its frame sync and multi-frame sync outputs with a sync input without the need use a low bandwidth setting to lock directly to the sync input. The DPLLs support three primary operating m odes: Free-Run, Locked and Holdover. In Free- Run mode the DPLLs synthesize clocks ba sed on the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term output fre- quency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL use s frequency data acquired while in Locked mode to generate accurate frequencies when input references are not available. DPLL1 also supports DCO mode. In DCO mode the DPLL control loop is opened and the DCO can be controlled by an IEEE 1588 clock recovery servo running on an external processor to synthesize IEEE 1588 clocks. The 82P33714 requires a system clock for its re ference monitors and other digital circuitry. The fr equency accuracy of the syst em clock deter- mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequenc y stability of the DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked mode. When used with a suitable system clock, DPLL1 meets the frequenc y accuracy, pull-in, hold-in, pul lout, noise generation, noise tolerance, tran- sient response, and holdover performance requirements of the fo llowing applications: ITU-T G.8262/G.813 EEC/SEC options 1 and 2, Telcordia GR- 1244 Stratum 3 (S3), Telcordia GR-253-CORE S3 and SONET Minimum Clock (SMC). DPLL1 can be configured with a range of selectable filtering bandwidths from 0.09 MHz to 567 Hz. The 17 MHz bandwidth can be used to lock the DPLL directly to a 1 PPS reference. The 92 MHz bandwidth can be used for G.8262/G.813 Option 2, or Telcordia GR-253-CORE S3, or SMC applica- used for Telcordia GR-1244-CORE S3 applications. Bandwidths above 10 Hz can be used in jitter attenuation and rate conversion applications. DPLL2 is a wideband (BW > 25Hz) frequency translator that can be used, for example, to convert a recovered line clock to a 1.54 4 MHz or 2.048 MHz synchronization interface clock. For SETS applications per ITU-T G.8264, DPLL1 is configured as an EEC/SEC to output clocks for the T0 reference point and DPLL2 is used to output clocks for the T4 reference point. Clocks generated by DPLL1 can be passed thr ough APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The o utput clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces. All 82P33714 control and status registers are accessed through an I2C slave, SPI or UART interface. For configuring the DPLLs, APLL1 and APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset.

Figure 1. Functional Block Diagram

1 PIN ASSIGNMENT

Figure 1. Pin Assignment (Top View)

2 PIN DESCRIPTION

Table 1: Pin Description Pin No. Name I/O Type Description Global Control Signal 6O S C I I C M O S OSCI: Crystal Oscillator System Clock A clock provided by a crystal oscillator is input on this pin. It is the system clock for the device. The oscillator frequency is selected via pins XO_FREQ0 ~ XO_FREQ2

58 MS/SL I

MS/SL: Master / Slave Selection This pin, together with the MS_SL_CTRL bit, controls whether the device is configured as the Master or as the Slave. The signal level on this pin is reflected by the MASTER_SLAVE bit. MS_SL = 0: Slave MS_SL = 1: Master (default with internal pull-up)

59 SONET/SDH/

I pull-down CMOS SONET/SDH: SONET / SDH Frequency Selection During reset, this pin determines the default value of the IN_SONET_SDH bit: High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET); Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH). After reset, the value on this pin takes no effect. LOS3- This pin is used to disqualify input clocks. See input clocks section for more details.

52 RSTB I

pull-up CMOS RSTB: Reset Refer to section 2.2 reset operation for details. XO_FREQ0/ LOS0 XO_FREQ1/ LOS1 XO_FREQ2/ LOS2 I pull-down CMOS XO_FREQ0 ~ XO_FREQ2: These pins set the oscillator frequency. XO_FREQ[2:0] Oscillator Frequency (MHz) 000 10.000 001 12.800 010 13.000 011 19.440 100 20.000 101 24.576 110 25.000 111 30.720 LOS0 ~ LOS2 - These pins are used to disqualify input clocks. See input clocks section for more details. After reset, this pin takes on the operation of LOS0-LOS2 Input Clock and Frame Synchronization Input Signal IN1_POS IN1_NEG I PECL/LVDS IN1_POS / IN1_NEG: Positive / Negative Input Clock 1 A reference clock is input on this pin. This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN2_POS IN2_NEG I PECL/LVDS IN2_POS / IN2_NEG: Positive / Negative Input Clock 1 A reference clock is input on this pin. This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN3_POS IN3_NEG I PECL/LVDS IN3_POS / IN3_NEG: Positive / Negative Input Clock 3 A reference clock is input on this pin. This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin. IN4_POS IN4_NEG I PECL/LVDS IN4_POS / IN4_NEG: Positive / Negative Input Clock 4 A reference clock is input on this pin. This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

37 IN5 I

IN5: Input Clock 5 A reference clock is input on this pin. This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

41 IN6 I

IN6: Input Clock 6 A reference clock is input on this pin. This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

43 FRSYNC

_8K_1PPS OC M O S FRSYNC_8K_1PPS: 8 kHz Frame Sync Output An 8 kHz signal or a 1PPS sync signal is output on this pin.

44 MFRSYNC

_2K_1PPS OC M O S MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output A 2 kHz signal or a 1PPS sync signal is output on this pin. Output Clock OUT1 OUT2 OC M O S OUT1 ~ OUT2: Output Clock 1 ~ 2 OUT3_POS OUT3_NEG O PECL/LVDS OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3 This output is set to LVDS by default. OUT4_POS OUT4_NEG O PECL/LVDS OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4 This output is set to LVDS by default. OUT5_POS OUT5_NEG O PECL/LVDS OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5 This output is set to LVDS by default. OUT6_POS OUT6_NEG O PECL/LVDS OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6 This output is set to LVDS by default. OUT7 OUT8 OC M O S OUT7 ~ OUT8: Output Clock 7 ~ 8 OUT9 OUT10 OC M O S OUT9 ~ OUT10: Output Clock 9 ~ 10 Miscellaneous

13 VC1 O Analog

VC1: APLL1 VC Output An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in parallel) should be connected to this pin. 1V C 2 O A n a l o g VC2: APLL2 VC Output An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in parallel) should be connected to this pin. Lock Signal

54 DPLL2_LOCK OC M O S DPLL2_LOCK

This pin goes high when DPLL2 is locked

55 DPLL1_LOCK OC M O S DPLL1_LOCK

This pin goes high when DPLL1 is locked Microprocessor Interface

57 INT_REQ O

Tri-state CMOS INT_REQ: Interrupt Request This pin is used as an interrupt request. MPU_MODE1/ I2CM_SCL MPU_MODE0/ I2CM_SDA I/O pull-up CMOS/ Open Drain MPU_MODE[1:0]: Microprocessor Interface Mode Selection During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol- lows: 00: I2C mode 01: SPI mode 10: UART mode 11: I2C master (EEPROM) mode I2CM_SCL: Serial Clock Line In I2C master mode, the serial clock is output on this pin. I2CM_SDA: Serial Data Input for I2C Master Mode In I2C master mode, this pin is used as the input for the serial data. Table 1: Pin Description (Continued) Pin No. Name I/O Type Description

47 SDI/I2C_AD2/

UART_RX I pull-down CMOS SDI: Serial Data Input In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri- ally clocked into the device on the rising edge of SCLK. I2C_AD2: Device Address Bit 2 In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface. UART_RX In UART mode, this pin is used as the receive data (UART Receive)

48 CLKE/I2C_AD1 I

CLKE: SCLK Active Edge Selection In Serial mode, this pin is an input, it selects the active edge of SCLK to update the SDO: High - The falling edge; Low - The rising edge. I2C_AD1: Device Address Bit 1 In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.

49 CS/I2C_AD0 I

CS: Chip Selection In Serial modes, this pin is an input. A transition from high to low must occur on this pin for each read or write operation and this pin should remain low until the operation is over. I2C_AD0: Device Address Bit 0 In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.

50 SCLK/I2C_SCL I

SCLK: Shift Clock In Serial mode, a shift clock is input on this pin. Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated on the active edge of SCLK. The active edge is determined by the CLKE. I2C_SCL: Serial Clock Line In I2C mode, the serial clock is input on this pin. SDO/I2C_SDA/ UART_TX I2C_SDA I/O pull-up CMOS/ Open Drain SDO: Serial Data Output In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked out of the device on the active edge of SCLK. I2C_SDA: Serial Data Input/Output In I2C mode, this pin is used as the input/output for the serial data. UART_TX: In UART mode, this pin is used as the transmit data (UART Transmit) JTAG (per IEEE 1149.1)

14 TMS I

TMS: JTAG Test Mode Select The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK.

15 TRSTB I

TRSTB: JTAG Test Reset (Active Low) A low signal on this pin resets the JTAG test port. This pin should be connected to ground when JTAG is not used.

16 TCK I

TCK: JTAG Test Clock The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is updated on the falling edge of TCK. If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely retain their state.

17 TDI I

TDI: JTAG Test Data Input The test data are input on this pin. They are clocked into the device on the rising edge of TCK. Table 1: Pin Description (Continued) Pin No. Name I/O Type Description

2.1 RECOMMENDATIONS FOR UNUSED INPUT

2.1.1 INPUTS

All control pins have internal pul l-ups or pull-downs; additional resis- tance is not required but can be added for additional protection. A 1k Ω resistor can be used. Single-Ended Clock Inputs For protection, unused single- ended clock inputs should be tied to ground. Differential Clock Inputs For applications not requiring the use of a differential input, both *_POS and *_NEG can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from _POS to ground.

2.1.2 OUTPUTS

For applications not requiring the use of a status pin, we recommend bringing out to a test point for debugging purposes. Single-Ended Clock Outputs All unused single-ended clock outputs can be left floating, or can be brought out to a test point for debugging purposes. Differential Clock Outputs All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.

2.2 RESET OPERATION

The device must be reset properly in order to ensure operations conform with specification. To properly reset the device, the RSTB pin must be held at a low value for at least 50 usec. The device should be brought out of reset only at the time when power s upplies are stabilized and the system clock is available on OSCi pin. The RSTB can be held low until this time, or pulsed low for at least 50us after this time. The bootstrap pins (XO_FREQ[2:0], MPU_MODE[1:0], I2C_AD[2:0], MS/SL, SONET/SDH) need to be held at desired states for at least 2ms after de-assertion of RSTB pin to al low correct sampling. See Figure 3 for detail. If loading from an EEPROM, the maximum time from RSTB de- assert to have stable clocks is 100ms. Note that if there is a bad EEPROM read sequence and the EEPROM loading is repeated once or twice (three times halts the device), then this time can be 2 or 3 times longer respectively. If not loadi ng from EEPROM the maximum time from RSTB de-assert to have stable clocks is 10ms. An on-board reset circuit or a commercially available voltage supervisory can be used to generate t he reset signal. It is also feasible to use a standalone power-up RC rese t circuit. When using a power-up RC reset circuit, careful consideration must be taken into account to fine tune the circuit properly based on eac h power supply's specification to ensure the power supply rise time is fast enough with respect to the RC time constant of the RC circuit.

18 TDO O

TDO: JTAG Test Data Output The test data are output on this pin. They are clocked out of the device on the falling edge of TCK. TDO pin outputs a high impedance signal except during the process of data scanning. Power & Ground 2, 3, 4, 5, 10 11, 12 VDDA Power - VDDA: Analog Core Power - +3.3V DC nominal 20, 24, 69, 72 VDDAO Power VDDAO: Analog Output Power - +3.3V DC nominal 27, 29, 64, 66 VDDDO Power VDDDO: Digital Output Power - +3.3V DC nominal 40, 62 VDDD Power VDDD: Digital Core Power - +3.3V DC nominal 42, 53 VDDD_1_8 Power VDDD_1_8: Digital Core Power - +1.8V DC nominal 19,23 VSSAO Ground VSSAO: Ground 73 (e_PAD) VSS Ground - VSS: Ground Other

56 IC - - IC: Internal Connection

Internal Use. This pin must be left open for normal operation. Table 1: Pin Description (Continued) Pin No. Name I/O Type Description

Figure 2. Reset timing diagram

2.3 MS/SL PIN USAGE

for SETS and SMU Devices on Timing Redundancy Designs.

3 FUNCTIONAL DESCRIPTION

3.1 SYNCHRONOUS ETHE RNET, SONET, AND

ITU-T Recommendation G.8262, Ti ming characteristics of Syn- chronous Ethernet Equipment slave clock (EEC)
ITU-T Recommendation G.8264, Di stribution of timing through packet networks
ITU-T Recommendation G.812, Ti ming requirements of slave clocks suitable for use as node clocks in synchronization networks.
ITU-T Recommendation G.813, Ti ming characteristics of SDH equipment slave clocks (SEC).
GR-253-CORE - Telcordia Technol ogies Generic Requirements - Issue 5, October 2009
GR-1244-CORE - Telcordia Technol ogies Generic Requirements - Issue 4, October 2009
ATIS-0900101.2006 - T1.101 - Synchronization Interface Standard Figure 3 shows a single blade architecture that it is usually used in simple equipment. Figure 4 shows an active/redundant architecture, as described before it is usually used in Telecom equipment that are designed to have a redundant timing card in case of primary timing card failure. The redundant timing card mimics the output of the active timing card, so in case of failure the system will still provide proper synchronization. Single Blade CDR SyncE/ SONET /SDH PHY SyncE-RxCK SyncE-TxCK Ethernet TCXO BITS/SSU SyncE (T0) AP LL LOS

Figure 3. SyncE/SONET/SDH single blade application

Figure 4. SyncE/SONET/SDH active/redundant application

3.2 HARDWARE FUNCTI ONAL DESCRIPTION

3.2.1 SYSTEM CLOCK

A crystal oscillator should be used as an input on the OSCI pin. This clock is provided for the device as a system clock. The system clock is used as a reference clock for all the internal circuits. The active edge of the system clock can be selected by the OSC_EDGE bit in xo_freq_cnfg register. Eight common oscillator frequencies can be used for the stable Sys- tem Clock. The oscillator frequency can be set by pins or by xo_fre- q_cnfg register as shown in Table 2. An offset from the nominal frequency may be compensated by set- ting the NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within ±741 ppm. The crystal oscillator should be c hosen accordingly to meet different applications and standard requirements. (See AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL).

3.2.2 MODES OF OPERATION

3.2.2.1 DPLL1 Operating Mode

The DPLL1 can operate in several different modes as shown in Table 3. The DPLL1 operating mode is controlled by the DPLL1_OPERAT- ING_MODE[4:0] bits. When the operating mode is switched automatically, the operation of the internal state machine is shown in Figure 5. Whether the operating mode is under ex ternal control or is switched automatically, the current operating mode is always indicated by the DPLL1_OPERATING_STS[4:0] bits. When the operating mode switches, the DPLL1_OPERATING_ STS bit will be set. If the DPLL1_OPERATING_STS bit is ‘1’, an interrupt will be generated if the corresponding mask bit is set to “1”, the mask bit is set to “0” by default. Table 2: Oscillator Frequencies xo_freq[2:0] pins xo_freq_cnfg[2:0] bits Oscillator Frequency (MHz) 000 10.000 001 12.800 010 13.000 011 19.440 100 20.000 101 24.576 110 25.000 111 30.720 Table 3: DPLL1 Operating Mode Control DPLL1_OPERATING_MODE[4:0] DPLL1 Operating Mode

00000 Automatic

00001 Forced - Free-Run

00010 Forced - Holdover

00011 Reserved

00100 Forced - Locked

00101 Forced - Pre-Locked2

00110 Forced - Pre-Locked

00111 Forced - Lost-Phase

01010 DCO write frequency

see Chapter 3.2.2.1.6 10010 - 11111 Reserved 10011-11111 Reserved

Figure 5. DPLL Automatic Operating Mode

An input clock is selected.
The DPLL selected input clock is disqualified AND No qualified input clock is available.
The DPLL selected input clock is switched to another one.
The DPLL selected input clock is locked (the DPLL_LOCK bit is ‘1’).
The DPLL selected input clock is disqualified AND No qualified input clock is available.
The DPLL selected input clock is unlocked (the DPLL_LOCK bit is ‘0’).
The DPLL selected input clock is locked again (the DPLL_LOCK bit is ‘1’).
The DPLL selected input clock is switched to another one.
The DPLL selected input clock is locked (the DPLL_LOCK bit is ‘1’).
The DPLL selected input clock is disqualified AND No qualified input clock is available.
The DPLL selected input clock is switched to another one.
The DPLL selected input clock is disqualified AND No qualified input clock is available.
An input clock is selected.
The DPLL selected input clock is switched to another one.

3.2.2.1.1 Free-Run Mode

In Free-Run mode, the DPLL1 output refers to the system clock and is not affected by any input clock. The accuracy of the DPLL1 output is equal to that of the system clock.

3.2.2.1.2 Pre-Locked Mode

In Pre-Locked mode, the DPLL1 output attempts to track the selected input clock. The Pre-Locked mode is a secondary, temporary mode.

3.2.2.1.3 Locked Mode

In Locked mode, the DPLL1 is lock ed to the input clock. The phase and frequency offset of the DPLL1 output track those of the DPLL1 selected input clock. For a closed loop, different bandwidths and damping factors can be used depending on DPLL locking stages: starting, acquisition and locked. In the first two seconds when the DPLL1 attempts to lock to the selected input clock, the starting bandwidth and damping factor are used. They are set by the DPLL1_START_BW[4:0] bits and the DPLL1_START_DAMPING[2:0] bits respectively. During the acquisition, the acquisition bandwidth and damping factor are used. They are set by the DPLL1_ACQ_BW[4:0] bits and the DPLL1_ACQ_DAMPING[2:0] bits respectively. When the DPLL1 is locked, the locked bandwidth and damping factor are used. They are set by the DPLL1_LOCKED_BW[4:0] bits and the DPLL1_LOCKED_DAMPING[2:0] bits respectively. The corresponding bandwidth and damping factor are used when the DPLL1 operates in different locki ng stages: starting, acquisition and locked, as controlled by the device automatically. The locked bandwidth is selectable can be set as shown in Table 4.

17©2018 Integrated Device Technology, Inc. August 21, 2018 82P33714 Datasheet Table 4: DPLL1 Locked Bandwidth DPLL1_LOCKED_BW[4:0] BW Application 00000 0.090 mHz 00001 0.27 mHz 00010 0.90 mHz stratum 3E, BW<1mHz 00011 2.9 mHz G.812 Type I, BW< 3mHz 00100 4.3 mHz 00101 8.7 mHz 00110 17 mHz 00111 35 mHz 01000 69 mHz 01001 92 mHz GR-253 stratum 3, SMC and EEC- option, 2, BW < 0.1Hz 01010 277 mHz 01011 554 mHz 01100 1.1 Hz EEC-option 1, 1< BW <10 GR-1244 stratum 3, BW<3Hz 01101 2.2 Hz EEC-option 1, 1< BW <10 GR-1244 stratum 3, BW<3Hz 01110 4.4 Hz EEC-option 1, 1< BW <10 01111 8.9 Hz EEC-option 1, 1< BW <10 10000 18 Hz 10001 35 Hz 10010 71 Hz 10011 142 Hz 10100 283 Hz 10101 567 Hz 10110-11111 Reserved

3.2.2.1.4 Pre-Locked2 Mode

The Pre-Locked2 mode is a secondary, temporary mode.

3.2.2.1.5 Lost-Phase Mode

The Lost-Phase mode is a secondary, temporary mode.

3.2.2.1.6 DCO control modes

for details, see section 3.2.7.3 Output Phase control on page 31. Figure 6. DCO frequency offset control functional block diagram

3.2.2.1.7 Holdover Mode

19©2018 Integrated Device Technology, Inc. August 21, 2018 82P33714 Datasheet The default value for holdover mode is set to current averaged value with holdover filter BW of ~1.5mHz. In this mode the initial frequency off- set is better than 1.1e-5ppm assuming that there is no in-band jitter/wan- der at the input just before enteri ng holdover state. The default mode is used for Telcordia GR-1244, Telcordia GR-253, ITU-T G.8262 and ITU-T G.813 to meet holdover requirements. In Manual Mode, the frequency offset is set by the DPLL1_hold- over_freq_cnfg[39:0] bits. The accuracy is1.686305041e-10 ppm, how- ever the resolution is affected by the frequency offset applied, so when writing the frequency offset, t he programming resolution is [(77760/ 1638400) * 2^-48] * (1 + offset-in-ppm / 1e6). The offset value, which is ac quired by the modes shown in Table 5, can be read from the holdover_freq_c nfg[39:0] bits by setting the read_avg bit to “1”. If read_avg bit is set to “0” then the value in hold- over_freq_cnfg[39:0] bits is the val ue written into it. The value is 2’s complement signed number, and the total range is +/- 92 ppm. The holdover frequency resolution is calculated as follows: Holdover Frequency resolution: HO_freq_res = (77760/1638400) * 2^-48 The Holdover value read from register bits holdover_freq_cnfg[[39:0] must be converted to decimal: HO_value_dec = holdover_freq_cnfg[39:0] value in decimal The frequency offset in ppm is calculated as follows: Holdover Frequency Offset (ppm) = (HO_freq_res * HO_value_dec)/ (1-((HO_freq_res * HO_value_dec)/1e6))

3.2.2.1.8 Hitless Reference Switching

Bit hitless_switch_en in DPLL1_m on_sw_pbo_cnfg register can be used to set hitless reference switch ing. When a Hitless Switching (HS) event is triggered, the phase offset of the selected input clock with respect to the DPLL1 output is measured. The device then automatically accounts for the measured phase offset and compensates for the appro- priate phase offset into the DPLL output so that the phase transients on the DPLL1 output are minimized. The input frequencies should be set to frequencies equal to 8 kHz or higher. If hitless_switch_en is set to “1”, a HS event is triggered if any one of the following conditions occurs:

DPLL1 selected input clock switches to a different reference
DPLL1 exits from Holdover mode or Free-Run mode For the two conditions, the phase transients on the DPLL1 output are minimized to be no more than 0.61 ns with HS. The HS can also be fro- zen at the current phase offset by setting the hitless_switch_freeze bit in DPLL1_mon_sw_pbo_cnfg register. When th e HS is frozen, the device will ignore any further HS events triggered by the above two conditions, and maintain the current phase offset. When the HS is disabled, there may be a phase shift on the DPLL1 output, as the DPLL1 output tracks back to 0 degree phase offset with respect to the DPLL1 selected input clock. This phase shift can be lim- Table 5: Frequency Offset Control in Holdover Mode man_hold over auto_avg hist_mode [1:0] avg_mode[1 :0] Frequency Offset Acquiring Method 0 don’t-care don’t-care Averaged 0 0 Current averaged value with holdover filter BW of ~0.18mHz 0 1 Current averaged value with holdover filter BW of ~1.5mHz 1 0 Current averaged value with holdover filter BW of ~12mHz 1 1 Current averaged value with holdover filter BW of ~0.15Hz 0 0 Averaged value 1 second before with holdover filter BW of ~0.18mHz 0 1 Averaged value 1 second before with holdover filter BW of ~1.5mHz 1 0 Averaged value 1 second before with holdover filter BW of ~12mHz 1 1 Averaged value 1 second before with holdover filter BW of ~0.15Hz 0 0 Averaged value 8 seconds before with holdover filter BW of ~0.18mHz 0 1 Averaged value 8 seconds before with holdover filter BW of ~1.5mHz 1 0 Averaged value 8 seconds before with holdover filter BW of ~12mHz 1 1 Averaged value 8 seconds before with holdover filter BW of ~0.15Hz 0 0 Averaged value 64 seconds before with holdover filter BW of ~0.18mHz 0 1 Averaged value 64 seconds before with holdover filter BW of ~1.5mHz 1 0 Averaged value 64 seconds before with holdover filter BW of ~12mHz 1 1 Averaged value 64 seconds before with holdover filter BW of ~0.15Hz 1 don’t-care Manual - values is set by DPLL1_holdover_freq_cnfg register

3.2.2.1.9 Phase Slope Limit

options are shown in Table 6. mable limit is 1484.3614 us/s.

3.2.2.1.10 Frequency Offset Limit

limit (refer to Chapter 3.2.4.3).

3.2.2.2 DPLL2 Operating Mode

write “0” to bit DPLL2_pdn in pdn_conf register to enable it. Figure 7. DPLL2 Automatic Operating Mode

An input clock is selected.
An input clock is selected.
No input clock is selected.

3.2.2.2.1 Free-Run Mode

equal to that of the system clock.

3.2.2.2.2 Locked Mode

DPLL2 is a wide BW DPLL, with loop bandwidth higher than 25Hz. value to meet different standards according to this table.

000 Automatic

001 Forced - Free-Run

010 Forced - Holdover

100 Forced - Locked

3.2.2.2.3 Holdover Mode

In Holdover mode, the DPLL2 has 2 modes of operation for the hold- over set by DPLL2_auto_avg bit in DPLL2_holdover_mode_cnfg regis- ter. DPLL2_auto_avg = 0: holdover frequency is the instantaneous value of integral path just before entering holdover. If the DPLL2 was locked to an input clock reference that has no in-band jitter/wander and was then manually set to go into holdover, the initial frequency accuracy is 4.4X10-8 ppm. DPLL2_auto_avg = 1: averaged frequency value is used as holdover frequency. The holdover average bandwid th is about 1.5mHz. In this mode the initial frequency offset is 1.1e-5ppm assuming that there is no in-band jitter/wander at the input just before entering holdover state.

3.2.2.2.4 Frequency Offset Limit

The DPLL2 output is limited to be within the DPLL hard limit (refer to Chapter 3.2.4.3).

3.2.3 INPUT CLOCKS AND FRAME SYNC

The 82P33714 has 6 input clocks that can also be used for frame sync pulses. The 82P33714 supports Telecom and Ethernet frequencies from 1PPS up to 650 MHz. Any of the input clocks can be used as a frame pulse or sync signal. The SYNC_sel[3:0] bits in IN n_los_sync_cnfg (1 < n < 6) registers sets which pin is used as frame pulse or sync signal. IN1 to IN6 can be used for 2 kHz, 4 kHz or 8 kHz frame pulses or 1PPS sync signal. The input frequency should match the setting in the sync_freq[1:0] bits in DPLL1_input_mode_cnfg register.

3.2.3.1 Input Clock Pre-divider

Each input clock is assigned an inte rnal Pre-divider. The Pre-divider can be used to divide the clock frequency down to a convenient fre- quency, such as 8 kHz for the internal DPLL1. Note that T1 and E1 refer- ences can exhibit substantial jitter with frequencies above 4 kHz. These references should be applied to DPLL1 without being divided down to 8kHz. For IN1 ~ IN6, the DPLL required frequency is set by the correspond- ing IN_FREQ[3:0] bits. Each Pre-divider consists of an FEC divider and a DivN divider,. IN1~IN4 also include an HF (High Frequency) divider. Figure 8 shows a block diagram of the pre-dividers for an input clock. For 1 PPS, 2 kHz, 4 kHz or 8 kHz input clock frequency only, the Pre- divider should be bypassed by setting INn_DIV[1:0] bits = “0” (1 < n < 4), DIRECT_DIV bit = “0”, and LOCK_8K bit = “0”. The corresponding IN_- FREQ[3:0] bits should be set to match the input frequency. The HF divider, which is avail able for IN1 ~ IN4, should be used when the input clock is higher than ( ) 162.5 MHz. The input clock can be divided by 4, 5 or can bypass t he HF divider, as determined by the INn_DIV[1:0] bits (1 < n < 4). The DivN divider can be bypa ssed, as determined by the DIRECT_DIV bit and the LOCK_8K bit. When DivN divider is bypassed, the corresponding IN_FREQ[3:0] bits should be set to match the input frequency. DIVN must be bypassed on a reference clock input that is also associated with another reference input used as SYNC. When the DivN divider is used for INn (1  n  6), the division factor setting should observe the following order: 1. Write the lower eight bits of the division factor to the PRE_DIVN_VALUE[7:0] bits; 2. Write the higher eight bits of the division factor to the PRE_DIVN_VALUE[14:8] bits. The division factor is calculated as follows: Division Factor = (the frequency of the clock input to the DivN divider ÷ the frequency of the DPLL required clock set by the IN_- FREQ[3:0] bits) - 1 The Pre-divider configuration and the division factor setting depend on the input clock on one of the IN1 ~ IN6 pins and the DPLL required clock. For the fractional input divider, the FEC divider, each input clock has a 16-bit (fec_divp_cnfg[15:0]) that represents the value of the numerator and a 16-bit (fec_divq_cnfg[15:0]) that represents the value of the Table 8: IN_FREQ[3:0] DPLL Frequency IN_FREQ[3:0] Bits DPLL Frequency 0000 8 kHz 0001 1.544 MHz / 2.048 MHz (depends on SONET/ SDH bit) 0010 6.48 MHz 0011–1000 Reserved 1001 2 kHz 1010 4 kHz 1011 1 PPS 1100 6.25 MHz 1101–1111 Reserved

Figure 8. Pre-divider for an input clock

3.2.3.2 Input Clock Quality Monitoring

Activity
Frequency Activity and frequency monitoring are conducted on all the input clocks. The qualified clocks are available for selection for the 2 DPLLs.

3.2.3.2.1 Activity Monitoring

Each input clock is assigned an internal leaky bucket accumulator. with respect to the system clock within a 128 ms period. There are four configurations (0 - 3) for a leaky bucket accumulator. INn_NO_ACTIVITY_ALARM bit (6  n  1). Figure 9. Input Clock Activity Monitoring

3.2.3.2.2 Frequency Monitoring

the output of DPLL1, as determined by the FREQ_MON_CLK bit. Accepting Threshold and Soft Alarm Rejecting Threshold. quency monitoring, refer to Figure 10. (6 n  1) in the same way as hard alarm.

Read the value in the IN_FREQ_VALUE[7:0] bits and calculate

Figure 10. Hysteresis Frequency Monitoring

3.2.3.3 Input Clock Selection

3.2.3.3.1 Forced Selection

3.2.3.3.2 Automatic Selection

process is shown in Figure 11. Figure 11. Qualified Input Clocks for Automatic Selection set for frequencies  8 kHz, by default it is set to ‘0’. clock to be valid; otherwise, it is invalid.

No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);
No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is ‘0’);
No phase lock alarm, i.e., the INn_PH_LOCK_ALARM bit is ‘0’;
If the ULTR_FAST_SW bit is ‘1’, the DPLL selected input clock misses less than (<) 2 consecutive clock cycles; if the ULTR_- FAST_SW bit is ‘0’, this condition is ignored;
LOS[3:0] are not set to disqualify the input clock For DPLL2, the following conditions must be satisfied for the input clock to be valid; otherwise, it is invalid.
No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);
No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is ‘0’);
LOS[3:0] are not set to disqualify the input clock The INn bit (6  n  1) indicates whether or not the clock is valid. When the input clock changes from ‘valid’ to ‘invalid’, or from ‘invalid’ to ‘valid), the INn bit will be set. If the INn bit is ‘1’, an interrupt will be gen- erated. When the DPLL selected input clock has failed, i.e., the selected input clock changes from ‘valid’ to ‘invalid’, the DPLL_MAIN_REF_- FAILED bit will be set. If the DPLL_MAIN_REF_FAILED bit is ‘1’, an interrupt will be generated. Table 9: Input Clock Selection for DPLL1 and DPLL2 DPLL1/2 _INPUT_SEL[3:0] Input Clock Selection

0000 Automatic selection

26©2018 Integrated Device Technology, Inc. August 21, 2018 82P33714 Datasheet For DPLL1, Revertive and Non-Reve rtive switchings are supported, as selected by the REVERTIVE_MODE bit. For DPLL2, only Revertive switching is supported. GR-1244 defines Revertive and Non-Revertive Reference switching. In Non-Revertive switching, a switch to an alternate reference is main- tained even after the original refer ence has recovered from the failure that caused the switch. In Revertive switching, the clock switches back to the original reference after that reference recovers from the failure, independent of the condition of the alternate reference. In Non-Revertive switching, input clock switch is minimized. In Revertive switching, the selected input clock is switched when another qualified input clock with a higher priority than the current selected input clock is available. Therefore, if REVERTIVE_MODE bit is set to “1”, then the selected input clock is switched if any of the following is satisfied:

the selected input clock is disqualified;
another qualified input clock with a higher priority than the selected input clock is available. A qualified input clock with the highest priority is selected by revertive switching. If more than one qualified input clock INn is available, then it is important to set appropriate priori ties to the input clocks, two input clocks must not have the same priority. In Non-Revertive switching, the DPLL1 selected input clock is not switched when another qualified input clock with a higher priority than the current selected input clock becom es available. In this case, the selected input clock is switched and a qualified input clock with the high- est priority is selected only when t he DPLL1 selected input clock is dis- qualified. If more than one qualified input clock INn is available, then it is important to set appropriate prioriti es to the input clocks, two input clocks must not have the same priority.

3.2.3.3.3 Selected / Qualif ied Input Clocks Indication

The selected input clock is indi cated by the CURRENTLY_SELECT- ED_INPUT[3:0] bits. When the device is configured in Automatic selection and Revertive switching is enabled, the input clock indicated by the CURRENTLY_SE- LECTED_INPUT[3:0] bits is the same as the one indicated by the HIGH- EST_PRIORITY_VALIDATED[3:0] bits. For proper operation COARSE_PH_LOS_LIMT_EN must be set to 0.

3.2.3.3.4 Input Clock Loss of Signal

There are 4 LOS input pins (LOS[3:0 ]) that can be used to disqualify the input clock. If they are set hi gh, then the associated input clock is disqualified to be used as an input clock, and therefore the DPLLs will not lock to that particular input clock. The 4 LOS pins can be associated with any input clock by setting bits LOS_EN in INn_LOS_SYNC_CNFG (1 < n < 6) register. By default, the LOS pins are not associated with any input.

3.2.4 DPLL LOCKING PROCESS

The following events are always monitored for the DPLLs locking process:

Fast Loss;
Fine Phase Loss;
Hard Limit Exceeding. For proper operation, COARSE_PH_LOS_LIMT_EN must be set to

3.2.4.1 Fast Loss

A fast loss is triggered when the selected input clock misses 3 con- secutive clock cycles. It is cleared once an active clock edge is detected. For DPLL1 the occurrence of the fast loss will result in the DPLL to unlock if the FAST_LOS_SW bit is ‘1’. For DPLL2, the occurrence of the fast loss will result in the DPLL to unlock regardless of the FAST_LOS_SW bit.

3.2.4.2 Fine Phase Loss

The DPLL compares the selected input clock with the feedback sig- nal. If the phase-compared result ex ceeds the fine phase limit pro- grammed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is triggered. It is cleared once the phase -compared result is within the fine phase limit. For the greatest jitter and wander tolerance, set the PH_LOS_FINE_LIMT[2:0] to the largest value. The occurrence of the fine phase loss will result in DPLL to unlock if the FINE_PH_LOS_LIMT_EN bit is ‘1’.

3.2.4.3 Hard Limit Exceeding

Two limits are available for this m onitoring. They are DPLL soft limit and DPLL hard limit. When the frequency of the DPLL output with respect to the system clock exc eeds the DPLL soft / hard limit, a DPLL soft / hard alarm will be raised; the alarm is cleared once the frequency is within the corresponding limit. T he occurrence of the DPLL soft alarm does not affect the DPLL locking status. The DPLL soft alarm is indi- cated by the corresponding DPLL_SOFT_FREQ_ALARM bit. The occurrence of the DPLL hard alarm will result in the DPLL to unlock if the FREQ_LIMT_PH_LOS bit is ‘1’. The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits and can be calculated as follows: DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724 The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0] bits and can be calculated as follows: DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014

3.2.4.4 Locking Status

The DPLL locking status depends on the locking monitoring results. The DPLL is in locked state if none of the following events is triggered during 2 seconds; otherwise, the DPLL is unlocked.

Fast Loss (the FAST_LOS_SW bit is ‘1’);
Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’);
DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’). If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the FINE_PH_LOS_LIMT_EN bit or the FR EQ_LIMT_PH_LOS bit is ‘0’, the DPLL locking status will not be affected even if the corresponding event is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2 seconds. The DPLL locking status is indicated by the corresponding DPLL_LOCK bits and by the DPLL_LOCK pins.

3.2.4.5 Phase Lock Alarm

DPLL1 has a phase lock alarm that will be raised when the selected input clock can not be locked in DP LL1 within a certain period. This period can be calculated as follows: Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0] The phase lock alarm is indicated by the corresponding INn_PH_LOCK_ALARM bit (6  n  1). The phase lock alarm can be cleared, as selected by the PH_ALARM_TIMEOUT bit:

It is cleared when a ‘1’ is written to the corresponding INn_PH_LOCK_ALARM bit;
It is cleared after the period ( = TIME_OUT_VALUE[5:0] X MUL- TI_FACTOR[1:0] in second ) starting from the time the alarm is raised. The selected input clock with a phas e lock alarm is disqualified for the DPLL1 to lock. Note that phase lock alarm is not available for DPLL2.

3.2.5 APLL1 AND APLL2

APLL1 and APLL2 are provided for a better jitter and wander perfor- mance of the device output clocks. The bandwidth for APLL1 and APLL2 is internally set to 22 kHz (typical). The input of both APLLs can be derived from one of the DPLL1 out- puts, as selected by the apll1_path_freq_cnfg[2:0] and apll2_path_fre- q_cnfg[2:0] bits respectively as shown in Table 10. APLL2 is free- running by default, after reset APLL2 should be set to be connected to DPLL1 per Table 10. To following steps should be followed to set APLL1/APLL2 output to Ethernet LAN PHY frequencies. To initialize the device, write into the following registers: 1. Write 0x04F4F0 to bits apll1 /apll2_divn_frac_cnfg[20:0] of APLL1/APLL2 fractional feedback di vider configuration register to set the fractional part of feedback divider for APLL1/APLL2 2. Write 0x0051 to bits apll1/apll2_divn_den_cnfg[15:0] of APLL1/ APLL2 divisor denominator configur ation register to set the denominator part of feedback divider for APLL1/APLL2 3. Write 0x0010 to bits apll1 /apll2_divisor_num_cnfg[15:0] of APLL1/APLL2 divisor numerator confi guration register to set the numerator part of feedback divider for APLL1/APLL2 4. Write 0x21 to bits apll1/apll2_divisor_int_cnfg[5:0] of APLL1/ APLL2 divisor integer configuration register to set the integer part of feedback divider for APLL1/APLL2 5. Write 0x13356218 to bits apll1/apll2_fr_ratio_cnfg[28:0] of APLL1/APLL2 feedback divider configur ation register to set the feedback divider for APLL1/APLL2 Table 10: APLL1/2 input selection apll1/apll2_path_freq_cnfg[2:0] APLL1/2 Input Selection 000 622.08 MHz from DPLL1 001 625 MHz from DPLL1 010 644.53125 MHz from DPLL1 011~1111 Reserved

Write 1’b1 to dsm_cnfg_en bit to enable the preset programma- ble feedback divider of APLL1/APLL2 configuration register
Write the corresponding value in the apll1/apll2_path_fre- q_cnfg[2:0] bits according to Table 10 After the device has been initialized according to the steps 1 to 5 above, follow the following steps when setting APLL1/APLL2 path to 625MHz: or 622.08MHz
Write 1’b0 to dsm_cnfg_en bit to disable the preset programma- ble feedback divider of APLL1/APLL2 configuration register
Write the corresponding value in the apll1/apll2_path_fre- q_cnfg[2:0] bits according to Table 10 3.2.5.1 EXTERNAL FILTER It is recommended to use external filter component for better noise suppression. The filter components are connected to VC1 for APLL1 and VC2 APLL2. Choosing the correct external components and having a printed circuit board (PCB) layout is a key task for quality operation of the APLLs external filter option. Figure 12 shows the APLL1 and APLL2 external filter components, and Table 11 shows the recommended val- ues for Rs, Cs and Cp. The device has been characterized using these parameters. The external loop filter components should be kept as close as possible to the device. Loop filter traces should be kept short. Other signal traces should be kept separated and not run underneath the device, and loop filter components.

Figure 12. APLL External Filter

3.2.6 OUTPUT CLOCKS & FRAME SYNC SIGNALS

3.2.6.1 Output Clocks

OUT2 ~ OUT4 can be derived from APLL1. OUT5 ~ OUT7 can be derived from APLL2. OUT1 to OUT8 have an output divi der associated with each output. can be programmed by writing into OUTn_DIV2_CNFG[26:0]. Figure 13. OUT1 and OUT8 output dividers

Figure 14. OUT2 to OUT7 output dividers

To set the feedback divider, program DPLL2_fb_div_cnfg[13:0] bits of DPLL2 feedback divider register
To set the fractional divider, program DPLL2_divn_- frac_cnfg[23:0] of DPLL2 fractional divider register
To set the denominator of t he fractional divider, program DPLL2_divn_den_cnfg[15:0] bits of DPLL2 fractional divider denominator register
To set the numerator of the fractional divider, program DPLL2_divn_num_cnfg[15:0] bits of DPLL2 fractional divider numerator register
To set the integer divider, program DPLL2_int_cnfg[7:0]bits of DPLL2 integer divider register OUT1 to OUT10 output clocks can be inverted by setting OUTn_IN- VERT bit (0: output not inverted, 1: output inverted) in OUTn_MUX- _CNFG register for (1 < n < 8), and in OUT9_CNFG and OUT10_CNFG registers for OUT9 and OUT10 respectively. The output clocks can be squelched by setting OUT- n_SQUELCH[1:0] bits (0x: no squelch, 10: squelch to '0', 11: squelch to '1') in OUTn_MUX_CNFG register for (1 < n < 8), and in OUT9_CNFG and OUT10_CNFG registers for OUT1 to OUT8, and OUT9 and OUT10 respectively. OUT1 to OUT8 output clocks c an be individually powered down by setting OUTn_PDN bit to '1' in OUT n_MUX_CNFG register for (1 < n < 82P33714 provides a variety of output frequencies from 1Hz to 650MHz. APLL1 is always enabled and the default frequency for OUT1, OUT2, and OUT3 is respectively 25 MH z, 125 MHz, and 156.25MHz. OUT4 is squelched by default. By default, OUT5 to OUT8 are squelched. Set the proper registers to set desired frequency values for OUT5 to OUT8. DPLL2 is disabled by default, and if it is enabled, then the default fre- quency for OUT9 and OUT10 is respectively 16.384 MHz and 2.048 MHz. APLL1, APLL2, and the DPLLs can be configured from an external EEPROM after reset. It can be used to set specific start up frequency values as needed by the application.

3.2.6.2 Frame Sync Signals

quencies are selected through the DPLL1_fr_mfr_sync_cnfg registers. the output clocks connected to the DCO being used. with the frame/sync pulse signal.

30©2018 Integrated Device Technology, Inc. August 21, 2018 82P33714 Datasheet DPLL selected input clock is within the limit. If it is within the limit, whether frame/sync input signal is enabled to synchronize the frame sync output signal is determined by the AUTO_EXT_SYNC_EN bit and the EXT_SYNC_EN bit. When the frame/sync input signal is enabled to synchronize the frame/sync output signal, it is adjus ted to align itself with the DPLL selected input clock. By default, the falling edge of the fr ame/sync input signal is aligned with the rising edge of the DPLL1 selected input clock. The rising edge of frame/sync input signal can be set to be aligned with the rising edge of the DPLL1 selected input clock by setting sync_edge bit to “1” in DPLL1_sync_edge_cnfg register. The EX_SYNC_ALARM_MON bit i ndicates whether frame/sync input signal is in external sync al arm status. The external sync alarm is indicated by the EX_SYNC_ALARM bit. If the EX_SYNC_ALARM bit is ‘1’, the occurrence of the external sync alarm will trigger an interrupt. The 8 kHz frame pulse, the 2 kH z frame pulse, and the 1PPS sync signal can be inverted by setting the 8K_1PPS_INV and 2K_1PPS_INV bits of Frame Sync and Multiframe Sync Output Configuration Register. The 8 kHz and the 2 kHz frame sync outputs can be 50:50 duty cycle or pulsed, as determined by the 8K_P UL and 2K_PUL bits respectively. When they are pulsed, the pulse width derived from DPLL1 is defined by the period of OUT1. They are pulsed on the position of the falling or ris- ing edge of the standard 50:50 duty cycle, as selected by the 2K_8K_PUL_POSITION bit of Frame Sync and Multiframe Sync Output Configuration Register.

3.2.7 INPUT AND OUTPUT PHASE CONTROL

The device has several features to allow a tight control of the phase on the input and output clocks.

3.2.7.1 DPLL1 Phase offset control

The phase offset of the DPLL1 selected input clock with respect to the DPLL1 output can be adjusted. If the device is configured as the active PLL in a redundancy system, then the PH_OFFSET_EN bit deter- mines whether the input-to-output phas e offset is enabled. If the device is configured as the inactive P LL in a redundancy system, then the input-to-output phase offset is al ways enabled. If enabled, the input-to- output phase offset can be adjusted by setting the PH_OFF- SET_CNFG[28:0] bits in DPLL1 phase o ffset configuration register. The register value is a 2's complement phase offset with a resolution of 0.0745ps and a total range of [20us, - 20us]. The input-to-output phase offset can be calculated as follows: Phase Offset (ps) = PH_OFFSET[28:0] X 0.0745

3.2.7.2 Input Phase control

All the inputs phase can be controll ed individually. They can be pro- grammed with a resolution of 0.61 ns and a range of [77.5 ns,-78.1ns] by setting INn_PHASE_OFFSET_CNFG[7:0] bits (1 < n < 6) in the input phase offset configuration register. T he register value is a 2's comple- ment phase offset, the default is ze ro. The programmed offset is auto- matically applied to the DPLL1 when a particular input is selected. If the manual DPLL1 phase offset control is used then the per-input phase off- set is not applied.

3.2.7.3 Output Phase control

The output phase can be controlled individually for outputs OUT1 to OUT8. There is the coarse phase control that allows the output phase to be adjusted as low as 1.6ns. There is a fine phase adjustment that allows the output phase to be adjusted as low as 187.27 ps. The total range is +/-180 There are two register s associated with the coarse phase adjust- ment, the OUTn_PH1_CNFG (1 < n < 8) and the OUTn_PH2_CNFG (1 < n < 8) registers. The OUTn_PH1_C NFG register is associated with output divider 1 as shown in Figure 13 and Figure 14, the phase can be adjusted by a step size that is equal to the period of the input of clock of the output Div1, the number set in the OUTn_PH1_CNFG register should not be larger than the number set in OUTn_DIV1_CNFG register. The OUTn_PH2_CNFG register is associated with output divider 2 as shown in Figure 13 and Figure 14, the phase can be adjusted by a step size that is equal to the period of the input of clock of the output Div2, the number set in the OUTn_PH2_CNFG r egister should not be larger than the number set in OUTn_DIV2_CNFG register. There is a register that is asso ciated with the fine phase adjustment, the OUTn_FINE_CNFG (1 < n < 8). For the fine phase adjustment, the output clocks must be output from the APLLs, The phase can be adjusted by a step size that is equal to the 1/2 of the period of the VCO. For Ethernet clocks the VCO frequenc y is 2.5GHz, for Ethernet LAN PHY the VCO frequency is 2.578125 GHz, and for SONET/SDH clocks the VCO frequency is 2.48832 GHz. OUT1 can be output from the DPLLs, and in that case the fine phase adjustment is not available, it is only available if the clocks are output from the APLLs. The output phase adjustments are not available for OUT9 and OUT10.

4 POWER SUPPLY FILTERING TECHNIQUES

To achieve optimum jitter perform ance, power supply filtering is required to minimize s upply noise modulation of the output clocks. The common sources of power supply noi se are switch power supplies and the high switching noise from the outputs to the internal PLL. The 82P33714 provides separate VDDA and VDDAO power pins for the internal analog PLL, it also prov ides VDDD and VDDDO pins for the core logic as well as I/O driver circuits. The suggested power decoupling scheme is shown in Figure 15.

Figure 15. 82P33714 Power Decoupling Scheme

5 MICROPROCESSOR INTERFACE

registers in the device. The microprocessor interface supports I2C.

5.1 I2C SLAVE MODE

5.1.1 I2C DEVICE ADDRESS

address is set by pins I2C_AD2, I2C_AD1, and I2C_AD0.

5.1.2 I2C BUS TIMING

Figure 16 shows the definition of I2C bus timing. Figure 16. Definition of I2C Bus Timing

35©2018 Integrated Device Technology, Inc. August 21, 2018 82P33714 Datasheet Table 12: Timing Definition for Standard Mode and Fast Mode(1) Symbol Parameter Standard Mode Fast Mode Unit Min Max Min Max SCL Serial clock frequency 0 100 0 400 kHz tHD; STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4.0 - 0.5 - s tLOW LOW period of the SCL clock 4.7 - 1.3 - s tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s tSU; STA Set-up time for a repeated START condition 4.7 - 0.6 - s tHD; DAT Data hold time: for CBUS compatible masters for I 2C-bus devices 5.0 0(2) 3.45(3) 0(2) 0.9(3) s tSU; DAT Data set-up time 250 - 100(4) -n s tr Rise time of both SDA and SCL signals - 1000 20 + 0.1Cb(5) 300 ns tf Fall time of both SDA and SCL signals - 300 20 + 0.1Cb(5) 300 ns tSU; STO Set-up time for STOP condition 4.0 - 0.6 - s tBUF Bus free time between a STOP and START condition 4.7 - 1.3 - s Cb Capacitive load for each bus line - 400 - 400 pF VnL Noise margin at the LOW level for each connected device (Including hysteresis) 0.1VDD - 0.1VDD - V VnH Noise margin at the HIGH level for each connected device (Including hysteresis) 0.2VDD - 0.2VDD - V tsp Pulse width of spikes which must be suppressed by the input filter 05 005 0 n s Note: 1. All values referred to VIHmin and VILmax levels (see Table 23) 2. A device must Internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the fall- ing edge of SCL. 3. The maximum tHD; DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU; DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. 5. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode device, faster fall-times according to Table 24 allowed. n/a = not applicable

5.1.3 SUPPORTED TRANSACTIONS

The supported types of transactions are shown below. Figure 17. I2C Slave Interface Supported Transactions reads and writes can be performed anywhere within that page.

5.2 I2C MASTER MODE

EEPROM reading process is completed.

8 kbit (1023 x 8) I2C EEPROM with device address 1010000 (for the base block)
Sequential read (block read) of t he entire memory-map for device, from byte-address 0x000 to 0x39E
7-bit device address mode
Validation of the EEPROM read data via CCITT-8 CRC check against value stored in memory-map address 0x39E
Support for 100 kHz and 400 kHz operation with speed program- mability. If bit 7 is set at memory-map address 0x001, the 82P33714 will shift from 100 kHz operation to 400 kHz operation.
2-byte word-addressing (1-byte word addressing is supported by offsetting the memory-map upwards 1 address in the EEPROM)
Read will abort with an alarm (RD_EEPROM_ERR interrupt status set) if any of the following conditions occur: Slave NACK, CRC fail- ure, Slave Response time-out Table 13: Description of I2C Slave Interface Supported Transactions Operation Description Current Read Reads a burst of data from an internal determined starting address, this starting address is equal to the last address accessed during the last read or write operation, incremented by one. If the address exceeds the address space, it will start from 0 again. Sequential Read Reads a burst of data from a specified address space. The starting address of the space is specified as offset a ddress. Sequential Write Writes a burst of data to a specified address space, the starting address of the space is specified as offset address. Current Read S Dev Addr + R A Data 0 A Data 1 A A Data n A P Sequential Read S Dev Addr + W A Data 0 A Data 1 A A Data n A PSr Dev Addr + R A Sequential Write S Dev Addr + W A Data 0 PA Data 1 A A Data n A from master to slave from slave to master S = start Sr= repeated start A = acknowledge A = not acknowledge P=s t o p Offset Addr A Offset Addr A

No support for Multi-master
No support for Slave clock stretching
No support for I2C Start Byte protocol
No support for EEPROM Chaining
No support for Writing to external I2C devices including the EEPROM used for booting

5.2.1 I2C BOOT-UP INITIALIZATION MODE

EEPROM mode is enabled via setting the MPU_MODE[1:0] pins high (through two separate pull-up resistors). Once the RSTB input has been asserted (low) and then de-asserted (high) and the device internal calibration has been completed, the 82P33714 will perform a short block read at 100 kHz to program the EEPROM read speed (100 kHz or 400 kHz). The 82P33714 will then perform a block read to program all the device configuration registers, and check the CRC of the EEPROM data. During the boot-up EEPROM-reading process, the 82P33714 will not respond to microprocessor serial control port accesses. Once the initialization process is completed, the contents of any of the device con- figuration registers can be further altered by the microprocessor, if desired. The 82P33714 can work with EEPR OMs supporting 2-byte word- addresses or 1-byte word-addresses by using 2-byte word addressing for both. This works in the us ual manner for EEPROMs supporting 2- byte word addresses, and gives an address-to-address match between EEPROM and memory-map. For EEPROMs supporting only 1-byte word addresses, the second address byte will cause an addition incre- ment of the address counter, and the memory-map will be read at the next highest EEPROM address,.i.e memory-map (CSR) address 0x00 will be read from EEPROM address 0x01, and memory map address 0x39E will be read from EEPROM address 0x39F. If a NACK is received to any of the read cycles performed by the 82P33714 during the initialization process, or if the CRC does not match the one stored in memory-map addres s 0x39E, the boot process will be restarted. This restart can happen up to three times before an abort is declared and the RD_EEPROM_ERR interr upt status bit is set. Also on RD_EEPROM_ERR the MPU_MODE1/ I2CM_SCL and MPU_MODE0/ I2CM_SDA pins are both held low until the interrupt status bit is cleared or the device is reset. The sugges ted method for dealing with RD_EE- PROM_ERR is to externally set the MPU_MODE[1:0] pins to 00 and then reset the 82P33714 so that it will boot into I2C serial port mode. After a successful EEPROM boot, the 82P33714 will stop toggling the MPU_MODE1/ I2CM_SCL and MPU_MODE0/I2CM_SDA pins, returning them to static high values, and the RD_EEPROM_DONE inter- rupt status bit will be set. The I2C serial port will now respond to micro- processor reads and writes to the appropriate I2C device address.

5.2.2 EEPROM MEMORY MAP NOTES

The EEPROM memory-map is the same as the control and status register (CSR) map with the following additions and constraints: 1. For EEPROMs supporting 2-byte word-address, the memory-map addresses are the same as the EPPROM addresses; for EEPROMs supporting 1-byte word-address, the memory-map addresses will by mapped to the next address in the EEPROM, i.e. memory-map address 0x00 will be read from EEPROM address 0x01, and memory-map address 0x39E will be read from EEPROM address 0x39F. 2. Memory-map address 0x001, bit 7 is the EEPROM read speed (0 for 100 kps, 1 for 400 kbps) 3. Memory-map address 0x39E is the CRC-8 of the memory-map from 0x000 to 0x39D (the standard CC ITT CRC-8 with the data width and result width being 8; the polynomial is (0, 1, 2, 8) or “0x07”). NB: all memory-map addresses from 0x000 to 0x39d are included in the sequential calculation of CRC, including those not used in the CSR - it is recommend that data at unused addresses be set to 0x00. 4. Memory-map addresses 0x392 to 0x39D must be set to the default values shown in the CSR documentation. 5. The device address at memo ry-map address 0x00f must match the address set by the board. 6. Each memory-map address that is a multiple of 0x7F must contain the pointer to the next page of the CSR i.e 0x07f 0x01 0x0ff 0x02 0x17f 0x03 0x1ff 0x04 0x27f 0x05 0x2ff 0x06 0x37f 0x07

5.3 SERIAL MODE

In a read operation, the active edge of SCLK is selected by CLKE. clocked out on the falling edge of SCLK. Figure 18. Serial Read Timing Diagram (CLKE Asserted Low) Figure 19. Serial Read Timing Diagram (CLKE Asserted High)

Figure 20. Serial Write Timing Diagram

5.4 UART MODE

Figure 21. UART Data Frame the baud_limit_cnfg register is pr ogrammed with the value (N - M). goes idle, so it is recommended that all 4 bytes be written in one burst.

Sample Clock Rate = 16 * 9600 = 153 600 Hz
Sample Clock Rate = 77.76 MHz * 4/2025 = 153 600 Hz
baud_freq_cnfg = 4 = x004
baud_limit_cnfg = 2025 - 4 = 2021 = x07E5 115 200 baud
Sample Clock Rate = 16 * 115 200 = 1 843 200 Hz
Sample Clock Rate = 77.76 MHz * 16/675 = 1 843 200 Hz
baud_freq_cnfg = 16 = x010
baud_limit_cnfg = 675 - 16 = 659 = x293 Reads and writes of the 82P33714 control and status registers are performed through a multi-frame/byte binary protocol, which is more effi- cient than a character-oriented (hyper -terminal) protocol. The UART will auto-increment the internal address to support burst reads and writes for even higher efficiency.

5.4.1 PROTOCOL

optionally acknowledged on completion. The format of the command byte is given in Table 16. ter at the top of the register page (address 127 / x3F). leave out the High Address byte. Set to 0 to enable address auto increment. Set to 1 to disable address auto increment. Set to 1 to send ACK byte at command completion.

The output boundary scan cells do not capture data from the core and the device does not support EXTEST instruction; The JTAG interface timing diagram is shown in Figure - 22.

Figure 22. JTAG Interface Timing Diagram

7 THERMAL MANAGEMENT

The device operates over the industry temperature range -40°C ~ +85°C. To ensure the functionality and reliability of the device, the maxi- mum junction temperature T jmax should not exceed 125°C. In some applications, the device will consume more power and a thermal solution should be provided to ensure the junction temperature T j does not exceed the Tjmax.

7.1 JUNCTION TEMPERATURE

Junction temperature Tj is the temperature of package typically at the geographical center of the chip where the device's electrical circuits are. It can be calculated as follows: Equation 1: Tj = TA + P X JA Where: JA = Junction-to-Ambient Thermal Resistance of the Package Tj = Junction Temperature TA = Ambient Temperature P = Device Power Consumption In order to calculate juncti on temperature, an appropriate JA must be used. The JA is shown in Table 18: Table 18 has the thermal results based on JEDEC standard condi- tions. It is industry practice and IDT practice to publish these results. If the PCB design differs from t he JEDEC standard conditions, then the thermal results will be different.

7.2 THERMAL RELEASE PATH

In order to maximize both the removal of heat from the package, electrical grounding from the package to the board can be done through thermal vias to effectively conduct fr om the surface of the PCB to the ground plane(s). The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electric al conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz cop- per via barrel plating. These re commendations are to be used as a guideline only. Table 18: Thermal Data Parameter Symbol CONDITIONS PKG Typ Values (oC/W) Notes Thermal Resistance JC Junction to Case QFN/NLG72 11.2 JEDEC PCB (7x7 matrix) JB Junction to Base 0.42 JA1 Junction to Air, still air 20.75 JA2 Junction to Air, 1 m/s air flow 17.05 JA3 Junction to Air, 2 m/s air flow 15.66 JA4 Junction to Air, 3 m/s air flow 14.96

8 ELECTRICAL SPECIFICATIONS

8.1 ABSOLUTE MAXIMUM RATING

8.2 RECOMMENDED OPER ATION CONDITIONS

Table 19: Absolute Maximum Rating Symbol Parameter Min Max Unit VDDA, VDDAO, VDDDO,VDDD Supply Voltage VDDA, VDDAO, VDDDO,VDDD -0.5 3.6 V VDDD_1_8 Supply Voltage VDDD_1_8 -0.5 1.98 V VINCMOS Input Voltage (CMOS and Open drain pins) -0.5 5.5 V VINDIFF Input Voltage (Differential pins) -0.5 VDDD+ 0.5 V VINAN Input Voltage (Analog pins) -0.5 2.2 V IOUTCONT Output Current (Continuous current) 50 mA IOUTSURGE Output Current (Surge current) 100 mA TA Ambient Operating Temperature Range -40 85 °C TSTOR Storage Temperature -50 150 °C Note: CDM Classification - Class III (JESD22 - C101) HBM Classification - Class 2 (JS-001-2010) Table 20: Recommended Operation Conditions Symbol Parameter Min Typ Max Unit Test Condition VDDA, VDDAO, VDDDO,VDDD Power Supply (DC voltage) 3.135 3.3 3.465 V VDDD_1_8 Power Supply (DC voltage) VDDD_1_8 1.71 1.8 1.89 V TA Ambient Temperature Range -40 85 °C IDDA Analog Supply Current 327.75 361.90 mA IDDD Digital Supply Current (VDDD) 24.66 27.98 mA IDDD_1_8 Digital Supply Current (VDDD_1_8) 81.46 94.55 mA IDDDO Digital Output Supply Current 38.92 42.47 mA All outputs enabled IDDAO Analog Output Supply Current 152.13 170.93 mA All outputs enabled, unloaded Analog Output Supply Current (loaded) 205.33 229.45 mA All outputs enabled,

4 LVPECL outputs

PTOT Total Power Dissipation 1.94 2.28 W All outputs enabled, excluding the loading

8.3 I/O SPECIFICATIONS

8.3.1 CMOS INPUT / OUTPUT PORT

Table 21: CMOS Input Port Electrical Characteristics Parameter Description Min Typ Max Unit Test Condition VIH Input Voltage High 2 V VIL Input Voltage Low 0.8 V IIN Input Current ±10 A Table 22: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics Parameter Description Min Typ Max Unit Test Condition VIH Input Voltage High 2 V VIL Input Voltage Low 0.8 V PU Pull-Up Resistor 50 K  IIN Input Current ±150 A Table 23: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics Parameter Description Min Typ Max Unit Test Condition VIH Input Voltage High 2 V VIL Input Voltage Low 0.8 V PD Pull-Down Resistor 50 K  IIN Input Current ±150 A Table 24: CMOS Output Port Electrical Characteristics Application Pin Parameter Description Min Typ Max Unit Test Condition Output Clock VOH Output Voltage High 2.4 VDD V IOH = -4 mA VOL Output Voltage Low 0.4 V IOL = 4 mA tR Rise time 2.2 ns CLOAD = 15 pF tF Fall time 2.2 ns CLOAD = 15 pF Other Output VOH Output Voltage High 2.4 V IOH = -2 mA VOL Output Voltage Low 0.4 V IOL= 2 mA tR Rise Time 7 20 ns CLOAD = 50 pF tF Fall Time 7 20 ns CLOAD = 50 pF

8.3.2 LVPECL / LVDS INPUT / OUTPUT PORT

8.3.2.1 PECL Input Port

Figure 23. Recommended PECL Input Port Line Termination

1 PPS

Assuming a differential input voltage of at least 100 mV.
Unused differential input terminated to VDD-1.4 V.

8.3.2.2 LVPECL Output Port

tionality. These outputs are designed to drive 50 transmission lines. circuit and clock component process variations. Figure 24. 3.3V LVPECL Output Termination Figure 25. 3.3V LVPECL Output Termination

8.3.3 LVDS INPUT / OUTPUT PORT

8.3.3.1 LVDS INPUT PORT

Figure 29. Recommended LVDS Input Port Line Termination

8.3.3.2 LVDS Output Port

input range should be verified for compatibility with the output. Figure 30. Recommended LVDS Output Port Line Termination Figure 31. Output Rise/Fall Time

8.3.4 OUTPUT CLOCK DUTY CYCLE

8.3.4.1 Single-Ended Input for Differential Input

attenuate the signal in half. This can be done in one of two wa ys. impedance. For most 50 applications, R3 and R4 can be 100 . Figure 32. Example of Single-Ended Signal to Drive Differential Input NOTE 1: Output Duty Cycle configured using APLL1 or APLL2.

8.4 JITTER PERFORMANCE

Table 30: Gigabit Ethernet Output Clock Jitter Generation (jitter measured on one differential output of APLL1/2 with one differential output enabled) Output Frequency RMS Jitter Typ (ps) RM S Jitter Max (ps) Test Filter Notes

25 MHz

0.70 0.96 2.5 kHz - 5 MHz ITU-T G.8262 limit 0.5 UI p-p (1 UI = 0.8 ns) 0.55 0.73 12 kHz - 5 MHz 0.27 0.34 637 kHz - 5 MHz IEEE 802.3-2008 limit 0.24 UI p-p /

0.0174 UI RMS

(1 UI = 0.8 ns) 125MHz 0.71 1.00 2.5 kHz to 10 MHz ITU-T G.8262 limit 0.5 UI p-p (1 UI = 0.8 ns) 0.56 0.75 12 kHz - 20 MHz 0.19 0.24 637 kHz - 10 MHz IEEE 802.3-2008 limit 0.24 UI p-p / (1 UI = 0.8 ns) 156.25MHz 0.55 0.74 12 kHz - 20 MHz 0.52 1.18 20 kHz - 40 MHz ITU-T G.8262 limit 0.5 UI p-p (1 UI = 100.47 ps) 0.23 0.31 1 MHz - 30 MHz 0.17 0.24 1.875 MHz - 20 MHz IEEE 802.3-2008 limit 0.28 UI p-p /

0.0203 UI RMS

(1 UI = 100.47 ps) 625MHz 0.56 0.76 12 kHz - 20 MHz 0.52 0.65 20 kHz - 80 MHz ITU-T G.8262 limit 0.5 UI p-p (1 UI = 100.47 ps) 0.16 0.29 1 MHz - 30 MHz 0.10 0.26 1.875 MHz - 20 MHz IEEE 802.3-2008 limit 0.28 UI p-p / (1 UI = 100.47 ps) NOTE 1: DPLL locked to input clock

52©2018 Integrated Device Technology, Inc. August 21, 2018 82P33714 Datasheet Table 31: Gigabit Ethernet Output Clock Jitter Generation (Jitter measured on one CMOS output of APLL1/2 with one CMOS output enabled) Output Frequency RMS Jitter Typ (ps) RM S Jitter Max (ps) Test Filter Notes 0.71 0.95 2.5 kHz - 5 MHz ITU-T G.8262 limit 0.5 UI p-p (1 UI = 0.8 ns) 0.54 0.70 12 kHz - 5 MHz 0.23 0.29 637 kHz - 5 MHz IEEE 802.3-2008 limit 0.24 UI p-p / (1 UI = 0.8 ns) 125MHz 0.78 1.07 2.5 kHz to 10 MHz ITU-T G.8262 limit 0.5 UI p-p (1 UI = 0.8 ns) 0.61 0.78 12 kHz - 20 MHz 0.20 0.25 637 kHz - 10 MHz IEEE 802.3-2008 limit 0.24 UI p-p / (1 UI = 0.8 ns) NOTE 1: DPLL locked to input clock

53©2018 Integrated Device Technology, Inc. August 21, 2018 82P33714 Datasheet Table 32: SONET/SDH Output Clock Jitter Generation (jitter measured on one differential output of APLL1/2 with one differential output enabled Output Frequency RMS Jitter Typ (ps) RM S Jitter Max (ps) Test Filter Notes

19.44 MHz

0.53 0.74 12 kHz to 1.3MHz GR-253-CORE and ITU-T G.813 Option 2 limit 0.1 UI p-p /

0.01 UI RMS

(STM-16: 1UI = 0.40 ns) 0.62 0.85 12 kHz to 5MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-1: 1 UI = 6.43 ns) 0.92 1.26 500 Hz to 1.3 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-4: 1 UI = 1.61 ns) 0.90 1.27 1 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-1: 1 UI = 6.43 ns) 0.32 0.43 65 kHz to 1.3 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-4: 1 UI = 1.61 ns) 0.41 0.53 250 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-4: 1 UI = 1.61 ns)

77.76 MHz

0.57 1.02 12 kHz to 20 MHz GR-253-CORE and ITU-T G.813 Option 2 limit 0.1 UI p-p / (STM-16: 1UI = 0.40 ns) 0.94 1.31 500 Hz to 1.3 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-1: 1 UI = 6.43 ns) 0.87 1.24 1 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-4: 1 UI = 1.61 ns) 0.27 0.36 65 kHz to 1.3 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-1: 1 UI = 6.43 ns) 0.22 0.29 250 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-4: 1 UI = 1.61 ns)

155.52 MHz

0.56 0.77 12 kHz to 20 MHz GR-253-CORE and ITU-T G.813 Option 2 limit 0.1 UI p-p / (STM-16: 1UI = 0.40 ns) 0.96 1.33 500 Hz to 1.3 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-1: 1 UI = 6.43 ns) 0.88 1.26 1 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-4: 1 UI = 1.61 ns) 0.68 0.97 5 kHz to 20 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-16: 1UI = 0.40 ns) 0.28 0.37 65 kHz to 1.3 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-1: 1 UI = 6.43 ns) 0.21 0.28 250 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-4: 1 UI = 1.61 ns) 0.20 0.27 1 MHz to 20 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-16: 1UI = 0.40 ns) Table 32: SONET/SDH Output Clock Jitter Generation (jitter measured on one differential output of APLL1/2 with one differential output enabled Output Frequency RMS Jitter Typ (ps) RM S Jitter Max (ps) Test Filter Notes

622.08 MHz

0.58 0.83 12 kHz to 20 MHz GR-253-CORE and ITU-T G.813 Option 2 limit 0.1 UI p-p / (STM-16: 1UI = 0.40 ns) 0.51 0.66 20 kHz to 80 MHz GR-253-CORE and ITU-T G.813 Option 2 limit 0.3 UI p-p (STM-64: 1 UI = 0.10 ns) ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-64: 1 UI = 0.10 ns) 0.16 0.26 4 MHz to 80 MHz GR-253-CORE and ITU-T G.813 Option 2 limit 0.1 UI p-p (STM-64: 1 UI = 0.10 ns) ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-64: 1 UI = 0.10 ns) 1.05 1.52 500 Hz to 1.3 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-1: 1 UI = 6.43 ns) 0.97 1.44 1 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-4: 1 UI = 1.61 ns) 0.73 1.06 5 kHz to 20 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-16: 1UI = 0.40 ns) 0.29 0.39 65 kHz to 1.3 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-1: 1 UI = 6.43 ns) 0.20 0.28 250 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-4: 1 UI = 1.61 ns) 0.14 0.27 1 MHz to 20 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-16: 1UI = 0.40 ns) NOTE 1: DPLL locked to input clock Table 32: SONET/SDH Output Clock Jitter Generation (jitter measured on one differential output of APLL1/2 with one differential output enabled Output Frequency RMS Jitter Typ (ps) RM S Jitter Max (ps) Test Filter Notes

56©2018 Integrated Device Technology, Inc. August 21, 2018 82P33714 Datasheet Table 33: SONET/SDH Output Clock Jitter Generation (jitter measured on one CMOS output of APLL1/2 with one CMOS output enabled) Output Frequency RMS Jitter Typ (ps) RM S Jitter Max (ps) Test Filter Notes 0.50 0.71 12 kHz to 1.3MHz GR-253-CORE and ITU-T G.813 Option 2 limit 0.1 UI p-p / (STM-16: 1UI = 0.40 ns) 0.54 0.74 12 kHz to 5MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-1: 1 UI = 6.43 ns) 0.89 1.23 500 Hz to 1.3 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-4: 1 UI = 1.61 ns) 0.84 1.17 1 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-1: 1 UI = 6.43 ns) 0.28 0.36 65 kHz to 1.3 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-4: 1 UI = 1.61 ns) 0.27 0.36 250 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-4: 1 UI = 1.61 ns) 0.57 2.63 12 kHz to 20 MHz GR-253-CORE and ITU-T G.813 Option 2 limit 0.1 UI p-p (STM-4: 1 UI = 1.61 ns) 0.93 1.30 500 Hz to 1.3 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-1: 1 UI = 6.43 ns) 0.86 1.22 1 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.5 UI p-p (STM-4: 1 UI = 1.61 ns) 0.28 0.37 65 kHz to 1.3 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-1: 1 UI = 6.43 ns) 0.22 0.29 250 kHz to 5 MHz ITU-T G.813 Option 1 limit 0.1 UI p-p (STM-4: 1 UI = 1.61 ns) NOTE 1: DPLL locked to input clock

57©2018 Integrated Device Technology, Inc. August 21, 2018 82P33714 Datasheet Table 34: DPLL1/DPLL2 Output Clock Jitter Generation (Jitter measured on one CMOS output of DPLL1/DPLL2 with all other outputs disabled) Output Frequency RMS Jitter Typ (ps) RM S Jitter Max (ps) Test Filter Notes 10 MHz 100.11 619.64 100 Hz - 100 kHz N x 1.544 MHz (Note 2) 100.63 543.45 100 Hz - 40 kHz 16.06 39.94 8 kHz - 40 kHz ANSI T1.403 limit 0.07 UI p-p (DS1: 1 UI = 647 ns) N x 2.048 MHz (Note 3) 99.42 449.83 100 Hz - 100 kHz 10.66 26.44 18 kHz - 100 kHz ITU-T G.823 limit 0.2 UI p-p (E1: 1 UI = 488 ns)

34.368 MHz

101.67 202.75 100 Hz - 800 kHz 25.62 39.06 10 kHz - 800 kHz ITU-T G.751 limit 0.05 UI p-p (E3: 1 UI = 29.10 ns)

44.736 MHz

105.16 198.15 100 Hz - 400 kHz 20.77 27.44 30 kHz - 400 kHz NOTE 1:DPLL1/2 locked to input clock NOTE 2: Measured on 12.352 MHz output clock NOTE 3: Measured on 16.384 MHz output clock Table 35: DPLL3 Output Clock Jitter Generation (Jitter measured on one CMOS output of DPLL3 with all other outputs disabled) Output Frequency RMS Jitter Typ (ps) RM S Jitter Max (ps) Test Filter Notes N x 2.048 MHz Note 2 147.325 347.530 100 Hz - 100 kHz 8.02 17.24 18 kHz - 100 kHz ITU-T G.823 limit 0.2 UI p-p (E1: 1 UI = 488 ns) N x 1.544 MHz Note 3 133.88 303.43 100 Hz - 40 kHz 0.80 1.47 8 kHz - 40 kHz ANSI T1.403 limit 0.07 UI p-p (DS1: 1 UI = 647 ns) NOTE 1:DPLL3 locked to input clock NOTE 2: Measured on 12.288 MHz output clock NOTE 3: Measured on 12.352 MHz output clock

8.5 INPUT / OUTPUT CLOCK TIMING

The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs. Figure 33. Input / output clock timing

8.6 OUTPUT / OUTPUT CLOCK TIMING

Figure 34. Output / output clock timing NOTE 2. The measurements in the above table are over operational temperature, varying power supply and repeated power on/off cycle. NOTE 3. Measurements are taken using an ideal REF input and an ideal System clock to account for only internal delays in the device.

59©2018 Integrated Device Technology, Inc. August 21, 2018 82P33714 Datasheet PACKAGE OUTLINE DRAWINGS The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/document/psc/nlnlg72-package-outline-100-x-100-mm-body-epad-75-mm-sq-050-mm-pitch-qfn-sawn

ORDERING INFORMATION

“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant. Table 38: Ordering Information Part/Order Number Package Temperature 82P33714ANLG 72-Pin QFN -40o to +85oC

60©2018 Integrated Device Technology, Inc August 21, 2018 DISCLAIMER Integrated Device Te chnology, Inc. (IDT) and its aff iliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specific ations described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operati ng parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. The informati on contained herein is provided without representation or warranty of any kind, whether express or implied, incl uding, but not limited to, the suitability of IDT's products for any particular purpose, an implied warran ty of merchantability, or non-infringement of the intellectual p roperty rights of others. This documen t is presented only as a guide and does not convey any license under intellectual propert y rights of IDT or any third parties. IDT's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other c ountries. Other trademarks used herein are the property Tech Support www.IDT.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

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REVISION HISTORY

Revision Date Description of Change August 21, 2018 Added Figure 31 June 15, 2018

Updated the Package Outline Drawings to append to the datasheet upon download from IDT.com; no mechanical changes.
Revision history note: The April 20, 2015 release of the 82P33714 Datasheet contained a change to Input Clock Loss of Signal that was not included in the document’s revision history. This was a documentation change only – there was no change to the form, fit, or function of the 82P33714. The text was changed as follows: From: There are 4 LOS input pins (LOS[3:0]) that can be used to disqualify the input clock. If they are set to zero, then the associ- ated input clock is disqualified to be used as an input clock, and therefore the DPLLs will not lock to that particular input clock. To: There are 4 LOS input pins (LOS[3:0]) that can be used to disqualify the input clock. If they are set high, then the associated input clock is disqualified to be used as an input clock, and therefore the DPLLs will not lock to that particular input clock. August 25, 2017 Added MS/SL PIN USAGE Updated Table 8 July 19, 2017 Updated the description of MS/SL in Table 1 Updated the Package Outline Drawings; however, no mechanical changes. January 23, 2017 Pages 3-4, 60 January 9, 2017 Pages, 1, 4, 22, 23, 28-29, 60 March 28, 2016 Page 31, 52 June 10, 2015 Pages 9, 12, 13, 39, 40, 41 May 13, 2015 Page 51 April 20, 2015 Pages 58, 60, 62-67 February 5, 2015 Pages 37, 58 (Table 38), 61 (Table 40), 62 (Table 41) January 28, 2015 Page 14 December 12, 2014 Page 51, Table 31

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Renesas Technology Corp 82P33714 overview.

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Summary

Synchronous Equipment Timing Source for Synchronous Ethernet August 21, 2018

Description

The 82P33714 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) provides tools to manage timing references,

Source title 82P33714 Datasheet(PDF) - Renesas Technology Corp

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