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8256AH INTEL

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and two parallel 1/O ports can be accessed directly by the microprocessor. Figure 1. MUART Block Diagram Contiguration

Table 1. Pin Description chip remains in this state until contro! information is written. was latched low during the ALE cycle. untilan INTA occurs or the interrupt address register is read. lcuk - | 17 |__| SYSTEM CLOCK: The reference clock for the baud rate generator and the timers. pin is an input which clocks serial data into the RxD pin on the rising edge of AxC. being sampled. This output remains high during start, stop, and parity bits. [RxD | 19 | 1 | RECEIVE DATA: Sorial data input. [ano __| 20 | PS _| GROUND: Power supply and logic ground reference.

Table 1. Pin Description (Continued) ignored. If the transmitter buffer is empty, this pulse will be ignored. chosen, the CTS input is edge sensitive. A negative edge on CTS. to-high transition at the center of each bit. | to | 23 | O | TRANSMIT DATA: Serial data output. as control pins which extend the functional spectrum of the chip.

intel. 8256AH 8085 and 8086/88 systems with direct interrupt vec- FUNCTIONAL DESCRIPTION toring, or the MUART can be polled to determine the ‘The 8256AH Multi-Function Universal Asynchronous cause of the interrupt. If additional interrupt contro! Receiver-Transmitter (MUART) combines five com- capability is needed, the MUART's interrupt control- monly used functions into a single 40-pin device. _ler can be cascaded into another MUART, into an The MUART performs asynchronous serial commu- _Intel 8259A Programmable Interrupt Controller, or nications, parallel 1/O, timing, event counting, and _into the interrupt controller of the iAPX 186/188 interrupt control. For detailed application informa- __High-Integration Microprocessor. tion, see Intel AP Note #153, Designing with the 8256. INITIALIZATION In general the MUART's functions are independent Serlal Communications of each other and only the registers and bits associ- The serial communications portion of the MUART __ ated with a particular function need to be initialized, contains a full-duplex asynchronous receiver-trans- __not the entire chip. The command sequence is arbi- miter (UART). A programmable baud rate generator _trary since every register is directly addressable; is included on the MUART to permit a variety of op- however, Command Byte 1 must be loaded first. To erating speeds without external components. The put the device into a fully operational condition, it is UART can be programmed by the CPU for a variety necessary to write the following commands: of character sizes, parity generation and detection, error detection, and start/stop bit handling. The re- Command byte 1 ceiver checks the start and stop bits in the center of Command byte 2 the bit, and a break halts the reception of data. The Command byte 3 transmitter can send breaks and can be controlled Mode byte by an external enable pin. Port 1 control Set Interrupts Parallel 1/O The modification register may be loaded if required for special applications; normally this operation is The MUART includes 16 bits of general purpose par- not necessary. The MUART should be reset before allel I/O. Eight bits (Port 1) can be individually initialization. (Either a hardware or a software reset changed from input to output or used for special /O _will do.) functions. The other eight bits (Port 2) can be used as nibbles (4 bits) or as bytes. These eight bits also include a handshaking capability using two pins on = INTERFACING Port 1 This section describes the hardware interface be- tween the 8256 MUART and the 80186 micro- Counter/Timers processor. Figure 3 displays the block diagram tor this interface. The MUART can be interfaced to There are five 8-bit counter/timers on the MUART. many other microprocessors using these basic prin- The timers can be programmed to use either a 1kHz ciples. or 16 kHz clock generated from the system clock. Four of the 8-bit counter/timers can be cascaded to _in alll cases the 8256 will be connected directly to two 16-bit counter/timers, and one of the 8-bit coun- the CPU's multiplexed address/data bus. If latches ter/timers can be reset to its initial value by an exter- or data bus butfers are used in a system, the nal signal. MUART should be on the microprocessor side of the address/data bus. The MUART latches the address internally on the falling edge of ALE. The address Interrupts consists of Chip Select (CS) and four address lines. For 8-bit microprocessors, ADO-AD3 are the ad- An eight-level priority interrupt controller canbe con- —_dress lines. For 16-bit microprocessors, AD1-AD4 figured for fully nested or normal interrupt priority. —_are the address lines; ADO is used as a second chip Seven of the eight interrupts service functions on _select which is active low. Since chip select is inter- the MUART (counter/timers, UART), and one exter- nally latched along with the address, it does not nal interrupt is provided which can be used fora have to remain active during the entire instruction particular function or for chaining interrupt control- cycle. As long as the chip select setup and hold lers or more MUARTs. The MUART will support _ times are met, it can be derived from multiplexed ad- 3-150

intel. 8256AH Vee 16 Mne x, RESET x = a ™O RESET. RES walt Poll T inra0 t-{-4 ner stm—|uor orm H| L = | nn Dee ul = 8282, | |-—~aponess— — > . IHOLD on nT (2) OE [ rom 80186 8286 ere TTT

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gw ALE GNTA in? WA RO’ RESET ciK ee Od a Ds.7 sont Pay, [6S CTS _Tx0 x0 Tae Pec EXTWNT| SERIAL HO 200759-9 Figure 3, 8016/8256 Interface dress/data lines or multiplexed address/status cy is shared by all the counter/timers enabled for lines. When the 8256 is in the 16-bit mode, AO timing; thus, all timers must run with the same time serves as a second chip select. As a result the base. MUART's internal registers will all have even ad- dresses since AO must be zero to select the device. Normally the MUART will be placed on the lower 8086-8086 MODE ENABLE data byte. if the MUART is placed on the upper data——_This bit selects between 8085 mode and 8086/8088 byte, the internal registers will be 512 address loca- mode. In 8085 mode (8086 = 0), AO to A3 are used pertain and the chip would occupy an 8k word 19 address the internal registers, and an RSTn in- space. struction is generated in response to the first INTA. In 8086 mode (8086 = 1), At to Ad are used to address the internal registers, and AO is used as an DESCRIPTION OF THE REGISTERS extra chip select (AO must equal zero to be enabled). a oti The response to INTA is for 8086 interrupts where The following section will provide a description of fo Th 4 the registers and define the bits within the registers the first INTA is ignored, and an interrupt vector where appropriate. Table 2 lists the registers and (40H to 47H) is placed on the bus in response to the their addresses. second INTA. BITI-INTERRUPT ON BIT CHANGE Command Register 1 This bit selects between one of two interrupt sourc- [tr [wo [st | s0 | eax | aim | 6000 | €8 on Priority Level 1, either Counter/Timer 2 or Port wo [s1] so] } +'P47 interrupt. When this bit equals 0, Counter/ (oR) (ow) Timer 2 will be mapped into Priority Level 1. If BIT! equals 0 and Level 1 interrupt is enabled, a tran- sition from 1 to 0 in Counter/Timer 2 will generate FRO—TIMER FREQUENCY SELECT an interrupt request on Level 1. When BIT! equals 1, This bit selects between two frequencies for the five Port 1 P17 external edge triggered interrupt source timers. if FRQ = 0, the timer input frequency is iS Mapped into Priority Level 1. In this case if Level 1 16 kHz (62.5 ys). If FRO = 1, the timer input fre. _'S enabled, a low-to-high transition on P17 generates quency is 1 kHz (1 ms). The selected clock frequen- 4 interrupt request on Level 1. 3-151

Table 2. MUART Registers

intel. 8256AH BRKI—BREAK-IN DETECT ENABLE provide a frequency of either 32x or 64 the baud rate. The data transmission rates range from 0. ..32 If this bit equals 0, Port 1 P16 is a general purpose |/ Kbaud. O port. When BRK! equals 1, the Break-In Detect feature is enabled on Port 1 P16. A Break-In condi- if bits 0... 3 are set to 0, separate clocks must be tion is present on the transmission line when it is input to pin RxC for the receiver and pin TxC for the forced to the start bit voltage level by the receiving transmitter. Thus, different baud rates can be used station. Port 1 P16 must be connected externally to for transmission and reception. In this case, pre- the transmission line in order to detect a Break-In. A scalers are disabled and the input serial clock fre- Break-In is polled by the MUART during the trans- quency must match the baud rate. The input serial mission of the last or only stop bit of a character. clock frequency can range from 0 MHz to 1.024 MHz. A Break-In Detect is OR-ed with Break Detect in Bit 3 of the Status Register. The distinction can be made through the interrupt controller. If the transmit 80, B1, B2, B3-BAUD RATE SELECT and receive interrupts are enabled, a Break-In will p , * generate an interrupt on Level 5, the transmit inter- Tn rete te the re bonis ante fupt, while Break will generate an interrupt on Level nerator. 4, the receive interrupt. ge if [es [ez [er| eo] fae | Sane | SO, Si—STOP BIT LENGTH = rs: [so | Sop Butea Pefetoto [rere] op fo fo fol 1] tre[ eo _| foo [oo fot | Po Poo re /s2 [32 J Poo fos fs fe Po Pa T9200 [a2 Cs Das rs Rt The relationship of the number of stop bits and the f1[ofo|o| eo] « | function of input CTS is discussed in the Pin De- tunction of input Crs sage [a1 [o fo [1 [300 |e | [ytott1{ol 20}; «| LO, L1I—CHARACTER LENGTH pa foti fa] sof 6 | [11 foto [06] [tr [to] charactertenoth | [4 1 tot1] 100} 6 | a a G | + {| o [6 |The folowing table gives an overview of the function Los fa Ts tins TC and xc: Bits 3to 0 (Hex.) Command Register 2 Input 1 x baud | Input: 1 x baud transmitter | teconer ne [ren | ep [ cr | co | es | 2 | 81 | 80 | tanomitor® | tocohor (aR) (aw) Input: 32 < or Output: receiver bit

64 X baud rate clock with a low-to-

Programming bits 0 . . . 3 with values from 3H to FH for transmitter high transition at enables the internal baud rate generator as a com- and receiver data bit sampling mon clock source for the transmitter and receiver time. Otherwise: and determines its divider ratio. high level Output: baud rate | Output: as above Programming bits 0 ... 3 with values of 1H or 2H clock of the enables input TxC as a common clock source for the transmitter transmitter and receiver. The external clock must 3-153

intel. 8256AH As an output, RxC outputs a low-to-high transition at any bits which were high. If any bit 0-6 is low, no sampling time of every data bit of a character. Thus, change occurs to that bit. When command Register data can be loaded, 6.g., into a shift register exter 3 is read, bits 0, 3, and 7 will always be zero. nally. The transition occurs only if data bits of a char- acter are present. It does not occur for start, parity, and stop bits (RxC = high). RST—RESET As an output, TxC outputs the intemal baud rate RST is set, the following events occur: lock of the transmitter, There will be a high-to-ow 1. All bits in the Status Register except bits 4 and § transition at every beginning of a bit. are cleared, and bits 4 and 5 are set. 2. The Interrupt Enable, Interrupt Request, and Inter- rupt Service Registers are cleared. Pending re- 5” C1—SYSTEM CLOCK PRESCALER (BITS 4, quests and indications for interrupts in service will be cancelled. Interrupt signal INT will go low. Bits 4 and 5 define the system clock prescaler divid- 3, The receiver and transmitter are reset. The trans- er ratio. The internal operating frequency of mitter goes idle (TxD is high), and the receiver 1.024 MHz is derived from the system clock. enters start bit search mode. 4. If Port 2 is programmed for handshake mode, IBF and OBF are reset high. Divider Ratio RST does not alter ports, data registers or command fo [o | 5 | S12Mz | registers, butt halts any operation in progress. RST [1 [of 2 [| 204emHz RST = 0 has no effect. The reset operation trig- [PT oee atic] Beigiard ronan > Mossi 9S @ subset of the hardware reset. EP—EVEN PARITY (BIT 6) TBRK—TRANSMIT BREAK EP = 0: Odd parity The transmission data output TxD will be set low as EP = 1: Even parity soon as the transmission of the previous character has been finished stays low until TBRK is cleared. The state of CTS is of no significance for this opera- PEN—PARITY ENABLE (BIT 7) tion. As long as break is active, data transfer from ; i i the Transmitter Butfer-to the Transmitter Register Bit 7 enables parity generation and checking. will be inhibited, As soon as TBRK is reset, the break nition will be deactivated and the transmitter will PEN = 0: No parity bit col PEN = 1: Even parity bit be re-enabled. The parity bit according to Command Register 2bit6 — SBRK—SINGLE CHARACTER BREAK (see above) is inserted between the last data bit of a Character and the first or only stop bit. The parity bit This causes the transmitter data to be set low for is checked during reception. A false parity bit gener- one character including start bit, data bits, parity bit, ates an error indication in the Status Register and an _and stop bits. SBRK is automatically cleared when Interrupt Request on Level 4. time for the last data bit has passed. It will start after the character in progress completes, and will delay the next data transfer from the Transmitter Butfer to Command Register 3 the Transmitter Register until TxD returns to an idle (marking) stato. If both TBRK and SBRK are set, [set] Rxe | Ae | NW] END|SBRK|TBRK]RST] break will be set as iong as TBRK is set, but SRK eA) et will be cleared after one character time of break. If SBRK is set again, it remains set for another charac- i i a it if break Command Register 3 is different from the first two __tef- The user can send a definite number o rogistors because it has a bit set/reset capability. Characters. in this manner by clearing TBAK after Writing a byte with Bit 7 high sets any bits which Setting for the last character time. were also high. Writing a byte with Bit 7 low resets 9-154

intel. 8256AH END—END OF INTERRUPT P2C2, P2C1, P2CO—PORT 2 CONTROL If fully nested interrupt mode is selected, this bit re- | Direction | sets the currently served interrupt level in the Inter- fupl Sonice Rogster This command mist cocur at ____| Veper | Lower the end of each interrupt service routine during tuly | © | 0 | 0 [Nibble | Input | input | nested interrupt mode. END is automatically cleared when tho nferupt Service Register (riemal) is | © | + [Nibble | input { ouput cleared. END is ignored if nested interrupts are not | 0 | 1 | 0 [Nibble | Output| input | enabled [o | 1 [+ [Niboie [output] output| Byte Input MENESTED NTERRUPT ENABLE Pee hte When NIE equals 1, the interrupt controller will oper- 1 7 Byte Output ate in the nested interrupt mode. When NIE equals Handshake ©. the interrupt controller will operate in the normal interrupt mode. Refer to the “Interrupt controller’ |_+ | 1 | 0 | DO NOT USE ed Mode" for a detailed description of these opera- tions. NOTE: If Port 2 is operating in handshake mode, Interrupt Level 7 is not available for Timer 5. Instead it is assigned to Port 2 IAE—INTERRUPT ACKNOWLEDGE ENABLE handshaking 3 This bit enables an automatic response to INTA. The particular response is determined by the 8086 bit in CT2, CT3—COUNTER/TIMER MODE Command Register 1. Bit 3 and 4 defines the mode of operation of event counter/timers 2 and 3 regardless of its use as a RxE—RECEIVE ENABLE single unit or as a cascaded one. This bit enables the serial receiver and its associat- | CT2 or CTS are high, then counter/timer 2 or 3 ed status bits in the status register. If this bit is reset, respectively is configured as an event counter on bit the serial receiver will be disabled and the receive 3 or 3 respectively of Port 1 (pins 37 or 36), The status bits will not be updated. event counter decrements the count by one on each 1-to-hig it f the ext y it. If CT2 Note that the detection of break characters remains Ga\\e ah ransiion of We extemal input I rz oF enabled while the receiver is disabled; ie., Status furedi aoa tinor anal ihe Port 1 pine are used tor Register Bit 3 (BD) will be set while the receiver is FOUN S7-§ disabled whenever a break character has been rec- : ognized at the receive data input RxD. ‘TSC—TIMER 5 CONTROL SET—BIT SET/RESET If T5C is set, then Timer 5 can be preset and started brie hich during a wri , by an external signal. Writing to the Timer 5 register I this bitis high during a write to Command Register gage the Timer § save register and stops the timer, 3, then any bit marked by a high will set If this bitis |e wanstorlow tansition en bit & of Pott (pin 34) tow, then any bit marked by a high will be cleared. toads the timer with the saved value and starts the timer. The next high-to-low transition on pin 34 re- triggers the timer by reloading it with the initial value MODE REGISTER and continues timing. Paci] P2C0} — egtowing a hardware reset, the save register is re- (@R) ew) set to 00H and both clock and trigger inputs are dis- abled. Transferring an instruction with TSC = 1 en- If test mode is selected, the output from the internal ables the trigger input; the save register can now be baud rate generator is placed on bit 4 of Port 1 (pin loaded with an initial value. The first trigger pulse 35). causes the initial value to be loaded from the save , register and enables the counter to count down to To achieve this, it is necessary to program bit 4 of zero. Port 1 as an output (Port 1 Control Register Bit P14 5 and t program Command Register 2 bis 82- When the timer reaches 010 issues an intorup 80 with a value 2 SH. request, disables its interrupt level and continues 3-155

the pin is an output, and if it is low the pin is an input. each pin are described below. cascaded. Level 2 will be vacated if event coun- _ programmed as IBF/OBF handshake control output. Table 3. Event Counters/Timers Mode of Operation

intel. 8256AH device reads the data, it acknowledges this opera- Inf ble Re: tion by driving ACK low. OBF is set low by writing to terrupt Enal gister i byte hanclsheke mode is enabled for input on Port (6R) (6W = enable, 2, STB is an input. IBF is driven low after STB goes 6W= disable) low. On the rising edge of STB the data from Port 2 ; is latched. Interrupts are enabled by writing to the Set Interrupts Register (5W). Interrupts are disabled by writing to TBF is reset high when Port 2 is read. the Reset Interrupts Register (6W). Each bit set by the Set Interrupts Register (5W) will enable that level interrupt, and each bit set in the Reset interrupts PORT 12, 13—COUNTER 2, 3 INPUT Register (6W) will disable that level interrupt. The it Timer 2 of Timer 3 ie programmed as an event U2et,c2N determine which intonupte are enabled by ‘ reading the Interrupt le Register (5R). counter by the Mode Register, then Port 12 or Port ‘°ading the Interrupt Enable Register (5A) 13 is the counter input for Event Counter 2 or 3, Priority Source respectively. Highest LO Timer 1 L1 Timer 2 or Port Interrupt PORT 14—BAUD RATE GENERATOR OUTPUT L2 External Interrupt (EXTINT) cLock L3_ Timer 3 or Timers 3 & 5 If test mode is enabled by the Mode Register and te Recelve trent ! 3 Command Register 2 baud rate select is greater Fansmitter Interrupt than 2, then Port 14 is an output from the internal L6 Timer 4 or Timers 2 & 4 baud rate generator. Lowest —_L7_ Timer 5 or Port 2 Handshaking P14 in Port 1 control register must be set to 1 for the baud rate generator clock to be output. The baud «Interrupt Address Register fate generator clock is 64 X the serial bit rate excet at 19.2 Kbps when it is 32 x the bit rate. Ol isintetetey Indeaton PORT 15—TIMER 5 TRIGGER 20750-4 If TSC is set in the Mode Register enabling a retrig- gerable timer, then Port 15 is the input which starts Reading the interrupt address register transfers an and reloads Timer 5. identifier for the currently requested interrupt level , on the system data bus. This identifier is the number A high-to-low transition on P15 (Pin 34) loads the —_of the interrupt level multiplied by 4. It can be used timer with the slave register and starts the timer. by the CPU as an offset address for interrupt han- dling. Reading the interrupt address register has the 6-—BREAK- same effect as a hardware interrupt acknowledge PORT 16—BREAK-IN DETECT INTA; it clears the interrupt request pin (INT) and It Break-In Detect is enabled by BRKI in Command _ indicates an interrupt acknowledgement to the inter- Register 1, then this input is used to sense a Break- _rupt controller. In. If Port’ 16 is low while the serial transmitter is sending the last stop bit, then a Break-In condition is signaled. Receiver and Transmitter Buffer [07 [06 [ bs [04 | 0s | 02 [ 01 | 00 | PORT 17—PORT INTERRUPT SOURCE A 7 (7A) (7) If BITI in Command Register 1 is set, then a low-to- . high transition on Port 17 generates an interrupt re- 80th the receiver and transmitter in the MUART are quest on Priority Level 1 double buffered. This means that the transmitter and . receiver have a shift register and a buffer register. i The buffer registers are directly addressable by Port 17 is edge triggered. reading or writing to register seven. After the receiv- er butter is full, the RBF bit in the status register is set. 3-157

intel . 8256AH eee Reading the receive buffer clears the RBF status bit. The timer/counter interrupts are automatically dis- The transmit buffer should be written to only if the abled when the interrupt request is generated. TBE bit in the status register is set. Bytes written to the transmit buffer are held there until the transmit shift register is empty, assuming CTS is low. If the Status Register transmit butfer and shift register are empty, writing to the transmit buffer immediately transfers the byte to INT | RBF | TBE | TRE | BD | PE | OE | FE | the transmit shift register. If a serial character length (OF 6A) is less than 8 bits, the unused most significant bits 10 are set to zero when reading the receive buffer, and Readin i i s re ‘ 9 the status register gates its contents onto are ignored when writing to the transmit butter. the data bus. It holds the operational status of the serial interface as well as the status of the interrupt Port 1 in INT. The status register can be read at any time. The flags are stable and well defined at all instants. Loz | 06 | os [04 | 0s | 02 [0s | 00 | (eR) (ew FE—FRAMING ERROR, TRANSMISSION MODE Writing to Port 1 sets the data in the Port 1 output Bit 0 can be used in two modes. Normally, FE indi- latch. Writing to an input pin does not affect the pin, Cates framing error which can be changed to trans- but the data is stored and will be output if the direc- ‘mission mode indication by setting the TME bit in the tion of the pin is changed later. If the pin is used asa _-—- Modification register. contro! signal, the pin will not be affected, but the i ; data is stored. Reading Port 1 transfers the data in _‘!f transmission mode is disabled (in Modification Port 1 onto the data bus. Register), then FE indicates a framing error. A fram- ing error is detected during the first stop bit. The error is reset by reading the Status Register or by a Port 2 chip reset. A framing error does not inhibit the load- ing of the Receiver Butter. if RxD remains low, the [7 [ 06 [ os [v4 [ 03 | D2] D1 | 0] receiver will assemble the next character. The false A) ew) stop bit is treated as the next start bit, and no high- to-low transition on RxD is required to synchronize Writing to Port 2 sets the data in the Port 2 output _the receiver. latch. Writing to an input pin does not affect the pin, ; ‘ficat ‘stor but it does store the data in the latch. Reading Port 2. When the TME bit in the Modification Register is set, puts the input pins onto the bus or the contents of FE is used to indicate that the transmitter was active the output latch for output pins. during the reception of a character, thus indicating that the character received was transmitted by its own transmitter. FE is reset when the transmitter is Timer 1-5 not active during the reception of character. Reading the status register will not reset the FE bit in the Lov [os | os [54] os [oa [01 [0] transmission mode. (OAy-OEy6R) (0Ayg-OE6W) . . OE—OVERRUN ERROR Reading Timer N puts the contents of the timer onto the data bus. If the counter changes while RD is low, If the user does not read the character in the Re- the value on the data bus will not change. If two _ ceiver Buffer before the next character is received timers are cascaded, reading the high-order byte will and transferred to this register, then the OE bit is cause the low-order byte to be latched. Reading the _set. The OE flag is set during the reception of the low-order byte will unlatch them both. Writing to ei- first stop bit and is cleared when the Status Register ther timer or decascading them also clears the latch _is read or when a hardware or softwara reset occurs. condition. Writing to a timer sets the starting value of The first character received in this case will be lost. that timer. If two timers are cascaded, writing to the high-order byte presets the low-order byte to all ‘ones. Loading only the high-order byte with a value 4 PE—PARITY ERROR of X leads to a count of X *256 + 255. Timers count , down continuously. If the interrupt is enabled, it oc- Trainees charactor 8 panty overs amend curs when the counter changes from 1 to 0. : 3-158

intel. 8256AH if value of the parity bit in the received character is TBE—TRANSMITTER BUFFER EMPTY different from the one expected according to com- mand word 2 bits 6 EP. The parity bit is expected TBE indicates the Transmitter Buffer is empty and is and checked only if itis enabled by command word —_ready to accept a character. TBE is set by a chip 2 bit 7 PEN. reset or the transfer of data to the Transmitter Reg- ister, and is cleared when a character is written to A parity error is. set during the first stop bit and is _the transmitter buffer. When TBE is set, an interrupt reset by reading the Status Register or by a chip _request is generated on Level 5 if enabled. reset. RBF—RECEIVER BUFFER FULL BD—BREAK/BREAK-IN ; RBF is set when the Receiver Butfer has been load- The BD bit flags whether a break character has —_ed with a new character during the sampling of the been received, or a Break-In condition exists on the _first stop bit. RBF is cleared by reading the receiver transmission line. Command Register 1 Bit 3 (BRK!) __butfer or by a chip reset. enables the Break-In Detect function. Whenever a break character has been received, 'NT—INTERRUPT PENDING Status Register Bit 3 will be set and in addition an ' interrupt request on Level 4 is generated. The re- ny Nycuice amv inlerunt fe poneing Its reset by ceiver will be idled. It will be started again with the IETF or by reading the Interrupt Address Register if Next high-to-low transition at pin RxD. only one interrupt is pending and by a chip eset. Ry The break character received will not be loaded into. EE. OF, PE, RBF, and Break Detect all generate a the receiver butter register. Level 4 interrupt when the receiver samples the first If Break-In Detection is enabled and a Break-In con- SOP. BIL mortage TRE perenne or intocupt when dition occurs, Status Register Bit 3 will be set and in TBE" ¥g sot and the Transmitter Register finished addition an interrupt request on Level § is generat- trangmitting, The Break-In Detect interrupt is issued od. at the same time as TBE or TRE. The BD status bit will be reset on reading the status register or on a hardware or software reset. For MODIFICATION REGISTER more information on Break/Break-In, refer to the “Serial Asynchronous Communication” section of [0 [ ps4] Asa | Rs2] Rss | Aso | TwE | psc] ‘AP-153 under “Receive Break Detect” and “Break- (OFe™) In Detect.” 16 ‘TRE—TRANSMIT REGISTER EMPTY DSC—DISABLE START BIT CHECK ; DSC disables the receivers start bit check. In this When TRE is set the transmit register is empty and stata the receiver will not be reset if XD is not low an interrupt request is generated on Level 5 if en- + the center of the start bit abled. When TRE equals 0 the transmit register is in " the process of sending data, TRE is set by a chip reset and when the last stop bit has left the transmit- © TME—TRANSMISSION MODE ENABLE ter. It is reset when a character is loaded into the Transmitter Register. If CTS is low, the Transmitter TME enables transmission mode and disables fram- Register will be loaded during the transmission of ing error detection. For information on transmission the start bit. if CTS is high at the end of a character, mode see the description of the framing error bit in TRE will remain high and no character will be loaded _the status register. into the Transmitter Register until CTS goes low. If the transmitter was inactive before a character is loaded into the Transmitter Buffer, the Transmitter RS0. RS1, RS2, RS3, RS4—RECEIVER SAMPLE Register will be empty temporarily while the buffer is full. However, the data in the buffer will be trans- The number in RSn alters when the receiver sam- ferred to the transmitter register immediately and —_ ples RxD. The receiver sample time can be modified TRE will be cleared while TBE is set. only if the receiver is not clocked by RxC. 3-159

intel. 8256AH ee NOTE: Reset has no effect on the contents of receiver butt- The modification register cannot be read. Reading _ ar register, transmitter buffer register, the intermedi- from address OFH, 8086: 1EH gates the contents _ate latches of parallel ports, and event counters/tim- of the status register onto the data bus. ers, respectively. A harcore reset (reset, Pin 12) resets all modifica. Point of Time Between! hi . ites Start of Bit and End of © The start bit check is enabled. Bit Measured in Steps * Status Register Bit 0 (FE) indicates framing error. Of Ye Bit Length ‘* The sampling time of the serial receiver is the bit olaialaia 1 (Start of Bit) center. ofi}r]ito 2 A software reset (Command Word 3, RST) doesnot | 2) 1) 1] 0/1 3 affect the modification register. Oj; 1} 1) o0;0 4 of 1}o}r}t 5 o}/1}o]1]} 0 6 Hardware Reset o}1{o}]o]4 7 o}1}lofo]o 8 A reset signal on pin RESET (HIGH level) forces the ololiala]a 9 device 8256 into a well-defined initial state. This ololil1to to state is characterized as follows: ololilols " 1) Command registers 1, 2 and 3, mode register, oloj4 olo 12 Port 1 control register, and modification register olololi/4 13 are reset. Thus, all bits of the parallel interface olololilo ta are set to be intputs and event counters/timers are configured as independent 8-bit timers. ° ° ° ° 4 15 eit 2) Status register bits are reset with the exception of 2° o}o]° % (Bit center) bits 4 and 5. Bits 4 and 5 are set indicating that both transmitter register and transmitter buffer Ty) apr) ra} o 18 register are empty. TP ar} ryojd 19 3) The interrupt mask, interrupt request, and inter- tT} ay r}ojo 20 Tupt service register bits are reset and disable all tyr }oyryys ral requests. As a consequence, interrupt signal INT 1} 1} o}1)o 22 IS INACTIVE (LOW). t}1}ofof1 23 4) The transmit data output is set to the marking 1] 1} o]o}o 24 state (HIGH) and the receiver section is disabled TPO; rp ay gd 25 until it is enabled by Command Register 3 Bit 6. 1}o}1}1}o0 26 5) The start bit will be checked at sampling time. TPO; ryoys 27 The receiver will return to start bit search mode if 1; oO} tr} o}o 28 input RxD is not LOW at this time. rloloja]4 29 6) Status Register Bit 0 implies framing error. 1) O;o);rjo 30 7) The receiver samples input RxD at bit center. 1] O}o;o)4 31 1{o]o}o|o 32 (End of Bit) 3-160

intel. 8256AH ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- ‘ Ambient Te Us Bi C107 cations are subject to change without notice. Voltage On Any Pin These are stress ratings only. Operation beyond the Pi Dissipati Ww tended exposure beyond the “Operating Conditions” D.C. CHARACTERISTICS T, = 0°C to 70°C, Voc = +5.0V +10% [_Symnor [Parameter [min [| Max | Unite | Test Conaitions InputlowVotage | -o5 [| oe | ov fo inottighVotage | 20 | Voo+os | v |_| OutputLowVortage [| | 04s |v | ty = 2.5ma Outputtighvotage | 24 [|v ton = —400nA_| he Input Leakage BA Vin = Veo BA Vin = 0V lo Output Leakage nA Vout = Voc 3 BA Vout = 0.45V Veo Supply Curent [to | ma | [cw [tnputCapactance || to Tarte tmnt | Cvo \\/O Capacitance pF Unmeasured Pins Returned to Vsg(1) NOTE: 1, Sampled, not 100% tested. Ta = 25°C. A.C. CHARACTERISTICS T, = 0°C to 70°C, Voc = +5.0V + 10%, GND = OV BUS PARAMETERS ALE Pulse With [oso Ts GS to ALE Setup Time poo | ts AddressioALESetwpTime | 20 | | ns ALE to RO/WR ee ee ee FO.WA.INTAPuse wish | 200 | | Data Val rom AGW) [os 3-161

intel. 8256AH A.C. CHARACTERISTICS T, = 0°C to 70°C, Voc = +5.0V +10%, GND = OV (Continued) | rm | P| | et} ee [tor | dataFioataterAB@ Ts | tow | DatavaidtoWR | tos [wo | DatavaidaterwA | sos [tx | RO/WAConroltotatchenabie || ns_ | won | Aatetodataveid PT tc | tasr__| ResetPusewisth | gos | tw | RecoveryTimebewoonABWA | soo [ns | tom | GounterinputGycieTime (Praia [a2 TT ns | torwn | CounterinputPutse wrath High Tat [ns | torm | CounterinputPuise width tow | at ns | tre1 | Gountorinput FtoinT f at TerminalCount | [2.75 | us| | tm | LOAD Pulse High Time Gounters [taf ns [tm | Load PusetowtimeGountors at T ns | te | Counter Loadbetore Next Glock PuseonPis [at | ns a Reflected in Count | Sener [TT] is not Reflected in Count le Written is Not Decremented = [Sesser [| Written is Decremented [tox | exrntttomtt 200s | tori __| intorruptRequestonPr7ttowntt || toy +500 | ns | | tr __| Pusewiethotinterrupt RequestonPi7 | tov 100 | ns _| [tex | TAT oABTtoexrntd Tons [wa | TAT oABtowTy TT cts [toy | Glock Period 198 T1000 Tne | [oust | Gaekran ase as | [tou | GockLowPuisewitn Twn [| GockFartine 3-162

intel. 8256AH A.C. CHARACTERISTICS T, = 0°C to 70°C, Voc = +5.0V + 10%, GND = OV (Continued) SERIAL INTERFACE AND CLOCK PARAMETERS (Continued) Seriat Clock Period (4) [os [ons | |_ seo | Serial Glock High (4) [sso | Ts |_tspw | Seriat Clock Low (4) | ss | ns | sto Internal Status Update Delay from Center of Stop Bit (5) tree INT Delay from Falling Edge of Transmit Clock at 2tcy +500 End of Start Bit Pulse Width for Single Character Transmission | @) [| PARALLEL 1/0 PORT PARAMETERS. |_twe | WAT toP1/P2 Data Vaiid [_[ [= | 1/2 Data Hold Time po fs | CK Pulse Width | so [Ts | Strobe Pulse Wiath re ee ee |_ te | Data Hold after STB T ps [Tne | WAT toOBFT ee ee ACR | 10 OBF | a [tae | STB) wiBFL re ee [ta | ADT woBFT re tsit STBT toiNTT 2tcy +500 tair ACK T toiNTT 2tcy +500 NOTES: 1. O, = pF all outputs. 2. Measured from logic “one” or “zero” to 1.5V at C, = 150 pF. 3. P12, P13 are external clock inputs. 4, Note that RxC may be used as an input only in 1 mode, otherwise it will be an output. 5. The center of the Stop Bit will be the receiver sample time, as programmed by the modification register. 6. Yasth bit length for 32x, 64%; 100 ns for 1x. 7. To ensure tap spec is met. 3-163

intel. 8256AH WAVEFORMS A.C, TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT Xen x 045, 28 28 = 190 9F AC. ti re driven at 2.4V fc "1" and 0.45V_ = for a Loge "0" Timing measurements are mae et 20V for 230759-6 Logie “1” and 0.8V for a Logic “O”. CL = 150 pF Cy Includes Jig Capacitance SYSTEM CLOCK Ney: SouKH’ ox 7 'e a fouKL soomse-2 WRITE CYCLE oe, s ‘ose =| wa “ “ " 290759-8 READ CYCLE oe, "on" Ae ( sooness| OE wr) Ss sty fa ca oom “te ce ‘oe ~ 230759-9 3-164

intel. 8256AH WAVEFORMS (Continued) PARALLEL PORT HANDSHAKING—INPUT MODE ss p ‘os ou er Pp "se ton . fey Na wr ‘an meme re oe - a 230750-10 PARALLEL PORT HANDSHAKING—OUTPUT MODE A, ——. wn P ‘woe noe Pa pp oar) Lan ax: (ex) Sar ‘wa wr TTA on #5 — Se oureur ee DATA VALID Pan ————. 20759-11 3-165

intel. 8256AH COUNT PULSE TIMINGS Scown "cow. reams couvren cavams (COUNTER INPUT) ‘DECREMENTED eoae ‘ZERO COUNT Se _ wr a20780-12 LOADING TIMER (OR CASCADED COUNTER/TIMER 3 AND 5) ms coat causme (COUNTER INPUT) yp ‘ZERO COUNT rs (COUNTER INPUT) an i wr 220750-13 TRIGGER PULSE FOR TIMER 5 (CASCADED EVENT COUNTER/TIMER 3 AND 5) ns haaen meu a! ‘oe 22075014 COUNTER TIMER TIMING EXTERNAL CLOCK Ne (P12, P13) cy ‘on ne] wa New. Wwe 0789-15 OUTPUT FROM PORT 1 AND PORT 2 ee > ourrur ios, paar 220789-16 3-166

intel. 8256AH INPUT FROM PORT 1 AND PORT 2 our Pio P2027 tye the cy ~ SG A os 290780-17 INTERRUPT TIMING wrennuer Prot ba ber "bex exrt Nae wr ‘eal WTA OR RO on, 0789-10 ETS FOR SINGLE CHARACTER TRANSMISSION as ers: 220750-19 RESET TIMING eset Sway 0789-20 3-167

intel. 8256AH EXTERNAL BAUD RATE CLOCK FOR SERIAL INTERFACE sp spp" tc We ane 22 Siu mare woot Neer zo0750-21 TRANSMITTER AND RECEIVER CLOCK FROM INTERNAL CLOCK SOURCE shy wm He Garon Teeve MAU RATE zoors0-22 TRANSMISSION OF CHARACTERS ON SERIAL INTERFACE —ravous ope — anon raveuaason—ot wm 7 r : stars brs ee) ; A . Prof) ee CV WIYY TTT] EY Y ] = At Nd pire me) , a ras Ni Y \\ K wr fy y Y (LEVEL 5) . Some nome Seon 10 — SOOT ST 2207850-20 NOTES: 1. Load transmitter buffer register. 2. Transmitter butfer register is empty. 3. Transmitter register is empty. 4. Character format for this example: 7 Data Bits with Parity Bit and 2 Stop Bits. 5. Loading of transmitter butter register must be complete before CTS goes low. 6. Interrupt due to transmitter butter register empty. 7. Interrupt due to transmitter one empty. No status bits are altered when is active. 3-168

intel. 8256AH DATA BIT OUTPUT ON SERIAL INTERFACE ne TS eauo mare moun ne (64 x BAUD RATE INPUT) Te (82 « BAUO RATE PUT) ‘om tora para wr 0759-24 CONTINUOUS RECEPTION OF CHARACTERS ON SERIAL INTERFACE WITHOUT ERROR CONDITION ciunacreN _GHARAGTER__GHARAGTEN__—_GHAMMGTEN_cHARACTEN m9 TIO \\ DN) ol DOO Y Hoey se [ory yp srarvs mates err 6 (ne) . Int 4 \\ (LEVEL 4) Nene} ef —— 4)” peceven EnaBLE RECEIVER DISABLE CHARACTER CHARACTER —=GHARACTER 2007850-25 NOTES: 1. Character format for this example: 6 data bits with parity bit and one stop bit. 2. Set or reset bit 6 of command register 3 (enable receiver) 3. Receiver butfer located. 4, Read receiver butter register. 3-169

intel. 8256AH ERROR CONDITIONS DURING RECEPTION OF CHARACTERS ON THE SERIAL INTERFACE CHARACTER CHARACTER CHARACTER CHARACTER CHARACTER pon mae) DXNOOU\\_ DOOOU UO, DOOD status \\—| “ - “4 evel REGIS! BIT 1 (OE) TR (CHARACTER A LOST y—/ status Lilad (OVERRUN ERROR) Browre, FRAMING ERROR 230759-26 NOTES: 1, Character format for this example: 6 data bits without parity and one stop bit. 2. Receiver buffer register loaded. 3. Overrun error. 4, Framing error. 5. Interrupt from receiver butfer register loading. 6. Interrupt from overrun error. 7. Interrupt from framing error and loading receiver butfer register. No status bits are altered when RD is active. 3-170

Overview

8256AH is listed in the Microcontroller category. Available datasheets include documents from Intel Corporation. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

MULTIFUNTION MICROPROCESSOR SUPPORT CONTROLLER

Description

MULTIFUNTION MICROPROCESSOR SUPPORT CONTROLLER

Source title 8256AH Datasheet(PDF) - Intel Corporation

8256AH

Compare 8256AH variants.

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