82563EB INTEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 52
Technical content
Datasheet sections
- 1.0 Introduction
- 1.1 Document Scope
- 1.2 Reference Documents
- 1.3 Product Codes
- 2.0 Block Diagrams
- 3.0 Signal Descriptions
- 3.1 Signal Type Definitions
- 3.2 Shared PHY Pins
- 3.3 MDIO Interface
- 3.4 Port A PHY Interface
- 3.5 Port A Kumeran Interface
- 3.6 Port A LEDs
- 3.7 Reset, Power Down, and Initialization Signals
- 3.8 JTAG and IEEE Interface
- 3.9 Reserved Signals
- 3.10 Voltage Control Pins
- 3.11 Clock Generator Interface
- 3.12 Power/Ground Pins
- 3.13 Port B PHY Interface
- 3.14 Port B Kumeran Interface
- 3.15 Port B LEDs
- 4.0 Voltage, Temperature and Timing Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 Recommended Operating Conditions
- 4.3 DC and AC Characteristics
- 4.4 Power Supply Connections
- 4.4.1 External LVR Power Delivery
- 4.4.2 Power Sequencing with External Regulators
- 4.4.3 Internally-Generated Power Delivery
- 4.4.4 Internal LVR Power Sequencing
- 4.5 Link (MDI) Interface
- 4.6 Kumeran (Serial) Interface
- 4.6.1 Transmit
- 4.6.2 Receive
- 4.6.3 Electrical Idle
- 4.7 Crystal
- 4.7.1 External Clock Oscillator
- 4.8 Reset and Initial Clock Timing
- 4.9 Power Consumption
- 5.0 Package and Pinout Information
- 5.1 Package Information
- 5.2 Thermal Specifications
- 5.3 Pinout Information
82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon Datasheet Product Features ■ IEEE 802.3ab compliant — Robust operation over the installed base of Category-5 (Cat-5) twisted pair cabling ■ PICMG 3.1 compliant — Robust operation in backplane over Ethernet applications. ■ Support for cable line lengths greater than 100 m (spec); 123 m physical — Robust end to end connections over various cable lengths ■ Full duplex at 10, 100, or 1000 Mb/s and half duplex at 10 or 100 Mb/s. ■ IEEE 802.3ab Auto-negotiation with Next Page support — Automatic link configuration including speed, duplex, and flow control ■ 10/100 downshift — Automatic link speed adjustment with poor quality cable ■ Automatic MDI crossover — Helps to correct for infrastructure issues ■ Advanced Cable Diagnostics — Improved end-user troubleshooting ■ Kumeran interface — Low pin count, high speed interface to the Intel® 631xESB/632xESB I/O Controller Hub — Allows PHY placement proximity to I/O back panel. ■ 7 LED outputs per port (4 configurable plus 3 dedicated) — Link and Activity indications (10, 100,
1000 Mb/s) on each port
■ Clock supplied to the 631xESB/632xESB — Cost optimized design ■ Full chip power down — Support for lowest power state ■ 100 pin TQFP Package — Smaller footprint and lower power dissipation compared to multi-chip MAC and PHY solutions ■ Operating temperature: 0°C to 60° C (maximum) – heat sink or forced airflow not required — Simple thermal design ■ Power Consumption: < 1.0 Watts per port (silicon power) — Minimize impact of incorporating dual Gigabit instead of Fast Ethernet ■ Leaded and lead-freea 100-pin TQFL with an Exposed-Pad*. Devices that are lead-free are marked with a circled “e3” and have a product code: HYXXXXX a.This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 pp m. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazard- ous Substances (RoHS) -banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Pack In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative. 316534-004 Revision 2.9
82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon ii
Revision History
Nov 2007 2.9 Updated Tables 19, 20, 23, and 24. Updated Figures 5 and 6. Oct 2007 2.8 Updated Table 16 “Recommended Operating Conditions”. April 2007 2.7 Updated Section 4.2, Table 16 “Core Digital Voltage Range”. Feb 2007 2.6 Updated Table 6. May 2006 2.5 Initial public release. April 2006 2.1 Removed “Preliminary” from section 4.9 “Power Consumption”. Updated 1.9V external power supply parameters in Tables 16 and 19. Nov 2005 2.0 Initial release (Intel Confidential). Aug 2005 1.75 Added lead-free information. Added measured power consumption values. Updated crystal specifications (drive level now 750 µW). Changed 1.8V power rail references to 1.9V. Dec 2004 1.0 Major revisions in all sections. Sep 2004 0.70 Added power sequencing. Jul 2004 0.51 Changed pin 51 (page13) from AVDD (1.8V) to AVDDR (3.3V). May 2004 0.5 Initial release (Intel Secret). Legal Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82563EB/82564EB Gigabit Platform LAN Connects discussed in this document may contain design defects or errors known as erra ta which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtain ed from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708- 296-9333. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries . *Other names and brands may be claimed as the property of others. Copyright © Intel Corporation, 2007
82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon iv Figures Tables 22 82563EB/82564EB BOM (Bill of
v 82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
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82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
1.0 Introduction
The Intel® 82563EB Gigabit Platform LAN Connect is a dual, compact Physical Layer Transceiver (PHY) component designed for 10/100/1000 Mb/s operation. This device uses the Kumeran interface port of the 631xESB/632xESB I/O Controller Hub enabling the routing of long distances up to 28 inches (~711 mm). The 82564EB Gigabit Platform LAN Connect is the single port implementation. The Intel® 82563EB and 82564EB allow for Gigabit Ethernet implementations in a very small package; easing routing constraints from the 631xESB/632xESB I/O Controller Hub to the PHY . The Intel® 82563EB/82564EB devices are based upon proven PHY technology integrated into Intel’s Gigabit Ethernet Controllers. The physical layer circuitry provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The 82563EB/82564EB devices are capable of transmitting and receiving data at rates of 1000 Mb/s, 100 Mb/s, or 10 Mb/s.
1.1 Document Scope
This document contains datasheet specifications for the 82563EB/82564EB Gigabit Platform LAN Connect, including signal descriptions, DC and AC parameters, packaging data, and pinout information.
1.2 Reference Documents
This document assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide application information: 82563EB/82564EB LAN on Motherboard Design Guide (AP-467), Intel Corporation. 82563EB/82564EB Gigabit Platform LAN Connect Specification Update, Intel Corporation. 631xESB/632xESB I/O Controller Hub EEPROM Information Guide Application Note (AP- 477), Intel Corporation. 82571/82572/ESB2 LAN System Manageability Application Note (AP-497), Intel Corporation. IEEE Standard 1149.1, 2001 Edition (JTAG). Institute of Electrical and Electronics Engineers (IEEE). IEEE Standard 802.3, 2002 Edition. Incorporates various IEEE Standards previously published separately. Institute of Electrical and Electronic Engineers (IEEE). Intel® 631xESB/632xESB I/O Controller Hub External Design Specification (EDS), Volumes 1-3, Intel Corporation. Bensley/Bensley-VS Platform Design Guide (PDG), Intel Corporation. PICMG3.1 Ethernet/Fiber Channel Over PICMG 3.0 Draft Specification, September 4, 2002, Version 0.90. PCI Industrial Computer Manufacturers Group (PICMG). Software driver developers should contact their local Intel Representatives for programming information.
1.3 Product Codes
Table 1. Product Ordering Codes
2.0 Block Diagrams
Figure 1. 82563EB Dual Port Block Diagram Figure 2. 82564EB Single Port Block Diagram
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82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
3.0 Signal Descriptions
3.1 Signal Type Definitions
The signals of 82563EB/82564EB are defined as follows: I: Standard input-only signal I (T): Functional input signal implemented as a bidirectional for test O: Standard output-only signal O (T):Functional output signal implemented as a bidirectional for test I/O: Bi-directional, tri-state input/output signal A: Analog signal A-in: Analog input signal A-o: Analog output signal P: Power signal G: Ground signal NC: No connect (these signals must not be connected to any traces or planes) B: Input bias Signals may be further qualified to indicate whether an internal pull-up or pull-down is normally active. Unless otherwise stated, internal pull-up and pull-down impedances are between 50 KΩ: and 130 KΩ. PU: Internal pull-up to VDD PD: Internal pull-down to VSS Note: It may be desirable to leave some input signals as no-connects in certain system applications that rely on a device’s internal pull-up or pull-down signal to be active. Care should be taken to ensure there are no long traces, such as far-away test points or errant trace routings, on any inputs which rely solely on internal pull-devices. Excess capacitance of dangling traces may generate charge and/or noise on inputs which exceeds the capability of the internal pull-device, leading to unpredictable component behavior. In addition to a primary type, each pin can be classified according to one of the following sub-types based on its electrical characteristics, such as input and output voltages and drive strengths. TTL: TTL compatible inputs TTL3: TTL compatible pins with at least 3mA drive strength TTL6: TTL compatible pins with at least 6mA drive strength TTL8: TTL compatible pins with at least 8mA drive strength TTL12:TTL compatible pins with at least 12mA drive strength
3.2 Shared PHY Pins
3.3 MDIO Interface
Table 1. Shared PHY Pins External 4.99 KΩ ± 1% resistor connection to VSS. Table 2. MDIO Interface Pins MDIO being an in-band operation. operating frequency of 2.5 MHz. Bi-directional data signal of the management data interface. disconnected (or pulled up) if not used.
3.4 Port A PHY Interface
Note: Port A on the 82563EB/82564EB corresponds to connection to Port 0 on the 631xESB/632xESB. Table 3. Port A PHY Interface Pins and is used to determine the clock speed used for PHY_CLK_OUT.
3.5 Port A Kumeran Interface
3.6 Port A LEDs
Table 4. Port A Kumeran Interface Pins
91 A-o A Port A KumeranTX Pair
Differential Kumeran Transmit interface.
94 A-in A Port A Kumeran RX Pair
Differential Kumeran Receive interface. Table 5. Port A LEDs
3.7 Reset, Power Down, and Initialization Signals
3.8 JTAG and IEEE Interface
Table 6. Reset and Power Down Signals continuously being driven from an external source. This will power down the PHY and the Kumeran of both ports. continuously being driven from an external source. Table 7. JTAG Signals
10 KΩ 5% resistor
3.9 Reserved Signals
3.10 Voltage Control Pins
Table 8. Test Signals This pin should be left disconnected in normal operation. Table 9. Voltage Control Pins produce a linearly-regulated supply. connect the CTRL_18 pin to VSS through a 10 K Ω resistor. produce a linearly-regulated supply. connect the CTRL_12 pin to VSS through a 10 K Ω resistor.
3.11 Clock Generator Interface
3.12 Power/Ground Pins
Table 10. Clock Generator Related Signals
25 MHz Clock/Crystal Input
25 MHz Crystal Output
oscillation. If using an oscillator, XTAL2 is left as a no connect. If LINK_A is 0b, the clock speed is 62.5 MHz. If LINK_A is 1b, the clock speed is 25 MHz. If LINK_B is 0b: Clock output enabled (pulled-down). If LINK_B is 1b: Clock output disabled (no connect). Table 11. Power/Ground Pins (Sheet 1 of 2)
Table 11. Power/Ground Pins (Sheet 2 of 2)
3.13 Port B PHY Interface
632xESB. There is no port B on the 82564EB. Table 12. Port B PHY Interface Pins (Sheet 1 of 2)
3.14 Port B Kumeran Interface
Table 12. Port B PHY Interface Pins (Sheet 2 of 2) Table 13. Port B Kumeran Interface Pins
87 A-o A Port B Kumeran TX Pair
84 A-in A Port B Kumeran RX Pair
3.15 Port B LEDs
Table 14. Port B LEDs stuffing option for a test header.
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4.0 Voltage, Temperature and Timing Specifications
4.1 Absolute Maximum Ratings
4.2 Recommended Operating Conditions
4.3 DC and AC Characteristics
Table 15. Absolute Maximum Ratings a Table 16. Recommended Operating Conditions a. Higher ambient temperatures may be possible with forced airflow. Table 17. DC and AC Characteristics (Sheet 1 of 2)
4.4 Power Supply Connections
4.4.1 External LVR Power Delivery
into the 82563EB/82564EB as described in Section 4.4.3. Table 17. DC and AC Characteristics (Sheet 2 of 2)
Table 18. 3.3V External Power Supply Parameters a. The peak to peak output rippled is measured at 20 MHz Bandwidth within the operational range. Table 19. 1.9V External Power Supply Parameters a. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range.
4.4.2 Power Sequencing wit h External Regulators
The following power-on/off sequence should be applied when external power supplies are in use.
4.4.2.1 External LVR Power up Sequencing and Tracking
not electrically overstressed and does not latch-up. These requirements are shown in Figure 3. required to begin ramping before the 3.3V or the 1.9V supply. Table 20. 1.2V External Power Supply Parameters within the operational range.
Figure 3. 82563EB/82564EB power up sequencing with external regulators
4.4.2.2 External LVR Power down Sequencing
stored in the decoupling capacitors is left in the system.
4.4.3 Internally-Generated Power Delivery
external transistors to generate 2 of the 3 required voltages: 1.9V (nominal) and 1.2V (nominal). These two voltages are stepped-down from a 3.3V source. Table 21. 3.3V External Power Supply Parameters
4.4.4 Internal LVR Power Sequencing
4.4.4.1 Power up Sequencing and Tracking
prevent electrical overstress or latch-up. the internal LVR circuit). The 1.9V supply will track the 3.3V ramp. defined to the ramp rate of the 3.3V input to the internal voltage regulator circuit. a. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range.
Figure 4. 82563EB/82564EB power up sequencing with internal regulators
4.4.4.2 Internal LVR Power down Sequencing
storing in decoupling capacitors is left in the system. Table 22. 82563EB/82564EB BOM (Bill of Materi al) of Components for Internal Regulator
Table 23. 1.9V Internal LVR Specification a. The use of Tantalum capacitors is not recommended. b. The peak to peak output rippled is measured at 20 MHz Bandwidth within the operational range. Table 24. 1.2V Internal LVR Specification (Sheet 1 of 2)
4.4.4.6 PNP Transistor Specification for Internal LVR
4.4.4.7 Internal LVR Board Schematic
must never drop below the minimum Vce and out of the linear region. a. The use of Tantalum capacitors is not recommended. b. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range. Table 24. 1.2V Internal LVR Specification (Sheet 2 of 2) Table 25. PNP Specification
Figure 5. 82563EB 1.9V and 1.2V internal LVR schematic demand. See Figure 4.9 for more details regarding power consumption. Figure 6. 82564EB 1.9V and 1.2V internal LVR schematic
4.5 Link (MDI) Interface
Table 26. Link (MDI) Interface Electrical Specification
4.6 Kumeran (Serial) Interface
the 631xESB/632xESB is in electrical idle.
4.6.1 Transmit
The transmit specifications are measured with the following test load. a. IEEE 802.3ab Figure 40-19 points A&B. voltage at the far end receiver. c. See IEEE 802.3, Clause 14, Figure 14.17 for the template for the receive wave form. signal detect. The 82563EB/82564EB will accept signals typically with 460 mV peak-to-peak differential amplitude. Table 27. Kumeran (Serial) Transmit Specifications
In addition, the transmitter must meet the following eye diagram. Figure 7. Kumeran (Serial) Transmit Eye Diagram
4.6.2 Receive
valid voltage and timing specifications and is delivered from a balanced 100 Ω source. Table 28. Kumeran (Serial) Receive Specifications
Note: TDR measurements are recorded times. Record time = TDR transmit time *2. The receiver expects to receive a signal meeting the following eye diagram. Figure 8. Kumeran (Serial) Receive Eye Diagram
4.6.3 Electrical Idle
4.6.3.1 Electrical Idle Detection
senses that the differential voltage has gone below and is remaining below a threshold voltage. corresponds to the minimum output voltage in Electrical Idle plus some noise margin. corresponds to the minimum valid receive level.
4.6.3.2 Electrical Idle Output
Table 29. Kumeran (Serial) Electrical Idle Detection Table 30. Kumeran (Serial) Electrical Idle Output
4.7 Crystal
4.7.1 External Clock Oscillator
Figure 9. External Clock Oscillator Connectivity to 82563EB/82564EB Table 31. Crystal Parameters
4.8 Reset and Initial Clock Timing
guarantees that the 82563EB/82564EB resets cleanly. Figure 10. 82563EB/82564EB Reset Timing Table 32. Specification for External Clock Oscillator
PHY_RESET_N is deasserted (1b), and PHY_SLEEP is deasserted (0b).
4.9 Power Consumption
Table 33. Reset Specification over PHY_RESET_N or PHY_SLEEP. PHY_RESET_N input When 0b, the entire chip is held in reset except PHY_CLK_OUT. PHY_SLEEP input When 1b the entire chip is powered down, except PHY_CLK_OUT. Port” bit of the “Power Management Control” register. Kumeran bus or by writing a 1b to the “Control Register’s” “Power Down” bit. in energy detect mode, attempting to detect energy from the link partner. “Auto-Negotiation 1000 Disable” to control the 82563EB/82564EB’s speed. Kumeran Electrical Idle Nothing is transmitted on the differential pairs.
Table 34. Power Supply Characteristics - D0a (Both Ports)
1.2 V 20 26 140 140 165 165 345 345
Table 35. Power Supply Characteristics - D3cold - Wake Up Enabled (Both Ports)
1.2 V 20 26 140 140 166 166 12 12
Table 36. Power Supply Characteristics - Uninitialized/Disabled a. Equivalent to PHY_SLEEP = 1b and/or PHY_RESET_N = 0b.
3.3 V 10 13 11 13
1.9 V 18 20 19 19
1.2 V 2 2 7 12
Table 37. Power Supply Characteristics - Complete Subsystem
10 Mb/s Operation 100 Mb/s Operation 1000 Mb/s Operation
1.9 V 33 33 78 79 413 413
1.2 V 280 280 220 220 704 704
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5.0 Package and Pinout Information
signal mapping is indicated beginning with Section 5.3.
5.1 Package Information
ground and thermal connection. Figure 11. Mechanical Information
Figure 12. Mechanical Specifications and Notes
5.2 Thermal Specifications
within the range of 0° C to 60° C. VCC. The preliminary thermal resistances are shown in Table 38. Table 38. Thermal Characteristics
5.3 Pinout Information
Table 39. 82563EB/82564EB Pinout by Pin Number Order (Sheet 1 of 3)
1 JTAG_TDI - 1 - 10 K Ω, 5%, p/u
3 JTAG_TMS - 1 - 10 K Ω, 5%, p/u
4 RESERVED_NC - -
5 RESERVED_NC - -
6 RESERVED_NC - -
8 RESERVED_NC - -
9 RESERVED_NC - -
10 RESERVED_NC - -
11 VDDO - -
12 DVDD - -
13 RESERVED_NC - -
14 RESERVED_NC - -
15 RESERVED_NC - -
16 DVDD - -
17 RESERVED_NC - -
18 MDIO_ADD[2] - 1 - 10 K Ω, 5%, p/d
19 MDIO_ADD[3] - 1 - 10 K Ω, 5%, p/d
20 XTAL2 - -
21 XTAL1 - -
22 VDDO - -
23 CTRL_12 - -
24 AVDDR - -
25 CTRL_18 - -
26 RESERVED_NC - -
27 MDIA_PLUS[0] - -
28 MDIA_MINUS[0] - -
29 AVDD - -
30 AVDD - -
31 MDIA_PLUS[1] - -
32 MDIA_MINUS[1] - -
33 MDIA_PLUS[2] - -
34 MDIA_MINUS[2] - -
35 AVDD - -
36 MDIA_PLUS[3] - -
37 MDIA_MINUS[3] - -
38 MDIB_MINUS[3] RESERVED_NC -
39 MDIB_PLUS[3] RESERVED_NC -
40 AVDD - -
41 MDIB_MINUS[2] RESERVED_NC -
42 MDIB_PLUS[2] RESERVED_NC -
43 MDIB_MINUS[1] RESERVED_NC -
44 MDIB_PLUS[1] RESERVED_NC -
45 AVDD - -
46 AVDD - -
47 MDIB_MINUS[0] RESERVED_NC -
48 MDIB_PLUS[0] RESERVED_NC -
49 RESERVED_NC - -
51 AVDDR - -
52 RESERVED_NC - -
53 RESERVED_NC - -
54 LINK_B - See Table 10
55 LEDB_RX_ACTIVITY RESERVED_NC test point
56 LEDB_TX_ACTIVITY RESERVED_NC -
57 LEDB_DUPLEX RESERVED_NC -
58 LEDB_SPEED_1000_N RESERVED_NC -
59 DVDD - -
60 VDDO - -
61 LEDB_SPEED_100_N RESERVED_NC -
62 LEDB_ACTIVITY_N RESERVED_NC -
63 LEDB_LINK_UP_N RESERVED_NC -
64 DVDD - -
65 LINK_A - See Table 10
66 LEDA_RX_ACTIVITY - test point
67 LEDA_TX_ACTIVITY - -
68 LEDA_DUPLEX - -
69 DVDD - -
70 LEDA_SPEED_1000_N - -
71 LEDA_SPEED_100_N - -
Table 39. 82563EB/82564EB Pinout by Pin Number Order (Sheet 2 of 3)
72 LEDA_ACTIVITY_N - -
73 LEDA_LINK_UP_N - -
74 DVDD - -
75 VDDO - -
76 MDIO - -
77 MDC - 1 - 10 K Ω, 5% p/d
78 MDIO_ADD[0] - 1- 10 K Ω, 5% p/d
79 MDIO_ADD[1] - 1 - 10 K Ω, 5% p/d
80 PHY_SLEEP - 1 - 10 K Ω, 5% p/d
81 PHY_RESET_N - 1 - 10 K Ω, 5% p/u
82 RESERVED_PD - 1 - 10 K Ω, 5% p/d
83 PHY_PWR_GOOD - -
84 RXB_MINUS RESERVED_NC -
85 RXB_PLUS RESERVED_NC -
86 AVDDF - -
87 TXB_MINUS RESERVED_NC -
88 TXB_PLUS RESERVED_NC -
89 VSS - -
90 TXA_PLUS, - -
91 TXA_MINUS - -
92 AVDDF - -
93 RXA_PLUS, - -
94 RXA_MINUS - -
95 TEST_JTAG - 1 - 10 K Ω, 5% p/u
96 PHY_CLK_OUT - -
97 VDDO - -
98 RESERVED_NC - -
99 JTAG_TDO - -
100 JTAG_TCK - 1 - 10 K Ω, 5%,p/d
a. The 82564EB device uses the same name as the 82563EB device unless otherwise specified. Table 39. 82563EB/82564EB Pinout by Pin Number Order (Sheet 3 of 3)
5.4 Interface Diagrams
Figure 13. 82563EB/82564EB Interfaces
5.5 Visual Pin Assignments
Figure 14. 82563EB Dual Port Gigabit Platform LAN connect Pinout (Top View)
Figure 15. 82564EB Single Port Gigabit Platform LAN Connect Pinout (Top View)
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