82562G INTEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 44
Technical content
Datasheet sections
- 1.0 Introduction
- 1.1 Overview
- 1.2 References
- 1.3 Product Codes
- 2.1 LAN Connect Interface
- 2.1.1 Reset/Synchronize Operations
- 2.1.2 Reset Considerations
- 2.1.3 LAN Connect Clock Operations
- 2.2 Hardware Configuration
- 3.0 Performance Enhancements
- 3.1 New Usage Modes: 1, 2, 3, and
- 3.1.1 Pin Usage for Modes 1, 2, 3, and
- 3.1.2 Enhanced Tx Mode
- 4.1 Signal Type Definitions
- 4.2 Twisted Pair Ethernet (TPE) Pins
- 4.3 External Bias Pins
- 4.4 Clock Pins
- 4.5 Platform LAN Connect Interface Pins
- 4.6 LED Pins
- 4.7 Miscellaneous Control Pins
- 4.8 Power and Ground Connections
- 5.0 Physical Layer Interface Functionality
- 5.3 Analog References
- 5.4 Dynamic Reduced Power & Auto Plugging Detection
- 5.4.1 Auto Plugging Detection
- 5.4.2 Dynamic Reduced Power
- 5.4.3 Configuration
- 6.0 Platform LAN Connect Registers
- 6.1 Medium Dependent Interface (MDI) Registers 0 through
- 6.1.1 Register 0: Control Register Bit Definitions
- 6.1.2 Register 1: Status Register Bit Definitions
- 6.1.3 Register 2: PHY Identifier Register Bit Definitions
- 6.1.4 Register 3: PHY Identifier Register Bit Definitions
- 6.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions
82562G 10/100 Mbps Platform LAN Connect (PLC) Networking Silicon Datasheet Product Features 1 This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)- banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative. Additional Features ■ The 82562G PLC supports drop-in replacement with the 82562ET. If it is not used as a drop- in replacement, strapping options enable new operating modes: —LED support for three logic configurations. —LAN disable function using one pin. —Increased transmit strength. ■ The receive BER performance increases the margin for cable length. ■ Return Loss performance is improved. ■ IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface ■ IEEE 802.3u Auto-Negotiation support ■ Digital Adaptive Equalization control ■ Link status interrupt capability ■ XOR tree mode support ■ 3-port LED support (speed, link and activity) ■ 10BASE-T auto-polarity correction ■ LAN Connect Interface ■ Diagnostic loopback mode ■ 1:1 transmit transformer ratio support ■ Low power (less than 300 mW in active transmit mode) ■ Reduced power in “unplugged mode” (less than 50 mW) ■ Automatic detection of “unplugged mode” ■ 3.3 V device ■ Lead-free1 48-pin Shrink Small Outline Package for both leaded and lead-free designs. (Devices that are lead-free are marked with a circled “e3” and have the product code prefix: LUxxxxxx). Revision 1.3 April 2005
Revision History
Revision Revision Date Description 1.0 October 2004 Initial release (confidential status). 1.1 November 2004 • Updated lead-free device information.
- Updated Table 1 and Table 2 to reflect correct hardware configurations and LED logic functionality.
- Corrected signal names to match design guide and reference schemat- ics. 1.2 January 2005 • Added a note for PHY signals RBIAS100 and RBIAS10 to Section 4.3.
1.3 April 2005 • Added internal/external pull-up/pull-down resistor values to the Hardware
Configuration table and signal definition tables for TESTEN, ISOL_EXEC, ISOL_TI, ISOL_TCK, and ADV10/LAN_DISABLE# Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or oth erwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82562G PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2005, Intel Corporation * Other brands and names are the property of their respective owners.
82562G — Networking Silicon
6.3.8 Register 23: 100BASE-TX Receive Premature End of Frame
Networking Silicon — 82562G Datasheet 1
1.0 Introduction
This document is applicable to the Intel® 82562G 10/100 Mbps Platform LAN Connect device, a member of the 82562G Fast Ethernet device family.
1.1 Overview
The Intel® 82562G 10/100 Mbps Platform LAN Connect is a highly-integrated device designed for 10 or 100 Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards. The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. The 82562G complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full Duplex Flow Control standard. The 82562G also includes a PHY interface compliant to the current platform LAN connect interface.
1.2 References
- IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and Electronics Engineers.
- 82562ET(EM) and 82562GT(G) LAN on Motherboard Design Guide. Intel Corporation.
- Intel® I/O Controller Hub 6 (ICH6) Family External Design Specification (EDS), V olume 1, Revision 1.5V1. Intel Corporation.
- Intel® I/O Controller Hub 6 (ICH6) Family External Design Specification (EDS), V olume 2, Revision 1.5V2. Intel Corporation.
- LAN Connect Interface Specification. Intel Corporation.
- I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation.
- I/O Control Hub 5, 6, and 7 EEPROM Map and Programming Information. Intel Corporation. Programming information can be obtained through your local Intel representatives.
1.3 Product Codes
The product ordering code for the 82562G is: EP82562G . The product ordering code for the 82562G lead-free version is: LU82562G .
82562G — Networking Silicon
2 Datasheet
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Access Control (MAC) components that meet the Platform LAN connect interface specification. Figure 1 shows a block diagram of the 82562G architecture. Figure 1. 82562G PLC Block Diagram
2.1 LAN Connect Interface
from a PLC in comparison to a standard MII PHY . Figure 2 shows how the 82562G can be used in a 10/100 Mbps ICHx design.
25 MHz
4 Datasheet
Figure 2. 82562G PLC 10/100 Mbps Ethernet Solution
2.1.1 Reset/Synchronize Operations
- Synchronize. When this pin is activated synchronously for only one LAN connect clock, it is used for synchronization between the ICHx integrated LAN and PHY on LAN connect word boundaries.
- Reset. When this pin is asserted beyond one LAN connect clock, the 82562G uses this signal as a reset signal. To ensure a reset of the 82562G , the reset should remain active for at least 500 µs.
2.1.2 Reset Considerations
2.1.3 LAN Connect Clock Operations
applications such as Wake on LAN (WoL).
2.2 Hardware Configuration
for the different modes of operation. Table 1. 82562G Hardware Configuration
- LEDs are 82562E-compatible (“A” configuration)
- LAN_DISABLE# pin is used as ADV10 (auto-negotiation advertise 10M only) Alternative Mode: drop-in replacement for existing 82562E- based designs The ISOL_TCK, ISOL_TCI, and ISOL_EXEC, and ADV10/ LAN_DISABLE# pins have internal
10 K Ω pull-down resistors and
- LEDs are in configuration B
- LAN_DISABLE# pin is single pin LAN disable (tri-state and full power down function) The ISOL_TCK pin has an internal
10 K Ω pull-down resistor and
0 1 1 1 Isolate Tri-state and power down. 1 0 0 0 XOR Tree Board testing plus tri-state.
6 Datasheet
NOTE: Combinations not shown in Table 1 are reserved and should not be used. and should not be connected. 1 1 1 1 Power-down Mode Tri-state and power down. Table 2. LED Logic Functionality
10 Mb or 100 Mb
3.0 Performance Enhancements
3.1 New Usage Modes: 1, 2, 3, and 4
82562GZ/82562GX/82562G LAN on Motherboard Design Guide for more information.
3.1.1 Pin Usage for Modes 1, 2, 3, and 4
- ISOL_TCK
- ISOL_TI
- ISOL_EX
- TESTEN
- ADV10/LAN_DISABLE# and supporting circuits
- ACTLED#, SPDLED#, and LILED# and supporting circuits
Table 3. Usage Modes 1, 2, 3, and 4 pin LAN disable. Usability and reduced BOM cost. Usability and reduced BOM cost. Usability, reduced BOM cost, and stronger Tx drive strength. Usability, reduced BOM cost, and stronger Tx drive strength.
82562G — Networking Silicon
8 Datasheet
3.1.2 Enhanced Tx Mode
The enhanced Tx mode speeds up the rise and fall times of the 100 Mb signal. This was done so the 82562G can have improved IEEE PHY conformance requirements over a more capacitive Analog Front End (AFE); usually caused by long traces or differential switches that customers use, usually on mobile platforms. However, running an 82562G device in enhanced mode increases the radiated emissions seen from the LAN solution. The increase in radiated emissions may or may not impact the DUT’s ability to pass regulatory requirements, as it will depend largely on the design of the AFE. The enhanced mode should only be used when 100Base-TX rise/fall times cannot be met in the normal 82562G mode. Consult an Intel representative if you are considering using this mode.
Networking Silicon — 82562G Datasheet 9 4.0 82562G Signal Descriptions
4.1 Signal Type Definitions
4.2 Twisted Pair Ethernet (TPE) Pins
4.3 External Bias Pins
I Input Input pin to the 82562G. O Output Output pin from the 82562G. I/O Input/Output Multiplexed input and output pin to and from the 82562G. MLT Multi-level analog I/O Multi-level analog pin used for input and output. B Bias Bias pin used for ground connection th rough a resistor or an external voltage reference. DPS Digital Power Supply Digital power or ground pin for the 82562G. APS Analog Power Supply Analog power or ground pin for the 82562G. Pin Name Pin Number Type Description TDP TDN MLT Transmit Differential Pair. The transmit differential pair sends serial bit streams to the unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in 10BASE-T (Manchester) mode and a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with the isolation transformer. RDP RDN MLT Receive Differential Pair. The receive differential pair receive the serial bit stream from an unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in 10BASE-T mode (Manchester) or a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with an isolation transformer. Pin Name Pin Number Type Description RBIAS10 4 B Reference Bias Resistor (100 Mbps). This pin should be connected to a pull-down resistor.a a. Based on some board designs, RBIAS100 and RBIAS10 values may need to be increased/decreased to compensate for high/ low MDI transmit amplitude. See the 82562G/GT and 82562ET/EM LAN on Motherboard Design Guide for more information. RBIAS100 5 B Reference Bias Resistor (10 Mbps). This pin should be connected to a pull-down resistor.a
82562G — Networking Silicon
10 Datasheet
4.4 Clock Pins
4.5 Platform LAN Connect Interface Pins
X1 46 I Crystal Input Clock. X1 and X2 can be driven by an external 25 MHz crystal of 30 PPM or better. Otherwise, X1 is driven by an external metal- oxide semiconductor (MOS) level 25 MHz oscillator when X2 is left floating. X2 47 O Crystal Output Clock. X1 and X2 can be driven by an external 25 MHz crystal of 30 PPM or better. Pin Name Pin Number Type Description JCLK 39 O LAN Connect Clock. The LAN Connect Clock is driven by the 82562G on two frequencies depending on operation speed. When the 82562G is in 100BASE-TX mode, JCLK drives a 50 MHz clock. Otherwise, JCLK drives a 5 MHz clock for 10BASE-T. The JCLK does not stop during normal operation. JRSTSYNC 42 I Reset/Synchronize. This is a multiplexed pin and is driven by the Media Access Control (MAC) layer device. Its functions are:
- Reset. When this pin is a sserted beyond one LAN Connect clock period, the 82562G uses this signal Reset. To ensure reset of the 82562G, the Reset signal should remain active for at least 500 µs.
- Synchronize. When this pin is activated synchronously, for only one LAN Connect clock period, it is used to synchronize the MAC and PHY on LAN Connect word boundaries. JTXD[2:0] 45, 44, I LAN Connect Transmit Data. The LAN Connect transmit pins are used to transfer data from the MAC device to the 82562G. These pins are used to move transmitted data and real time control and management data. They also transmit out of band control data from the MAC to the PHY. The pins should be fully synchronous to JCLK. JRXD[2:0] 37, 35, O LAN Connect Receive Data. The LAN Connect receive pins are used to transfer data from the 82562G to the MAC device. These pins are used to move received data and real time control and management data. They also move out of band control data from the PHY to the MAC. These pins are synchronous to JCLK.
Networking Silicon — 82562G Datasheet 11
4.6 LED Pins
4.7 Miscellaneous Control Pins
LILED# O Link Integrity LED. The LILED# signal has three logic modes. The LED configurations are listed in Table 2, “LED Logic Functionality”. ACTLED# O Activity LED. The LED is active low and the Activity LED signal indicates either receive or transmit activity. When no activity is present, the LED is off. The Activity LED will flicker when activity is present. T he flicker rate depends on the activity load. If Address Matching mode is enabled by the MAC, this pin will also indicate address match events on previously received frames. SPDLED# O Speed LED. The SPDLED# signal has three logic modes. The LED configurations are listed in Table 2, “LED Logic Functionality”. Pin Name Type Description ADV10/ LAN_DISABLE# I Advertise 10 Mbps Only. The Advertise 10 Mbps Only signal is asserted high, and the 82562G advertises only 10BASE- T technology during Auto-Negotiation processes in this state. Otherwise, the 82562G advertises all of its technologies. Note: ADV10 has an internal 10 K Ω pull-down resistor. LAN Disable in 82562G Mode. In the 82562G operating mode, this pin is used as a LAN disable signal. When it is driv en low, the device is fully powered down. ISOL_TCK I Test Clock. The Test Clock signal sets the device into asynchronous test mode in conjunction with the Test Input, Test Execute and Test Enable pins (refer to Table 1, “82562G Hardware Configuration”). In the manufacturing test mode, it acts as the test clock. Note: ISOL_TCK has an internal 10 K Ω pull-down resistor. ISOL_TI I Test Input. The Test Input signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Execute and Test Enable pins (refer to Table 1, “82562G Hardware Configuration”). In the manufacturing test mode, it acts as the test data input pin. Note: ISOL_TI has an internal 10 K Ω pull-down resistor. ISOL_EXEC I Test Execute. The Test Execute signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Input, and Test Enable pins (refer to Table 1, “82562G Hardware Configuration”). In the manufacturing test mode, it places the command that was entered through the TI pin in the instruction register. Note: ISOL_EXEC has an internal 10 K Ω pull-down resistor. TOUT O Test Output. The Test Output pin is used for Boundary XOR scan output. In the manufacturing test mode, it acts as the test output port. TESTEN I Test Enable. The Test Enable pin is used to enable test mode and should be externally pulled up to V CC using a 200 Ω resistor to allow XOR Tree test mode.
82562G — Networking Silicon
12 Datasheet
4.8 Power and Ground Connections
1, 25 36, 40 9, 12, 14, 17 DPS Digital 3.3 V Power. These pins should be connected to the main digital power supply. VSS VSSP VSSA VSSA2 8, 13, 18 24, 48 33, 38 DPS Digital Ground. These pins should be connected to the main digital ground. VCCR 19, 23 APS Analog Power. VSSR 20, 22 APS Analog Ground. These pins should not be isolated from the main digital.
5.0 Physical Layer Interface Functionality
The transmit subsection of the 82562G accepts 3 bit wide data from the LAN Connect unit. Another subsection passes data unconditionally to the 4B/5B encoder. Unshielded Twisted Pair (UTP) or Shielded Twisted Pair (STP) wire. code. The table below illustrates the 4B/5B encoding scheme associated with the given symbol. Table 4. 4B/5B Encoder
82562G — Networking Silicon
14 Datasheet
5.1.1.2 100BASE-TX Scrambler and MLT-3 Encoder Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled data to the MLT-3 encoder. The 82562G implements the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation. The cipher equation used is: X[n] = X[n-11] + X[n-9] (mod 2) The MLT-3 encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT-3 is similar to NRZ1 coding, but three levels are output instead of two. The three output levels are positive, negative and zero. When an NRZ “0” arrives at the input of the encoder, the last output level is maintained (either positive, negative or zero). When an NRZ “1” arrives at the input of the encoder, the output steps to the next level. The order of steps is negative-zero-positive-zero which continues periodically. Refer to IEEE 802.3 Specification for details. 5.1.1.3 100BASE-TX Transmit Framing The 82562G does not differentiate between the fields of the MAC frame containing preamble, start of frame delimiter, data and Cyclic Redundancy Check (CRC). The 82562 encodes the first byte of the preamble as the “JK” symbol, encodes all other pieces of data according to the 4B/5B lookup table, and adds the “TR” code after the end of the packet. The 82562 scrambles and serializes the data into a 125 Mbps stream, encodes it as MLT-3, and drives it onto the wire. J 11000 1st Start of Packet Symbol 0101 K 10001 2nd Start of Packet Symbol 0101 T 01101 1st End of Packet Symbol R 00111 2nd End of Packet Symbol and Flow Control V 00000 INVALID V 00001 INVALID V 00010 INVALID V 00011 INVALID H 00100 INVALID V 00101 INVALID V 00110 INVALID V 01000 INVALID V 01100 INVALID V 10000 Flow Control S V 11001 INVALID Symbol 5B Symbol Code 4B Nibble Code
5.1.1.4 Transmit Driver
waveform for 100 Mbps is illustrated in the following figure. Figure 3. Conceptual Transmit Differential Waveform
5.1.2.1 Adaptive Equalizer
superior data dependent jitter performance.
5.1.2.2 Receive Clock and Data Recovery
5.1.2.3 MLT-3 Decoder, Descrambler, and Receive Digital Section
82562G — Networking Silicon
16 Datasheet
In 100BASE-TX mode, the 82562G can detect errors in receive data in a number of ways. Any of the following conditions is considered an error:
- Link integrity fails in the middle of frame reception.
- The start of stream delimiter “JK” symbol is not fully detected after idle.
- An invalid symbol is detected at the 4B/5B decoder.
- Idle is detected in the middle of a frame (before “TR” is detected). 5.2 10BASE-T Mode 5.2.1 10BASE-T Transmit Blocks 5.2.1.1 10BASE-T Manchester Encoder After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs the Manchester encoding. The Manchester code always has a mid-bit transition. The boundary transition occurs only when the data is the same from bit to bit. For example, if the value is 11b, then the change is from low to high within the boundary. 5.2.1.2 10BASE-T Driver and Filter Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented inside the chip. The 82562G supports both technologies through one pair of transmit differential pins and by externally sharing the same magnetics. In 10 Mbps mode the line drivers use a pre-distortion algorithm to improve jitter tolerance. The line drivers reduce their drive level during the second half of “wide” (100 ns) Manchester pulses and maintain a full drive level during all narrow (50 ns) pulses and the first half of the wide pulses. This reduces line overcharging during wide pulses, a major source of jitter. 5.2.2 10BASE-T Receive Blocks 5.2.2.1 10BASE-T Manchester Decoder The 82562G performs Manchester decoding and timing recovery in 10BASE-T mode. The Manchester encoded data stream is decoded from the receive differential pair. This data is transferred to the controller at 2.5 MHz/nibble. The high-performance circuitry of the 82562G exceeds the IEEE 802.3 jitter requirements. 5.2.2.2 10BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter In 10 Mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. The filter is implemented inside the 82562G for supporting single magnetics that are shared with the 100BASE-TX side. The input differential voltage range for the Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V . The TPE receive buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the requirements of the 10BASE-T standard. The following line activity is determined to be inactive and is rejected as invalid data:
- Differential pulses of peak magnitude less than 300 mV .
- Continuous sinusoids with a differential amplitude less than 6.2 VPP and frequency less than 2 MHz.
- Sine waves of a single cycle duration starting with 0° or 180° phase that have a differential amplitude less than 6.2 VPP and a frequency of at least 2 MHz and not more than 16 MHz. These single-cycle sine waves are discarded only if they are preceded by 4 bit times (400 ns) of silence. All other activity is determined to be either data, link test pulses, Auto-Negotiation fast link pulses, or the idle condition.
5.3 Analog References
values listed in Figure 4 are starting values. Also, resistors of 1% tolerance should be used.
5.4 Dynamic Reduced Power & Auto Plugging Detection
interface (5 MHz for LAN Connect). Thus, the reduced power mode is fully transparent to driver. Figure 4. Analog References
18 Datasheet
5.4.1 Auto Plugging Detection
setting the SQL LAN Connect control bit. Link activity detection is based on energy detection.
5.4.2 Dynamic Reduced Power
82562G operates in reduced power mode only if the LAN Connect power-down bit is set).
5.4.3 Configuration
82562G is in reduced power mode, these two bits are set to 1b. Table 5. Register 16 (10 Hexadecimal): PLC Status, Control and Address Data
13 Dynamic Reduced Power Down 0 = Automatic reduced power down
Table 6. Register 0: Control Data
11 Reduced Power Down 0 = Reduced power down disabled (normal
Networking Silicon — 82562G Datasheet 19
6.0 Platform LAN Connect Registers
The following subsections describe PHY registers that are accessible through the LAN Connect management frame protocol. Acronyms mentioned in the registers are defined as follows: SC: Self cleared. RO: Read only. RW: Read/Write. E: EEPROM setting affects content. LL: Latch low. LH: Latch high.
6.1 Medium Dependent Interface (MDI) Registers 0 through 7
6.1.1 Register 0: Control Register Bit Definitions
Bit(s) Name Description Default R/W
15 Reset This bit sets the status and control register of the PHY to
their default states and is self-clearing. The PHY returns a value of one until the reset process has completed and accepts a read or write transaction. 0 = Normal operation 1 = PHY Reset 0R W SC
14 Loopback This bit enables loopback of transmit data nibbles to the
receive data path. The PHY receive circuitry is isolated from the network. Note that this may cause the descrambler to lose synchronization and produce 560 ns of “dead time.” Note also that the loopback configuration bit takes priority over the Loopback MDI bit. 0 = Loopback disabled (normal operation) 1 = 1 = Loopback enabled 0R W
13 Speed Selection This bit is valid on read and controls speed when Auto-
Negotiation is disabled. 0 = 10 Mbps 1 = 100 Mbps 1R W
12 Auto-Negotiation
This bit enables Auto-Negotiation. Bits 13 and 8, Speed Selection and Duplex Mode, respectively, are ignored when Auto-Negotiation is enabled. 0 = Auto-Negotiation disabled 1 = Auto-Negotiation enabled 1R W
11 Reduced Power
This bit sets the PHY into a low power mode. 0 = Power down disabled (normal operation) 1 = Power down enabled 0R W
82562G — Networking Silicon
20 Datasheet
6.1.2 Register 1: Status Register Bit Definitions
10 Isolate This bit allows the PHY to isolate the medium
independent interface. The PHY is disconnected from the LAN Connect block on both the transmit and receive side. 0 = Normal operation 1 = Isolates internal medium independent interface 0R W
9 Restart Auto-
This bit restarts the Auto-Negotiation process and is self- clearing. 0 = Normal operation 1 = Restart Auto-Negotiation process 0R W SC
8 Duplex Mode This bit controls the duplex mode when Auto-Negotiation
is disabled. When Auto-Negotiation is enabled this bit is read only and always equals 1b. When the PHY is placed in Loopback mode, the behavior of the PHY shall not be affected by the status of this bit. 0 = Half Duplex 1 = Full Duplex 0R W / RO
7 Collision Test This bit is not used in the 82562G and has a default value
of 1b. (If it is used in other devices, it forces a collision in response to the assertion of the transmit enable signal.) 1R W 6:0 Reserved These bits are reserved and should be set to 0b. 0 RW Bit(s) Name Description Default R/W 15 Reserved This bit is reserved and should be set to 0b. 0 RO 14 100BASE-TX Full-duplex This bit enables 100BASE-TX full-duplex operation and is dependent on ADV10. If ADV10 is active, the default value is 0. 0 = PHY unable to perform full-duplex 100BASE-TX 1 = PHY able to perform full-duplex 100BASE-TX 1R O 13 100 Mbps Half- duplex This bit enables 100BASE-TX half-duplex operation and is dependent on ADV10. If ADV10 is active, the default value is 0. 0 = PHY unable to perform half-duplex 100BASE-TX 1 = PHY able to perform half-duplex 100BASE-TX 1R O 12 10 Mbps Full- duplex This bit enables 10BASE-T full duplex operation. 0 = PHY unable to perform full-duplex 10BASE-T 1 = PHY able to perform full-duplex 10BASE-T 1R O 11 10 Mbps Half- duplex This bit enables 10BASE-T half-duplex operation. 0 = PHY unable to perform half-duplex 10BASE-T 1 = PHY able to perform half-duplex 10BASE-T 1R O 10:7 Reserved These bits are reserved and should be set to 0b. 0 RO
6 Management
This bit allows the 82562G to receive management frames with suppressed preamble. 0 = PHY will not accept management frames with preamble suppressed 1 = PHY will accept management frames with preamble suppressed 0R O Bit(s) Name Description Default R/W
Networking Silicon — 82562G Datasheet 21
6.1.3 Register 2: PHY Identifier Register Bit Definitions
6.1.4 Register 3: PHY Identifier Register Bit Definitions
6.1.5 Register 4: Auto-Negotiation Adve rtisement Register Bit Definitions
5 Auto-Negotiation
This bit reflects status of the Auto-Negotiation process. 0 = Auto-Negotiation process has not completed 1 = Auto-Negotiation process completed 0R O
4 Remote Fault 0 = No remote fault condition detected
1 = Remote fault condition detected 0R O
3 Auto-Negotiation
This bit reflects the PHY’s Auto-Negotiation ability status. 0 = PHY is unable to perform Auto-Negotiation 1 = PHY is able to perform Auto-Negotiation 1R O 2 Link Status This bit reflects link status. 0 = Invalid link detected 1 = Valid link established 0R O LL 1 Jabber Detect This bit is used only in 10BASE-T mode. 0 = No jabber condition detected 1 = Jabber condition detected 0R O LH
0 Extended
This bit enables the extended register capabilities. 0 = Extended register capabilities disabled 1 = Extended register capabilities enabled 1R O Bit(s) Name Description Default R/W 15:0 PHY ID (high byte) Value: 02A8 hexadecimal -- RO Bit(s) Name Description Default R/W 15:0 PHY ID (low byte) Value: 0330 hexadecimal for 82562G PLC (and 82562GZ) -- RO 15:0 PHY ID (low byte) Value: 0310 hexadecimal for 82562G -- RO Bit(s) Name Description Default R/W
15 Next Page This bit is a constant 0, transmit primary capability
data page. 0R O 14 Reserved This bit is reserved and should be set to 0b. 0 RO Bit(s) Name Description Default R/W
82562G — Networking Silicon
22 Datasheet
6.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit
6.1.7 Register 6: Auto-Negotiation Ex pansion Register Bit Definitions
13 Remote Fault 0 = No remote fault
1 = Indicate link partner’s remote fault 0R W 12:5 Technology Ability Field Technology Ability Field is an 8-bit field containing information indicating supported technologies specific to the selector field value. 00101111 RW 4:0 Selector Field The Selector Field is a 5-bit field identifying the type of message to be sent by Auto-Negotiation. This field is read only and contains a value of 00001b, IEEE Standard 802.3. 00001 RO Bit(s) Name Description Default R/W
15 Next Page This bit reflects the PHY’s link partner’s Next Page
ability. -- RO
14 Acknowledge This bit is used to indicate that the 82562G has
successfully received its link partner’s Auto- Negotiation advertising ability. -- RO
13 Remote Fault This bit reflects the PHY’s link partner’s Remote Fault
condition. -- RO 12:5 Technology Ability Field This bit reflects the PHY’s link partner’s Technology Ability Field. -- RO 4:0 Selector Field This bit reflects the PHY’s link partner’s Selector Field. -- RO Bit(s) Name Description Default R/W 15:5 Reserved These bits are reserved and should be set to 0. 0 RO
4 Parallel Detection
This bit clears itself on read. 0 = No fault detected via parallel detection 1 = Fault detected via parallel detection (multiple link fault occurred) 0R O SC LH
3 Link Partner Next
0 = Link Partner is not Next Page able 1 = Link Partner is Next Page able 0R O
2 Next Page Able 0 = 0 = Local drive is not Next Page able
1 = Local drive is Next Page able 0R O 1 Page Received This bit clears itself on read. 0 = New Page not received 1 = New Page received 0R O SC LH
0 Link Partner Auto-
0 = Link Partner is not Auto-Negotiation able 1 = Link Partner is Auto-Negotiation able 0R O Bit(s) Name Description Default R/W
Networking Silicon — 82562G Datasheet 23
6.2 MDI Registers 8 through 15
Registers 8 through 15 are reserved for IEEE.
6.3 MDI Registers 16 through 31
6.3.1 Register 16: PHY Status and Control Register Bit Definitions
Bit(s) Name Description Default R/W 15:14 Reserved These bits are reserved and should be set to 00b. 00 RW
13 Reduced Power
This bit disables the automatic reduced power down. 0 = Enable automatic reduced power down 1 = Disable automatic reduced power down 1R W 12 Reserved This bit is reserved and should be set to 0b. 0 RW
11 Receive De-
This bit indicates status of the 100BASE-TX Receive De-Serializer In-Sync. -- RO 10 100BASE-TX Power-Down This bit indicates the power state of 100BASE-TX PHY unit. 0 = Normal operation 1 = Power-down 1R O 9 10BASE-T Power-Down This bit indicates the power state of 10BASE-T PHY unit. 0 = Normal operation 1 = Power-Down 1R O 8 Polarity This bit indicates 10BASE-T polarity. 0 = Normal polarity 1 = Reverse polarity -- RO 7 Reserved This bit is reserved and should be set to 0b. 0 RO 6:2 PHY Address These bits contain the sampled PHY address. -- RO 1 Speed This bit indicates the Auto-Negotiation result. 0 = 10 Mbps 1 = 100 Mbps -- RO 0 Duplex Mode This bit indicates the Auto-Negotiation result. 0 = Half-duplex 1 = Full-duplex -- RO
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24 Datasheet
6.3.2 Register 17: PHY Unit Special Control Bit Definitions
6.3.3 Register 18: Reserved
Bit(s) Name Description Default R/W
15 Scrambler By-
0 = Normal operations 1 = By-pass scrambler 0R W
14 By-pass 4B/5B 0 = Normal operation
1 = 4 bit to 5 bit by-pass 0R W
13 Force Transmit H-
0 = Normal operation 1 = Force transmit H-pattern 0R W
12 Force 34
0 = Normal operation 1 = Force 34 transmit pattern 0R W
11 Valid Link 0 = Normal operation
1 = 100BASE-TX valid link 0R W
10 Symbol Error
0 = Normal operation 1 = Symbol error output is enabled 0R W
9 Carrier Sense
This bit controls the receive 100 carrier sense disable function. 0 = Carrier sense enabled 1 = Carrier sense disabled 0R W
8 Disable Dynamic
0 = Dynamic Power-Down enabled 1 = Dynamic Power-Down disabled 0R W
7 Auto-Negotiation
0 = Auto-Negotiation normal mode 1 = Auto-Negotiation loopback 0R W 6M D I T r i - S t a t e 0 = Normal operation 1 = MDI Tri-state (transmit driver tri-states) 0R W
5 Force Polarity 0 = Normal polarity
1 = Reversed polarity 0R W 4A u t o P o l a r i t y Disable 0 = Normal polarity operation 1 = Auto Polarity disabled 0R W
3 Squelch Disable 0 = Normal squelch operation
1 = 10BASE-T squelch test disable 0R W
2 Extended
1 = 10BASE-T Extended Squelch control enabled 0 = 10BASE-T Extended Squelch control disabled 0R W
1 Link Integrity
0 = Normal Link Integrity operation 1 = Link disabled 0R W
0 Jabber Function
0 = Normal Jabber operation 1 = Jabber disabled 0R W Bit(s) Name Description Default R/W 15:0 Reserved These bits are reserved and should be set to a constant 0. 0R O
Networking Silicon — 82562G Datasheet 25
6.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit
6.3.5 Register 20: 100BASE-TX Receiv e Disconnect Counter Bit Definitions
6.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit
6.3.7 Register 22: Receive Symbol Error Counter Bit Definitions
6.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error
Bit(s) Name Description Default R/W 15:0 Receive False Carrier These bits are used for the false carrier counter. -- RO SC Bit(s) Name Description Default R/W 15:0 Disconnect Event This field contains a 16-bit counter that increments for each disconnect event. The counter stops when it is full and self-clears on read -- RO SC Bit(s) Name Description Default R/W 15:0 Receive Error Frame This field contains a 16-bit counter that increments once per frame for any receive error condition (such as a symbol error or premature end of frame) in that frame. The counter stops when it is full and self-clears on read. -- RO SC Bit(s) Name Description Default R/W 15:0 Symbol Error Counter This field contains a 16-bit counter that increments for each symbol error. The counter stops when it is full and self-clears on read. In a frame with a bad symbol, each sequential six bad symbols count as one. -- RO SC Bit(s) Name Description Default R/W 15:0 Premature End of Frame This field contains a 16-bit counter that increments for each premature end of frame event. The counter stops when it is full and self-clears on read. -- RO SC
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26 Datasheet
6.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter Bit
6.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit
Bit(s) Name Description Default R/W 15:0 End of Frame Counter This is a 16-bit counter that increments for each end of frame event. The counter stops when it is full and self-clears on read. -- RO SC Bit(s) Name Description Default R/W 15:0 Jabber Detect Counter This is a 16-bit counter that increments for each jabber detection event. The counter stops when it is full and self-clears on read. -- RO SC
Networking Silicon — 82562G Datasheet 27
6.3.11 Register 27: PHY Unit Special Control Bit Definitions
Bit(s) Name Description Default R/W 15:6 Reserved These bits are reserved and should be set to a constant 0. 0R O
5 Switch Probe
This bit switches the mapping on the LEDs. The LED mapping is described below in bits 2:0, LED Switch Control. This bit should always be set to 0b. 0R W
4 New mode If this bit equals 0, the device is in 82562EZ (or
82562ET) mode. If this bit equals 1, the device is in 82562G mode. RO 3 100BASE-TX Receive Jabber Disable This bit enables the carrier sense disconnection while the PHY is in jabber mode at 100 Mbps speed. 0R W 2:0 LED Switch Control Value 000 001 010 011 100 101 110 111 ACTLED# Activity Speed Speed Activity Off Off On On LILED# Link Collision Link Collision Off On Off On 000 RW
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device. The port provides the ability to perform basic production level testing.
7.1 Asynchronous Test Mode
7.2 Test Function Description
tests are described in the following sections. test output (TOUT) pin, are put into high-Z mode. These pins are driven to affect the tree’s output. Table 7. XOR Tree Chain Order
5 ADV10 (LAN_DISABLE#)
10 ACTLED#
30 Datasheet
11 SPDLED#
12 LILED#
8.0 Electrical and Timing Specifications
8.1 Absolute Maximum Ratings
conditions above those indicated in the operational sections of this specification is not implied.
8.2 DC Characteristics
8.2.1 X1 Clock DC Specifications
- This characteristic is only characterized, not tested. It is valid for digital pins only.
Table 8. General DC Specifications Table 9. X1 Clock DC Specifications
32 Datasheet
8.2.2 LAN Connect Interface DC Specifications
- This characteristic is only characterized, not tested. It is valid for digital pins only.
8.2.3 LED DC Specifications
NOTES:Current is measured between the transmit diff erential pins (TDP and TDN) at 3.3 V.
- RL is the resistive load measured across the transmit differential pins, TDP and TDN.
Table 10. LAN Connect Interface DC Specifications Table 11. LED DC Specifications Table 12. 10BASE-T Transmitter
- The input differential resistance is measured across the receive differential pins, RDP and RDN.
NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V.
- RL is the resistive load measured across the transmit differential pins, TDP and TDN.
- The input differential resistance is measured across the receive differential pins, RDP and RDN.
Table 13. 10BASE-T Receiver
5 MHz ≤ f ≤ 10 MHz
Table 14. 100BASE-TX Transmitter Table 15. 100BASE-TX Receiver
34 Datasheet
8.3 AC Characteristics
operation for voltage swings and slew rates that exceed the specified test conditions. Figure 5. AC Test Level Conditions Table 16. Normal Link Pulse Timing Parameters Figure 6. Normal Link Pulse Timings
8.3.2 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Table 17. Fast Link Pulse Timing Parameters Figure 7. Fast Link Pulse Timings
36 Datasheet
8.3.4 Reset (RSTSYNC) AC Specifications
Table 18. 100BASE-TX Transmitter Timing Parameters Figure 8. Reset Timing Parameters
9.0 Package and Pinout Information
9.1 Package Information
Literature Center or your local sales office. Figure 9. Dimension Diagram for the 82562G PLC 48-pin SSOP
38 Datasheet
9.2 Pinout Information
Table 20. 82562G Pin Assignments
1 VCC 13 VSS 25 VCC 37 JRXD2
2 VCCA 14 VCCT 26 TOUT 38 VSSP
3 VSSA 15 RDP 27 LILED# 39 JCLK
4 RBIAS10 16 RDN 28 ISOL_TI 40 VCCP
5 RBIAS100 17 VCCT 29 ISOL_EXEC 41 ADV10/LAN_
6 VSSA2 18 VSS 30 ISOL_TCK 42
7 VCCA2 19 VCCR 31 SPDLED# 43 JTXD0
8 VSS 20 VSSR 32 ACTLED# 44 JTXD1
9 VCCT 21 TESTEN 33 VSSP 45 JTXD2
10 TDP 22 VSSR 34 JRXD0 46 X1
11 TDN 23 VCCR 35 JRXD1 47 X2
12 VCCT 24 VSS 36 VCCP 48 VSS
Figure 10. 82562G Pin Out Diagram
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