82562EZ_08 INTEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 66
Technical content
Datasheet sections
- 1.0 Introduction
- 1.1 Scope
- 1.2 Reference Documents
- 1.3 Product Codes
- 2.0 System Data Port Interfaces
- 2.1 LCI Connection to 82562EZ(EX) Platform LAN Connect Device
- 2.2 CSA Port Connection to 82547GI(EI) Gigabit Ethernet Controller
- 2.2.1 Generation/Distribution of Reference Voltages
- 2.2.2 CSA Port Resistive Compensation
- 3.0 Ethernet Component Design Guidelines
- 3.1 General Design Considerations for Ethernet Controllers
- 3.1.1 Crystal Selection Parameters
- 3.1.2 Reference Crystal
- 3.1.3 Reference Crystal Selection
- 3.1.4 Circuit Board
- 3.1.5 Temperature Changes
- 3.1.6 Integrated Magnetics Module
- 3.2 Designing with the 82562EZ(EX) Platform LAN Connect Device
- 3.2.2 Serial EEPROM for 82562EZ(EX) Implementations
- 3.2.3 Magnetics Modules for 82562EZ(EX) PLC Device
- 3.2.4 Power Supplies for 82562EZ(EX) PLC Implementations
- 3.3 Designing with the 82547GI(EI) Gigabit Ethernet Controller
- 3.3.2 Serial EEPROM for 82547GI(EI) Controller Implementations
- 3.3.3 EEPROM Map Information
- 3.3.4 Magnetics Modules for 82547GI(EI) Controller Applications
- 3.3.5 Power Supplies for the 82547GI(EI) Device
- 4.0 Ethernet Component Layout Guidelines
- 4.1 General Layout Considerations for Ethernet Controllers
- 4.1.1 Guidelines for Component Placement
- 4.1.2 Crystals
- 4.1.3 Board Stack Up Recommendations
- 4.1.4 Differential Pair Trace Routing
- 4.1.5 Signal Trace Geometry
- 4.1.6 Trace Length and Symmetry
- 4.1.7 Impedance Discontinuities
- 4.1.8 Reducing Circuit Inductance
- 4.1.9 Signal Isolation
- 4.1.10 Power and Ground Planes
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Networking Silicon 317520-002 Revision 2.2
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The product(s) described in this document may contain design defects or errors known as errata which may cause the product to d eviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtain ed from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708- 296-9333. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries . Copyright © Intel Corporation, 2008 *Third-party brands and names are the property of their respective owners.
82562EZ(EX)/82547GI(EI) Dual Footprint
Revision History
Revision Revision Date Description 0.25 Jul 2002 Initial publication of preliminary design guide information.
0.75 Sep 2002 Published revised design guide information:
Added information on EEPROM settings Added design checklist Revised reference design schematic Revised Ball Number to signal mapping Table to conform to changes in 82547EI datasheet rev 0.75
1.0 Oct 2002 Published revised design guide information:
Added layout checklist Updated LAN disable circuit Removed EEPROM information due to publication of separate guides
1.5 Sep 2003 Published revised design guide information:
Added 82547GI coverage Removed Confidential status Updated schematics, removed redundant caps Revised LAN disable circuit 1.6 Nov 2004 Added crystal start-up information. Information includes: New crystal parameters Crystal selection guidelines Crystal validation methods Crystal testing methods Changed signal name FL_SO to the correct signal name FLSH_SO. Added 82562EX applicability. Added new values for TX and RX terminations (next to LAN silicon). New values are now 110 Ω for both TX and RX terminations. Added new starting values for RBIAS100 and RBIAS10. New starting values are now 649 Ω for RBIAS100 and 619 Ω for RBIAS10. Updated reference schematics to reflect new Tx and Rx termination values, new LAN disable circuit, and RBIAS100/RBIAS10 values. Removed excess capacitors and changed pins F12 and H12 to no connects. Added a 1K Ω resistor to pin A13 output.
1.7 Jan 2005 Changed text in the Catalyst EEPROM revision H table note from
“Revision H or higher not supported” to “Revision H is not supported”. Removed the Design and Layout Check lists. These checklists are now separate Microsoft* Excel spreadsheets.
1.8 Jan 2005 Updated reference schematics to refl ect current differential pair termination
resistor values for the 82547GI/EI. Updated section 4.2.1 “Termination Resistors for Designs Based on 82562EZ/ EX PLC Device” to reflect current resistor and RBIAS values. Updated section 4.3.1 “Termination Resistors for Designs Based on 8257GI(EI) Gigabit Ethernet Controller” to reflect current resistor values.
1.9 June 2006 Updated reference schematics for signals EE_MODE and JTAG_TRST#
(changed resistor values from 1 K Ω to 100 Ω). ESR rate from 20 Ω to 10 Ω for the 82547GI/EI). 2.1 June 2007 Updated reference schematics: sheets 4 and 6. 2.2 Jan 2008 Added Table 6; approved crystals for the 82547GI(EI).
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82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
4.1.13 Special Considerations for Non-Integrated
4.3.1 Termination Resistors for Designs Based on 82547GI(EI) Gigabit Ethernet Controller 30
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Tables
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1.0 Introduction
design technique that allowing maximized value while matching performance needs. Note: Since some of the signal pins have different usages, the term “pin-compatible” is not applicable. Controller and the 82562EZ(EX) Platform LAN Connect components. re-focus the platform without the need to redesign a new a motherboard.
1.1 Scope
Section 2 describes the port interfaces specific to each device. Section 3 explains what you need to know to hook up an Ethernet device to the system. Section 4 describes board layout techniques applicable to these devices. Section 5 provides a reference to the design and layout checklists. Table 1. LAN Component Connections/Features
Section 6 compares pin names and numbers between the two components. Section 7 concludes with a reference design schematic of the full dual footprint configuration. Note: It is assumed that the reader is acquainted with high-speed design and board layout techniques. Additional documents may be referred to for further information.
1.2 Reference Documents
82547GI(EI) Gigabit Ethernet Controller Datasheet. Intel Corporation. 82562ET/EM Platform LAN Connect Printed Circuit Board Design Guide. Intel Corporation. ICH2 Integrated LAN Controller Function Disable and Power Control. Intel Corporation. PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group. I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation. I/O Control Hub 5, 6, and 7 EEPROM Map and Programming Information. Intel Corporation. Programming information can be obtained through your local Intel representative.
1.3 Product Codes
Table 2 lists the product ordering codes for the 82562EZ(EX)and 82547GI(EI). Table 2. Product Ordering Codes
2.0 System Data Port Interfaces
controller employ different system interfaces, as illustrated in Figure 1. Figure 1. ICH5 Platform LAN Connect Sections
2.1 LCI Connection to 82562EZ(EX) Platform LAN Connect
achieve acceptable signal integrity by controlling signal reflection, undershoot and ringing.
2.2 CSA Port Connection to 82547GI(EI) Gigabit Ethernet
design guide, or the Intel® 875 Chipset design guide.
2.2.1 Generation/Distribution of Reference Voltages
voltage swing characteristics. The nominal CSA port reference voltage swing must be 0.8 V ± 3%. Figure 2. CSA Port Locally Generated Reference Divider Circuits Table 3. CSA Port Reference Circuit Specifications
1.2 V Voltage Divider Circuit
length from the voltage divider circuit to the CI_REF pins must be no longer than 3.5 inches. wide and spaced at least 20 mils from all other signals.
2.2.2 CSA Port Resistive Compensation
characteristics for temperature, voltage, and process. Figure 3. CSA port CI_RCOMP Circuits Table 4. CSA Port CI_RCOMP Resistor Values
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3.0 Ethernet Component Design Guidelines
These sections provide recommendations for selecting components and connecting special pins.
3.1 General Design Considerations for Ethernet Controllers
These recommendations apply to all designs, 10/100 or 10/100/1000 Mb/s. otherwise. Do not attach pull-up or pull-down resistors to any balls identified as No Connect. These devices may have special test modes that could be entered inadvertently.
3.1.1 Crystal Selection Parameters
package types and with various specification options. angle at which the unit is sliced with respect to the long axis of the quartz stone. parameters listed are described in the following subsections. Table 5. Crystal Parameters
.Table 6 lists the approved crystals for use with the 83547GI(EI) B1 steppings.
3.1.1.1 Vibration Mode
overtone. Unless there is a special need for third overtone, use fundamental mode crystals. values for these components is beyond the scope of this document.
3.1.1.2 Nominal Frequency
20 MHz transmit clocks, for 10BASE-T operation.
3.1.1.3 Frequency Tolerance
Note: Intel recommends a frequency tolerance of ±30 ppm.
3.1.1.4 Temperature Stability and Environmental Requirements
and its environmental requirements.
3.1.1.5 Calibration Mode
The terms “series-resonant” and “parallel-resonant” are often used to describe crystal circuits. Table 6. 82547GI(EI) Recommended Crystals
crystal’s inherent series resonant frequency. selected frequency. In other words, the crystal behaves like an inductor in a parallel LC circuit. Figure 4. Crystal Circuit
3.1.1.6 Load Capacitance
capacitance is 16 pF with an estimated stray capacitance of about 5 pF. capacitance than thick circuit boards.
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Standard capacitor loads used by crystal manufacturers include 16 pF, 18 pF and 20 pF. Any of these values will generally operate with the controller. However, a difference of several picofarads between the calibrated load and the actual load will pull the oscillator slightly off frequency. Note: C1 and C2 may vary by as much as 5% (approximately 1 pF) from their nominal values.
3.1.1.7 Shunt Capacitance
The shunt capacitance parameter is relatively unimportant compared to load capacitance. Shunt capacitance represents the effect of the crystal’s mechanical holder and contacts. The shunt capacitance should equal a maximum of 6 pF (7 pF is also acceptable).
3.1.1.8 Equivalent Series Resistance
Equivalent Series Resistance (ESR) is the real component of the crystal’s impedance at the calibration frequency, which the inverting amplifier’s loop gain must overcome. ESR varies inversely with frequency for a given crystal family. The lower the ESR, the faster the crystal starts up. Use crystals with an ESR value of 50 Ω or better. Note: Check the specific controller documentation carefully; some devices may have tighter ESR requirements. For example, Intel recommends that 82547GI(EI) devices use crystals with an ESR value of 10 Ω or less.
3.1.1.9 Drive Level
Drive level refers to power dissipation in use. The allowable drive level for a Surface Mounted Technology (SMT) crystal is less than its through-hole counterpart, because surface mount crystals are typically made from narrow, rectangular AT strips, rather than circular AT quartz blanks. Some crystal data sheets list crystals with a maximum drive level of 1 mW. However, Intel® Ethernet controllers drive crystals to a level less than the suggested 0.5 mW value. This parameter does not have much value for on-chip oscillator use.
3.1.1.10 Aging
Aging is a permanent change in frequency (and resistance) occurring over time. This parameter is most important in its first year because new crystals age faster than old crystals. Use crystals with a maximum of ±5 ppm per year aging.
3.1.2 Reference Crystal
The normal tolerances of the discrete crystal components can contribute to small frequency offsets with respect to the target center frequency. To minimize the risk of tolerance-caused frequency offsets causing a small percentage of production line units to be outside of the acceptable frequency range, it is important to account for those shifts while empirically determining the proper values for the discrete loading capacitors, C1 and C2. Even with a perfect support circuit, most crystals will oscillate slightly higher or slightly lower than the exact center of the target frequency. Therefore, frequency measurements (which determine the correct value for C1 and C2) should be performed with an ideal reference crystal. When the capacitive load is exactly equal to the crystal’s load rating, an ideal reference crystal will be perfectly centered at the desired target frequency.
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
3.1.3 Reference Crystal Selection
There are several methods available for choosing the appropriate reference crystal: If a Saunders and Associates (S&A) crystal network analyzer is available, then discrete crystal components can be tested until one is found with zero or nearly zero ppm deviation (with the appropriate capacitive load). A crystal with zero or near zero ppm deviation will be a good reference crystal to use in subsequent frequency tests to determine the best values for C1 and C2. If a crystal analyzer is not available, then the selection of a reference crystal can be done by measuring a statistically valid sample population of crystals, which has units from multiple lots and approved vendors. The crystal, which has an oscillation frequency closest to the center of the distribution, should be the reference crystal used during testing to determine the best values for C1 and C2. It may also be possible to ask the approved crystal vendors or manufacturers to provide a reference crystal with zero or nearly zero deviation from the specified frequency when it has the specified CLoad capacitance. Note: For 82547GI(EI) devices, Intel® recommends choosing a crystal with a ESR value of 10 Ω or less, an equivalent Cload of 18 pF, and a maximum of 30 ppm frequency shift. Cload is defined to be the load capacitance of the crystal, specified by the crystal vendor. When choosing a crystal, customers must keep in mind that to comply with IEEE specifications for 10/100 and 10/100/1000Base-T Ethernet LAN, the transmitter reference frequency must be precise within ±50 ppm. Intel® recommends customers to use a transmitter reference frequency that is accurate to within ±30 ppm to account for variations in crystal accuracy due to crystal manufacturing tolerance. For information about measuring transmitter reference frequency, refer to Appendix A, “Measuring LAN Reference Frequency Using a Frequency Counter”.
3.1.4 Circuit Board
Since the dielectric layers of the circuit board are allowed some reasonable variation in thickness, the stray capacitance from the printed board (to the crystal circuit) will also vary. If the thickness tolerance for the outer layers of dielectric are controlled within ±17 percent of nominal, then the circuit board should not cause more than ±2 pF variation to the stray capacitance at the crystal. When tuning crystal frequency, it is recommended that at least three circuit boards are tested for frequency. These boards should be from different production lots of bare circuit boards. Alternatively, a larger sample population of circuit boards can be used. A larger population will increase the probability of obtaining the full range of possible variations in dielectric thickness and the full range of variation in stray capacitance. Next, the exact same crystal and discrete load capacitors (C1 and C2) must be soldered onto each board, and the LAN reference frequency should be measured on each circuit board. The circuit board, which has a LAN reference frequency closest to the center of the frequency distribution, should be used while performing the frequency measurements to select the appropriate value for C1 and C2.
3.1.5 Temperature Changes
Temperature changes can cause the crystal frequency to shift. Therefore, frequency measurements should be done in the final system chassis across the system’s rated operating temperature range.
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
3.1.6 Integrated Magnetics Module
The magnetics module has a critical effect on overall IEEE and regulatory conformance. The device should meet the performance required for a design with reasonable margin to allow for manufacturing variation. Occasionally, components that meet basic specifications may cause the system to fail IEEE testing because of interactions with other components or the printed circuit board itself. Carefully qualifying new magnetics modules can go a long way toward preventing this type of problem. The steps involved in magnetics module qualification are similar to those for oscillator qualification: 1. Verify that the vendor's published specifications in the component datasheet meet the required IEEE specifications. 2. Independently measure the component's electri cal parameters on the test bench, checking samples from multiple lots. Check that the measured behavior is consistent from sample to sample as well as meeting the published specifications. 3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems. Vary temperature and voltage while performing system level tests (for IEEE only). Magnetics modules for 1000BASE-T Ethernet are similar to those designed solely for 10/100 Mbps, with the exception of four differential signal pairs instead of two for 10/100 Mbps.
3.2 Designing with the 82562EZ( EX) Platform LAN Connect
This section provides design guidelines specific to the PLC device. 3.2.1 82562EZ/EX PLC Device LAN Disable Guidelines Note: ICHx Integrated LAN Controller resides on the ICHx VccSus3_3 and VccSus1_8 power wells (typically referred to as “auxiliary” (“aux”) or “standby” supplies at the platform level). The ICHx Integrated LAN’s RST# is the ICHx Resume-well input. It can be held low indefinitely to keep the ICHx Integrated LAN Controller in a reset state. The LAN Reset (RST#) signal must not be deasserted sooner than 10 ms after the Resume power supply reaches its nominal voltage. This ensures that the ICHx Integrated LAN Controller is initialized. Figure 5 illustrates a possible solution for ICHx Integrated LAN disable.
Figure 5. LAN Disable Circuitry
3.2.2 Serial EEPROM for 82562EZ(EX) Implementations
Serial EEPROM for LAN implementations based on 82562EZ(EX) devices connects to the ICH5. Map and Programming Information. NOTE: No manageability provided. Table 7. 82562EZ(EX) Memory Layout (128 Byte EEPROM)
NOTE: Legacy manageability only.
3.2.3 Magnetics Modules fo r 82562EZ(EX) PLC Device
contain integrated USB jacks.
3.2.4 Power Supplies for 82562EZ(EX) PLC Implementations
operation are contained in the 82562ET LAN on Motherboard Design Guide.
3.3 Designing with the 82547GI(EI) Gigabit Ethernet Controller
This section provides design guidelines specific to the 82547GI(EI) controller. The 82547GI(EI) Controller has a LAN_DISABLE# function that is present on FLSH_SO ball P9. serial output pin does not interfere with this function. Table 8. 82562EZ(EX) Memory Layout (512 Byte EEPROM) Table 9. 82562EZ(EX) Recommended Magnetics Modules
For best results, do not attempt to use the LAN_POWER_GOOD signal for a LAN disable input. This pin is intended to operate as a power-on reset connected to a power monitor circuit. LAN_PWR_GOOD and/or RST#. The signal must be held valid for 80 ns after either rising edge.
- Most MAC clock domains are gated.
- Most functional blocks are held in reset.
- The device is in a low power state – equivalent to D3 w/ no wake or manageability.
gate U1 is populated. Depopulate the 0 Ω resistor R2. Figure 6. 82547GI(EI) LAN Disable Circuitry
3.3.2 Serial EEPROM for 82547GI(EI) Controller Implementations
software for storing the MAC address, serial numbers, and additional information.
0 Ohm
program, contact your Intel representative. algorithm drives extra pulses on the shift clock at the beginnings and ends of read and write cycles. serial EEPROM, choose a device that specifies “don't care” shift clock states between accesses. in Table 11. SPI EEPROMs must be rated for a clock rate of at least 2 MHz. Table 10. Microwire 64 x 16 Serial EEPROMs
- Revision H is not supported. Product die revision letter is marked on top of the package as a suffix to the production data
Table 11. SPI Serial EEPROMs for 82547GI(EI) Controller
3.3.3 EEPROM Map Information
Table 12 summarizes the EEPROM map for the 82547GI(EI) Gigabit Ethernet Controller. Table 12. 82547GI(EI) EEPROM Memory Layout Note: Full manageability provided.
3.3.4 Magnetics Modules for 82547GI(EI) Controller Applications
82562EZ(EX) Platform LAN Connect device.
3.3.5 Power Supplies for the 82547GI(EI) Device
approximately 550 mA current. The 1.8 V supply must provide approximately 230 mA current. The 3.3 V supply must provide only 5 mA current. Table 13. 82547GI(EI) Recommended Magnetics Modules
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Instead of using external regulators to supply 1.2 V and 1.8 V , the designer can use power transistors in conjunction with on-chip regulation circuitry. See the reference schematic for an implementation example. The 82547GI(EI) controller has a LAN_PWR_GOOD input. Treat this signal as an external device reset which works in conjunction with the internal power-on reset circuitry. In the situation where a central power supply furnishes all the voltage sources, LAN_PWR_GOOD can possibly be tied to the POWER_GOOD output of the power supply. Designs that generate some of the voltages locally can connect LAN_PWR_GOOD to a power monitor chip. Ensure that the system drives LAN_PWR_GOOD inactive for at least 80 ms after power-up. The power sources are all expected to ramp up during a brief power-up interval (approximately 20 ms.) with LAN_PWR_GOOD de-asserted. Do not leave the 82547GI(EI) controller in a prolonged state where some, but not all, voltages are applied. 3.3.6 82547GI(EI) Controller Power Supply Filtering Provide several bypass capacitors for each power rail, selecting values in the range of 0.01µF to 0.01 µF. If possible, orient the capacitors close to the device and adjacent to power pads. Decoupling capacitors should connect to the power planes with short, thick (15 mils - 0.4mm or more) traces and 14 mil (0.35 mm) vias. Furnish approximately 20 µF of bulk capacitance for each of the main 1.2 V and 1.8 V levels. A convenient way to do this is to use about two 10 µF capacitors, placing them as close to the device power connections as possible. 3.3.7 82547GI(EI) Controller Powe r Management and Wake Up The 82547GI(EI) Gigabit Ethernet Controller supports low power operation as defined in the PCI Bus Power Management Specification. There are two defined power states, D0 and D3. The D0 state provides full power operation and is divided into two sub-states: D0u (uninitialized) and D0a (active). The D3 state provides low power operation and is also divided into two sub-states: D3hot and D3cold. To enter the low power state, the software driver must stop data transmission and reception. Either the operating system or the driver must program the Power Management Control/Status Register (PMCSR) and the Wakeup Control Register (WUC). If wakeup is desired, the appropriate wakeup LAN address filters must also be set. The initial power management settings are specified by EEPROM bits. When the 82547GI(EI) controller transitions to either of the D3 low power states, the 1.2 V , 1.8 V , and 3.3 V sources must continue to be supplied to the device. Otherwise, it will not be possible to use a wakeup mechanism. The AUX_POWER signal is a logic input to the 82547GI(EI) controller that denotes auxiliary power is available. If AUX_POWER is asserted, the 82547GI(EI) device will advertise that it supports wake up from a D3cold state. The 82547GI(EI) device supports both Advanced Power Management (APM) wakeup and Advanced Configuration and Power Interface (ACPI) wakeup. APM wakeup has also been known in the past as “Wake on LAN”. Wakeup uses the PME# signal to wake the system up. PME# is an active low signal connected to a GPIO port on the ICH5 that goes active in response to receiving a “Magic Packet”, a network wakeup packet, or link status change indication. PME# remains asserted until it is disabled through the Power Management Control/Status Register.
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 3.3.8 82547GI(EI) Device Test Capability The 82547GI(EI) Gigabit Ethernet Controller contains a test access port conforming to the IEEE 1149.1a-1994 (JTAG) Boundary Scan specification. To use the test access port, connect these balls to pads accessible by your test equipment. Be sure to connect the TRST# input to ground through a pull-down resistor (approximately 1k value) so that the test capability cannot be invoked by mistake. A BSDL (Boundary Scan Definition Language) file describing the 82547GI(EI) device is available for use in your test environment. The controller also contains an XOR test tree mechanism for simple board tests. Details of XOR tree operation may be obtained through your Intel representative.
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82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
4.0 Ethernet Component Layout Guidelines
These sections provide recommendations for performing printed circuit board layouts. Good layout practices are essential to meet IEEE PHY conformance specifications and EMI regulatory requirements.
4.1 General Layout Considerations for Ethernet Controllers
Critical signal traces should be kept as short as possible to decrease the likelihood of being affected by high frequency noise from other signals, including noise carried on power and ground planes. Keeping the traces as short as possible can also reduce capacitive loading. Since the transmission line medium extends onto the printed circuit board, special attention must be paid to layout and routing of the differential signal pairs. Designing for Gigabit operation is very similar to designing for 10 and 100 Mbps. For the 82547GI(EI) Gigabit Ethernet controller, system level tests should be performed at all three speeds.
4.1.1 Guidelines for Component Placement
Component placement can affect signal quality, emissions, and component operating temperature. This section provides guidelines for component placement. Careful component placement can: Decrease potential problems directly related to electromagnetic interference (EMI), which could cause failure to meet applicable government test specifications. Simplify the task of routing traces. To some extent, component orientation will affect the complexity of trace routing. The overall objective is to minimize turns and crossovers between traces. Minimizing the amount of space needed for the Ethernet LAN interface is important because other interfaces will compete for physical space on a motherboard near the connector. The Ethernet LAN circuits need to be as close as possible to the connector (see Figure 5).
Figure 5. General Placement Distances Ethernet silicon would be approximately one inch behind the magnetics module.
4.1.2 Crystals
4.1.3 Board Stack Up Recommendations
connector side of the magnetics module.
Layer 3 is used for power planes. This board stack up configuration can be adjusted to conform to your company's design rules.
4.1.4 Differential Pa ir Trace Routing
Maintain constant symmetry and spacing between the traces within a differential pair. Keep the signal trace lengths of a differential pair equal to each other. mils to the differential traces (300 mils is recommended). Keep maximum separation within differential pairs to seven mils. bend is required, it is recommended to use two 45° bends instead. See Figure 6. ground plane rather than to adjacent wires or boards. from apertures by a distance that is greater than the largest aperture dimension. Figure 6. Trace Routing
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide The reference plane for the differential pairs should be continuous and low impedance. It is recommended that the reference plane be either ground or 1.8 V (the voltage used by the PHY). This provides an adequate return path for and high frequency noise currents. Do not route differential pairs over splits in the associated reference plane. Differential termination components should be placed as close as possible to the LAN silicon.
4.1.5 Signal Trace Geometry
The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width to trace-height above the ground plane. To minimize trace inductance, high-speed signals and signal layers that are close to a ground or power plane should be as short and wide as practical. Ideally, this trace width to height above the ground plane ratio is between 1:1 and 3:1. To maintain trace impedance, the width of the trace should be modified when changing from one board layer to another if the two layers are not equidistant from the power or ground plane. Each pair of signal should have a differential impedance of 100 Ω. +/- 20%. If a particular tool cannot design differential traces, it is permissible to specify 55-65 Ω single-ended traces as long as the spacing between the two traces is minimized. As an example, consider a differential trace pair on Layer 1 that is eight mils (0.2 mm) wide and two mils (0.05 mm) thick, with a spacing of eight mils (0.2mm). If the fiberglass layer is eight mils (0.2 mm) thick with a dielectric constant, ER, of 4.7, the calculated single-ended impedance would be approximately 61 Ω and the calculated differential impedance would be approximately 100 Ω. When performing a board layout, do not allow the CAD tool auto-router to route the differential pairs without intervention. In most cases, the differential pairs will have to be routed manually. The components should be laid out in the following order of priority: 1. Differential traces 2. Termination resistors 3. Bypass capacitors 4. Other components This allows placing those components in the best locations and avoids using critical space by non- critical components. Note: Measuring trace impedance for layout designs targeting 100 Ω often results in lower actual impedance. Designers should verify actual trace impedance and adjust the layout accordingly. If the actual impedance is consistently low, a target of 105 to 110 Ω should compensate for second order effects. It is necessary to compensate for trace-to-trace edge coupling, which can lower the differential impedance by up to 10 Ω, when the traces within a pair are closer than 30 mils (edge to edge).
4.1.6 Trace Length and Symmetry
As indicated earlier in Section 4.1.4, the overall length of differential pairs should be less than four inches measured from the Ethernet device to the magnetics. The differential traces should be equal within 50 mils (1.25 mm) within each pair and as symmetrical as possible. Asymmetrical and unequal length traces in the differential pairs contribute to common mode noise. Common mode noise can degrade the receive circuit’s performance and contribute to radiated emissions.
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
4.1.7 Impedance Discontinuities
Impedance discontinuities cause unwanted signal reflections. Avoid vias (signal through holes) and other transmission line irregularities. If vias must be used, a reasonable budget is two per differential trace. Unused pads and stub traces should also be avoided.
4.1.8 Reducing Circuit Inductance
Traces should be routed over a continuous ground plane with no interruptions. If there are vacant areas on a ground or power plane, the signal conductors should not cross the vacant area. This increases inductance and associated radiated noise levels. Noisy logic grounds should be separated from analog signal grounds to reduce coupling. Noisy logic grounds can sometimes affect sensitive DC subsystems such as analog to digital conversion, operational amplifiers, etc. All ground vias should be connected to every ground plane; and similarly, every power via, to all power planes at equal potential. This helps reduce circuit inductance. Another recommendation is to physically locate grounds to minimize the loop area between a signal path and its return path. Rise and fall times should be as slow as possible. Because signals with fast rise and fall times contain many high frequency harmonics, which can radiate significantly. The most sensitive signal returns closest to the chassis ground should be connected together. This will result in a smaller loop area and reduce the likelihood of crosstalk. The effect of different configurations on the amount of crosstalk can be studied using electronics modeling software.
4.1.9 Signal Isolation
To maintain best signal integrity, keep digital signals far away from the analog traces. A good rule of thumb is no digital signal should be within 300 mils (7.5 mm) of the differential pairs. If digital signals on other board layers cannot be separated by a ground plane, they should be routed at right angles with respect to the differential pairs. If there is another LAN controller on the board, take care to keep the differential pairs from that circuit away. Some rules to follow for signal isolation: Separate and group signals by function on separate layers if possible. Maintain a gap of 100 mils between all differential pairs (Ethernet) and other nets, but group associated differential pairs together. Note: Over the length of the trace run, each differential pair should be at least 0.3 inches away from any parallel signal traces. Physically group together all components associated with one clock trace to reduce trace length and radiation. Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI emission and susceptibility to EMI from other signals. Avoid routing high-speed LAN traces near other high-frequency signals associated with a video controller, cache controller, processor, or other similar devices.
4.1.10 Power and Ground Planes
Good grounding requires minimizing inductance levels in the interconnections and keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly reduce EMI radiation.
the vacant area. This will increase inductance and EMI radiation levels. may affect sensitive DC subsystems. connected to all power planes at equal potential. This helps reduce circuit inductance. many high frequency harmonics, which can radiate EMI.
4.1.11 Traces for Decoupling Capacitors
and thin traces are more inductive and would reduce the intended effect of decoupling capacitors.
4.1.12 Ground Planes Unde r the Magnetics Module
the primary and secondary sides of the transformer and between the adjacent coils in the magnetics. This arrangement also improves the common mode choke functionality of magnetics module. interconnect chassis ground and signal ground. Figure 7. Ground Plane Separation
0.10 Inches Minimum Spacing
4.1.13 Special Considerations for N on-Integrated Magnetics Modules and
magnetics module) should not exceed approximately four inches. termination scheme is normally contained inside an integrated magnetics module. through 75 Ω resistors to the plane. Stray energy on unused pins is then carried to the plane. Figure 9. Termination Plane Example for 82562EZ(EX) PLC Device and Discrete Magnetics
4.2 Layout for the 82562EZ(EX) Platform LAN Connect Device
This section provides layout guidelines specific to the 82562EZ(EX) PLC device.
4.2.1 Termination Resistors for De signs Based on 82562EZ(EX) PLC
connects to the MDI- (MDI negative) signal trace (see Figure 10). Termination resistor values were recently increased from 49.9 Ω to 54.9 Ω to improve return loss. better meet the IEEE peak-to-peak center specification. +1025 mVpk for the positive peak. Figure 10. 82562EZ(EX) PLC Device Differential Signal Termination
4.2.2 Light Emitting Diodes for Desi gns Based on 82562EZ(EX) PLC Device
desirable to attach filter capacitors. Place termination resistors as close to the Intel LAN device as possible.
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
4.3 Layout for the 82547GI(EI) Gigabit Ethernet Controller
4.3.1 Termination Resistors for Designs Based on 82547GI(EI) Gigabit
The four differential pairs are terminated with 49.9 Ω (1% tolerance) resistors, placed near the 82547GI(EI) controller. One resistor connects to the MDI+ signal trace and another resistor connects to the MDI- signal trace. The opposite ends of the resistors connect together and to ground through a single 0.1 µF capacitor. The capacitor should be placed as close as possible to the 49.9 Ω resistors, using a wide trace. Do not vary the suggested component values. Be sure to lay out symmetrical pads and traces for these components such that the length and symmetry of the differential pairs are not disturbed.
4.3.2 Light Emitting Diode s for Designs Based on 82547GI(EI) Controller
The 82547GI(EI) controller provides four programmable high-current outputs to directly drive LEDs for link activity and speed indication. Since the LEDs are likely to be integral to a magnetics module, take care with care to route the LED traces away from potential sources of EMI noise. In some cases, it may be desirable to attach filter capacitors.
4.4 Physical Layer Conformance Testing
Physical layer conformance testing (also known as IEEE testing) is a fundamental capability for all companies with Ethernet LAN products. PHY testing is the final determination that a layout has been performed successfully. If your company does not have the resources and equipment to perform these tests, consider contracting the tests to an outside facility. Crucial tests are as follows, listed in priority order: Bit Error Rate (BER). Good indicator of real world network performance. Perform bit error rate testing with long and short cables and many link partners. The test limit is 10-11 errors. Output Amplitude, Rise and Fall Time (10/100 Mbps), Symmetry and Droop (1000 Mbps). For the 82547GI(EI) controller, use the appropriate PHY test waveform. Return Loss. Indicator of proper impedance matching, measured through the RJ-45 connector back toward the magnetics module. Jitter Test (10/100 Mbps) or Unfiltered Jitter Test (1000 Mbps). Indicator of clock recovery ability (master and slave for Gigabit controller).
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
4.5 Troubleshooting Common Physical Layout Issues
The following is a list of common physical layer design and layout mistakes in LAN On Motherboard Designs. 1. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise and will distort the transmit or receive waveforms. 2. Lack of symmetry between the two traces w ithin a differential pair. Asymmetry can create common-mode noise and distort the waveforms. For each component and/or via that one trace encounters, the other trace should encounter the same component or a via at the same distance from the Ethernet silicon. 3. Excessive distance between the Ethernet silicon and the magnetics. Long traces on FR4 fiberglass epoxy substrate will attenuate the analog signals. In addition, any impedance mismatch in the traces will be aggravated if they are longer than the four inch rule. 4. Routing any other trace parallel to and close to one of the differential traces. Crosstalk getting onto the receive channel will cause degraded long cable BER. Crosstalk getting onto the transmit channel can cause excessive EMI emissions and can cause poor transmit BER on long cables. At a minimum, other signals should be kept 0.3 inches from the differential traces. 5. Routing one pair of differential traces too clos e to another pair of differential traces. After exiting the Ethernet silicon, the trace pairs should be kept 0.3 inches or more away from the other trace pairs. The only possible exceptions are in the vicinities where the traces enter or exit the magnetics, the RJ-45 connector, and the Ethernet silicon. 6. Use of a low quality magnetics module. 7. Re-use of an out-of-date physical layer schematic in a Ethernet silicon design. The terminations and decoupling can be different from one PHY to another. 8. Incorrect differential trace impedances. It is important to have ~100 Ω impedance between the two traces within a differential pair. This becomes even more important as the differential traces become longer. To calculate differential impedance, many impedance calculators only multiply the single-ended impedance by two. This does not take into account edge-to-edge capacitive coupling between the two traces. When the two traces within a differential pair are kept close to each other, the edge coupling can lower the effective differential impedance by 5 Ω to 20 Ω. Short traces will have fewer problems if the differential impedance is slightly off target. 9. For 82562EZ(EX) PLC designs, use of capacitor that is too large between the transmit traces and/or too much capacitance on the magnetic module's transmit center tap to ground. Using capacitors more than a few pF in either of these locations can slow the 100 Mbps rise and fall time. This will also cause return loss to fail at higher frequencies and will degrade the transmit BER performance. If a capacitor is used, it should almost certainly be less than 22 pF.
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5.0 Design and Layout Checklists
The Design and Layout checklists are in Portable Data Format (PDF) and available to aid designers via: http://developer.intel.com.
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6.0 Ball Number to Signal Mapping with Population
schematic names follow conventions used by Intel design engineers on their design tools. Table 14. Ball Number to Signal Mapping (Sheet 1 of 7)
C13 TDP MDI[0]+ X X X Connected to magnetics. C14 TDN MDI[0]- X X X Connected to magnetics. Table 14. Ball Number to Signal Mapping (Sheet 2 of 7) (Continued)
D10 ISOL_EXEC NC X X X 82562EZ: No Connect. D12 ISOL_TI 1.8 V X X X 82562EZ: No Connect. D14 ISOL_TCK IEEE_TEST- X X X 82562EZ: No Connect. E13 RDP MDI[1]+ X X X Connected to magnetics. E14 RDN MDI[1]- X X X Connected to magnetics. Table 14. Ball Number to Signal Mapping (Sheet 3 of 7) (Continued)
Table 14. Ball Number to Signal Mapping (Sheet 4 of 7) (Continued)
Table 14. Ball Number to Signal Mapping (Sheet 5 of 7) (Continued)
L7 ADV10 NC X X X 82562EZ: No Connect. Table 14. Ball Number to Signal Mapping (Sheet 6 of 7) (Continued)
Table 14. Ball Number to Signal Mapping (Sheet 7 of 7) (Continued)
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7.0 Dual Footprint Reference Schematic
The following pages illustrate a dual purpose 10/100 and 10/100/1000 design using the 82562EZ(EX) Platform LAN Connect device and the 82547GI(EI) Gigabit Ethernet Controller.
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82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide IntelR 82562EZ/EX - 82547GI/EI 10/100/1000 MbpsEthernet Controller with Communications Streaming Architecture (CSA) VDD Pins VSS Pins Reserved Pins Reserved Pins 2 of 2 Pin Name Decode = 82562EZ/EX Signal Name - 82547GI/EI Signal Name 15mm x 15mm BGA 1mm Pitch Place these capacitorsclose to their respectivepins of the 82547GI(EI). Place thesecapacitorsclose to the dividernetwork. Internal PHY clocktest point. IEEE conformance testing.Place this capacitorclose to it's respectivepin of the 82547GI(EI). 82562EZ/EX - 82547GI/EI Ref. Design D/T Install this component only when using the 82562EZ/EX Controller Install this component only when using the 82547GI/EI Controller A B Install only for special debug or testing purposes
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82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide IntelR Install only for special debug or testing purposes BA Install this component only when using the 82547GI/EI Controller Install this component only when using the 82562EZ/EX Controller D/T 82562EZ/EX - 82547GI/EI Ref. Design This LAN_DISABLE circuit is for the 82562EZ(EX) only. RSM_RST# should not be asserteduntil 50 ms after the LAN power rails are stable. Note: For the 82562EZ(EX) the BIOS must delay driving LAN_RST# for 20ms after resetting the ICH.Use the AND gate shown if this timing is not already accounted for in your design. Choose Super IO pin that defaults to input on power up and ispowered from the Resume (AUX) well Linear Regulators: Stuff only for 82547GI(EI) Bypass Caps for 1.2V COREVDD Place Close To LAN silicon If Alerting is supported, VCC3_3 is sourced from either PCI_AUX_3.3v or the planar 3.3v_STBY. Otherwise VCC3_3 can be sourced from a non-standby 3.3v power rail.VCC3_3 Supply Note:
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82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Appendix A Measuring LAN Reference Frequency Using a Frequency Counter A.1 Background To comply with IEEE specifications for 10/100 Mbps and 10/100/1000Base-T Ethernet LAN, the transmitter reference frequency must be correct and accurate within ±50 parts per million (ppm). Note: Intel recommends a frequency tolerance of ±30 (ppm). Most Intel LAN devices will operate properly with a 25.000 MHz reference crystal, provided it meets the recommended requirements for frequency stability, equivalent series resistance at resonance (ESR), and load capacitance. Most circuits for series resonant crystals include two discrete capacitors (typically C1 and C2), with values between 5 pF and 36 pF. The most accurate way to determine the appropriate value for the discrete capacitors is to install the approximately correct values for C1 and C2. Next, a frequency counter should be used to measure the transmitter reference frequency (or transmitter reference clock). If the transmitter reference frequency is more than 20 ppm below the target frequency, then the values for C1 and C2 are too big and should be decreased. If the transmitter reference frequency is more than 20 ppm above the target frequency, then the values for C1 and C2 are too small and should be increased. This Appendix provides instructions and illustrations that explain how to use a frequency counter and probe to determine the Ethernet LAN device transmit center frequency. An example describing how to calculate the frequency accuracy of the measured and averaged center frequency with respect to the target center frequency is also included. A.2 Required Test Equipment Tektronix CMC-251, or similar high resolution, digital counter Tektronix P6246, or similar high bandwidth, low capacitance (less than 1 pF) probe Tektronix 1103, or similar probe power supply or probe amplifier BNC, 50-ohm coaxial cable (less than 6 feet long) System with power supply and test software for the LAN circuit to be tested
method is to use the indirect probing test method when possible. MHz clock will be a 5X multiple of the crystal circuit’s reference frequency (Figure 11). Figure 11. Indirect Probing Setup
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide A.4 Indirect Frequency Measurement and Frequency Accuracy Calculation Steps 1. Make sure the system BIOS has the LAN controller enabled. 2. Connect the test equipment as shown in Figure 11. 3. Using the appropriate controls for your model of high resolution digital counter, make sure it can display ~125.0000 MHz with at least four decimal places frequency resolution. 4. Enable the 125 MHz buffered referen ce clock. An example can be found in Appendix B, “GigConf.exe Register Settings for 82547GI(EI) Devices”. 5. Determine the center reference frequency as accurately as possible. This can be done by taking 30 to 50 different readings using the frequency counter and then calculating the average results of the readings. 6. Calculate the accuracy of the measured and aver aged center frequency with respect to an ideal 125.0000 MHz reference frequency. where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz Example 1. Given: The measured averaged center frequency is 124.99942 MHz (or 124,999,420 Hertz). FrequencyAccuracy ppm() xy–() FrequencyAccuracy ppm() 124999420 125000000–()
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Example 2. Given: The measured averaged center frequency is 125.00087 MHz (or 125,000,870 Hertz). Note: The following items should be noted for an ideal reference crystal on a typical printed circuit board. If the transmitter reference frequency is more than 8 ppm below the target frequency, then the values for C1 and C2 are too big and they should be decreased. When tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. If the transmitter reference frequency is more than 8 ppm above the target frequency, then the values for C1 and C2 are too small and they should be increased. When tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. A.5 Direct Probing Test Method, Applicable for Most 10/100 Devices (Devices that do NOT support 1000Base-T) Because probe capacitance can load the reference crystal affecting the measured frequency, it is preferable to use a probe with less than 1 pF capacitance. Note: Direct probing is not recommended for the 82547GI(EI) LAN silicon. The probe should be connected between the X2 (or Xout) pin of the LAN device and a nearby ground. Typically, it is possible to connect the probe pins across one of the discrete load capacitors (C2 in Figure 12). FrequencyAccuracy ppm() 125000870 125000000–()
Figure 12. Direct Probing Method
- Make sure the system BIOS has the LAN controller enabled.
- Connect the test equipment as shown in Figure 12.
- Using the appropriate controls for your model of high resolution digital counter, make sure it
can display ~25.0000 MHz with at least four decimal places frequency resolution.
- Ensure the LAN circuits are powered.
- Determine the center reference frequency as accurately as possible. This can be done by taking
- Calculate the accuracy of the measured and aver aged center frequency with respect to an ideal
25.0000 MHz reference frequency.
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz Example 3. Given: The measured averaged center frequency is 24.99963 MHz (or 24,999,630 Hertz). Example 4. Given: The measured averaged center frequency is 25.00027 MHz (or 25,000,270 Hertz). Note: The following items should be noted for an ideal reference crystal on a typical printed circuit board. If the transmitter reference frequency is more than 8 ppm below the target frequency, then the values for C1 and C2 are too big and they should be decreased. When tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. If the transmitter reference frequency is more than 8 ppm above the target frequency, then the values for C1 and C2 are too small and they should be increased. When tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. FrequencyAccuracy ppm() xy–() FrequencyAccuracy ppm() 24999630 25000000–() FrequencyAccuracy ppm() 25000270 25000000–()
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Appendix B GigConf.exe Register Settings for 82547GI(EI) Devices The following steps describe the indirect probing test method using GigConf.exe for 82547GI(EI) devices. 1. Boot to DOS using a DOS Boot Diskette . 2. Launch Gigconf from the diskette (gigconf.exe) . 3. Select the Intel network connection to be measured . a. If multiple adapters are installed, use the arrow keys to navigate to highlight the selected adapter and press Enter. 4. Select Registers by pressing “R”. 5. Select PHY Registers by pressing “P ”. 6. Use the arrow keys to navigate to the value listed next to address 0000 . 7. Press Enter when the value is highlighted an d then use Backspace to clear out the current value. 8. Type “0100” for the value and then press Enter. 9. Navigate to the value listed next to address 0012 . 10. Press Enter to select the highlighted value and use Backspace to clear the current value. 11. Type “8000” for the value and then press Enter. 12. Navigate to the Set Address field on the right side of the screen (use the right arrow key) 13. Press Enter to select the highlighted value and then use Backspace to clear out the current value. 14. Type “4011” for the value and then press Enter. This changes the PHY register screen and updates it with new addresses and values. 15. Use the arrow keys to navigate to the value for address 4011. 16. Press Enter when the value is highlighted and then use Backspace to clear the current value. 17. Type “8000” for the value and then press Enter. 18. Use the right arrow key to navigate to the Set Address field on the right side of the screen . 19. Press Enter when the value is highlighted and use Backspace to clear the current value. 20. Enter “2F5B” (capital letters are not required) for the address and then press Enter. 21. Use the arrow keys to navigate to the value for address “2F5B”. 22. Press Enter when the value is highlighted and then use Backspace to clear the current value. 23. Type “0003” for the value and then press Enter. 24. Use the right arrow key to navigate to the Set Address field on the right side of the screen . 25. Press Enter when the value is highlighted and then use Backspace to clear the current value.
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