82551QM

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Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 120

Technical content

Datasheet sections

• 1.0 Introduction
• 1.1 Overview
• 1.2 Byte Ordering
• 1.3 References
• 1.4 Product Ordering Codes
• 2.0 Architectural Overview
• 2.1 Parallel Subsystem Overview
• 2.2 FIFO Subsystem Overview
• 2.3 Manageability Subsystem Overview
• 3.0 Performance Enhancements
• 3.1 Multiple Priority Transmit Queues
• 3.2 Early Release
• 3.3 Hardware Integrity Support
• 3.4 Management Data Interfac e MDI/MDI-X Feature
• 4.0 Signal Descriptions
• 4.1 Signal Type Definitions
• 4.2 PCI Bus and CardBus Interface Signals
• 4.2.1 Address and Data Signals
• 4.2.2 Interface Control Signals
• 4.2.3 System and Power Management Signals
• 4.3 Local Memory Interface Signals
• 4.4 System Management Bus (SMB) Interface Signals
• 4.5 Test Port Signals
• 4.6 PHY Signals
• 4.7 Power and Ground Signals
• 5.0 Media Access Control Functional Description
• 5.1 Device Initialization
• 5.1.1 Initialization Effects
• 5.1.2 Initialization Effects on TCO Functionality
• 5.2 PCI and CardBus Interfac e
• 5.2.1 Bus Operations
• 5.2.2 Clock Run Signal
• 5.2.3 Power Management Event and Card Status Change Signals
• 5.3 PCI Power Management
• 5.3.1 Power States
• 5.3.2 Wake-up Events
• 5.4 CardBus Power Management
• 5.5 Wake on LAN (Preboot Wake-up)
• 5.6 Parallel Flash/Modem Interface
• 5.7 Serial EEPROM Interface

Networking Silicon - 82551QM Datasheet Product Features  Enhanced IP Protocol Support — TCP, UDP, IPv4 Checksum Offload — Received Checks um Verification  Quality of Service (QoS) — Multiple Priority Transmit Queues  Optimum Integration for Lowest Cost Solution — Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY — 32-bit PCI/CardBus master interface — Modem interface for combination solutions — Integrated power ma nagement functions — Thin BGA 15mm 2 package  PHY detects polarity, MDI-X, and cable lengths. Auto MDI/MDI-X crossover at all speeds  XOR tree mode support  Wired for Reduced Total Cost of Ownership (TCO) — Wired for Management support — Integrated Alert Standard Format — ACPI and PCI Power Ma nagement standards compliance — Wake on “interesting” pa ckets and link status change support — Magic Packet* support — Remote power up support  High Performance Networking Functions — Early release — 8255x controller family chained memory structure — Improved dynamic transmit chaining with multiple priorities transmit queues — Full pin compatibility with the 82559 and 82550 controllers — Backward compatible software to the 8255x controller family (IPSec not supported) — Full Duplex support at 10 and 100 Mbps — IEEE 802.3u Auto-Negotiation support — 3 KB transmit and receive FIFOs — Fast back-to-back transmission support with minimum interframe spacing — IEEE 802.3x 100BASE-TX Flow Control support — Adaptive Technology  Low Power Features — Advanced Power Mana gement capabilities — Low power 3.3 V device — Efficient dynami c standby mode — Deep power down support — Clock Run protocol support  82551QM Enhancements — Improved Bit Error Rate performance — Integrated UNDI ROM support — HWI support — Deep power-down state power reduction  Lead-free1 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUXXXXX. 317803-004 Revision 4.0 1 This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/ material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales Rerepresentative.

Revision History

Oct 2001 0.6 • Removed references to IPSec support and changed description of FLA1/AUXPWR to use a pull-up resistor if auxiliary power is present, else leave it disconnected.

• Changed description of VCCR to show connecting it directly to main 3.3V supply and reduced text describing bus operations.
• Reduced PHY functional description to overview level and reorganized manageability section, adding ASF text. Added 0Fh as Revision ID and added targeted Icc specs. Dec 2001 1.0 • Added description for No Connect pins and corrected typographical errors. Apr 2002 2.0 Changed document status to Intel Confidential. Mar 2003 2.1 • Removed document status and removed references to MDI/MDI-X feature, which is not sup- ported by the 82551QM Jun 2003 3.0 • Added information for the 82551IT. Oct 2003 3.1 • Corrected operating temperature range in specifications to 0° to 70° C. Mar 2004 3.11 • Added operating temperature reference to Section 1.1 Oct 2004 3.2 • Removed operating temperature reference to Section 1.1.
• Added references to MDI/MDI-X feature, which is now supported by the 82551QM and removed information for the 82551IT. Nov 2004 3.3 • Updated the section describing “Multiple Priority Transmit Queues”.
• Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information.
• Added statement that no changes to existing soldering processes are needed for the 2-layer 0.32 mm wide-trace substrate change in the section describing “Package Information”. Jan 2005 3.4 • Added a note for PHY signals RBIAS100 and RBIAS10 to Table 9. Apr 2006 3.5 • Changed case temperature specification to “0° C to 85° C”. Oct 2006 3.6 • Added Figure 31 “196 PBGA Package Pad Detail”. The figure shows solder resist opening and metal diameter dimensions. July 2007 3.7 • Added Section 15 “Reference Schematics”, updated Section 12.1 (changed Tcase to ambient) and added ordering information to Section 1.4. Sept 2007 3.8 • Updated Figures 34 and 35. Added Digital I/O and Crystal Input One (X1) Characteristics (Tables 70 and 71). Updated Section 5.8.4. Mar 2008 3.9 • Updated Figure 35: changed TEST pull down resistor value (62 K  to 1 K). Nov 2008 4.0 • Updated Table 9 (X1 and X2 pin descriptions).
• Updated Tables 70 and 71 (Digital I/O and crystal input one (X1) characteristics). Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82551QM may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708- 296-9333 Intel ® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Copyright © 2008, Intel Corporation. * Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit, without intent to infringe.

82551QM — Networking Silicon iv Datasheet

Networking Silicon — 82551QM

82551QM — Networking Silicon vi Datasheet

11.3.8 Register 23: 100B ASE-TX Receive Premature End of Frame Error Coun-

Networking Silicon — 82551QM Datasheet 1

1.0 Introduction

This datasheet is applicable to the Intel® 82551QM Fast Ethernet Multifunction PCI/CardBus Controller, a member of the 8255x Fast Ethernet Controller family.

1.1 Overview

The 82551QM is an evolutionary addition to Intel’s family of 8255x controllers. It provides excellent performance by offloading TCP, UDP and IP checksums and supports TCP segmentation off-load for operations such as Large Send. Its optimized 32-bit interface and efficient scatter-gather bus mastering capabilities enable the 82551QM to perform high speed data transfers over the PCI bus or CardBus. This capability accelerates the processing of high level commands and operations, which lowers CPU utilization. Its architecture enables data to flow efficiently from the bus interface unit to the 3 KB Transmit and Receive FIFOs, providing the perfect balance between the wire and system bus. In addition, multiple priority queues are provided to prevent data underruns and overruns. The 82551QM also integrates advanced manageability features into one component. It includes support for the Alerting Standards Forum (ASF) alert standard format bi-directional alerting and provides a Total Cost of Ownership (TCO) interface that can be used with bus management controllers. ASF sensor polling is supported, as well as remote control capabilities. The 82551QM embeds UNDI (Universal NIC Driver Interface) code, allowing it to support Preboot eXecutable Environment (PXE) without the use of additional external ROM. The 82551QM includes both a MAC and PHY . In also has a simple interface to the analog front end, which allows cost effective designs requiring minimal board real estate. The 82551QM is pin compatible with the 82550 and 82559 family of controllers and is offered with software that provides backwards compatibility with previous 8255x controllers.

1.2 Byte Ordering

TCP and IP Internet Engineering Task Force (IETF) Request for Comments (RFCs) and literature use big endian (BE) byte ordering. This document uses big endian ordering for all IP and TCP frame formats. However, little endian byte ordering is used for referencing 82551QM memory resident structures and internal structures.

1.3 References

The following documents may provide further information on topics discussed in this document.

• 10/100 Mbit Ethernet Controller Family Software Developer’s Manual. Intel Corporation.
• Advanced Configuration and Power Interface Specification, Revision 1.0. Intel Corporation, Microsoft Corporation, and Toshiba.
• IEEE 802.3x and 802.1y Standards.

2 Datasheet

• Network Device Class Power Management Reference Specification, Revision 1.0a. AMD, Inc. and Microsoft Corporation.
• System Management Bus (SMB) Specification. Smart Battery System Special Interest Group (SIG).
• 82551QM/ER/IT EEPROM Map and Programming Information. Intel Corporation
• 82562EZ(EX)/82551QM & 82540EM Combined Footprint LOM Design Guide. Intel Corporation

1.4 Product Ordering Codes

• GD82551QM (Leaded)
• LU82551QM (Lead Free)

Figure 1. 82551QM Component Markings

Networking Silicon — 82551QM Datasheet 3

2.0 Architectural Overview

The Intel® 82551QM is divided into five main subsystems: a parallel subsystem, a FIFO subsystem, the manageability subsystem, a 10/100 Mbps Carrier Sense Multiple Access with Collision Detect (CSMA/CD) unit, and a 10/100 Mbps physical layer (PHY) unit.

2.1 Parallel Subsystem Overview

The parallel subsystem is comprised of several functional blocks: a PCI bus master interface, a micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/ Flash/EEPROM/Modem interface. The parallel subsystem also interfaces to the FIFO subsystem, passing data (such as transmit, receive, and configuration data) and command and status parameters between these two blocks. The dual function modem and PCI bus master interface provides a complete glueless interface to a PCI bus and is compliant with the PCI Bus Specification, Revision 2.2. The 82551QM provides 32 bits of addressing and data, as well as the PCI control interface. As a PCI target, it conforms to the PCI configuration scheme, which allows all accesses to the 82551QM to be automatically mapped into free memory and I/O space upon initialization of a PCI system. When transmit and receive data is processed, the 82551QM operates as a master on the PCI bus, initiating zero wait state transfers. The 82551QM Control/Status Register Block is part of the PCI target element. The Control/Status Register block consists of the following 82551QM internal control registers: System Control Block (SCB), PORT, Flash Control, EEPROM Control, Modem Control and Management Data Interface (MDI) Control. An embedded micromachine consisting of independent transmit and receive processing units allow the 82551QM to execute commands and receive incoming frames with no real time CPU intervention. The 82551QM contains a multiplexed interface to connect an external serial EEPROM and Flash memory and modem. The Flash interface, which can also be used to connect to any standard 8-bit device, provides up to 128 KB of addressing to the Flash. Both read and write accesses are supported. The Flash can be used for remote boot functions, network statistical and diagnostics functions, and management functions. The Flash is mapped into host system memory (anywhere within the 32-bit memory address space) for software accesses. It is also mapped into an available boot expansion ROM location during boot time of the system. More information on the Flash interface is detailed in Section 5.6, “Parallel Flash/Modem Interface”. The serial EEPROM is used to store relevant information for a LAN connection such as node address, as well as board manufacturing and configuration information. Both read and write accesses to the EEPROM are supported by the 82551QM. Information on the EEPROM interface is detailed in Section 5.7, “Serial EEPROM Interface”. The modem interface uses an ISA-like signal and is described in more detail in Section 7.0, “Modem Functionality”.

82551QM — Networking Silicon

4 Datasheet

2.2 FIFO Subsystem Overview

The 82551QM FIFO subsystem consists of independent 3 KB transmit and receive FIFOs. Each FIFO provides a temporary buffer for frames as they are transmitted or received. Transmit frames queued within the transmit FIFO allow back-to-back transmission within the minimum Interframe Spacing (IFS). The FIFOs allow the 82551QM to withstand long PCI bus latencies without losing incoming data. Additional attributes of the FIFOs that enhance performance and functionality are:

• Tunable transmit FIFO threshold allows elimination of underruns while concurrent transmits are being performed.
• Extended PCI zero wait state burst accesses to and from the 82551QM for both transmit and receive FIFOs
• Efficient re-transmission of data directly from the transmit FIFO when physical or data link errors (collision detection or data underrun) are encountered, increasing performance by eliminating the need to re-access the data from host memory
• Automatic discard of incoming runt receive frames

2.3 Manageability Subsystem Overview

The 82551QM’s Manageability subsystem supports bi-directional ASF, version 1.0. In addition, it provides a Total Cost of Ownership (TCO) interface that enables connection with alerting and management controllers such as the Intelligent Platform Management Interface (IPMI) solutions and Baseboard Management Controllers (BMCs). 2.4 10/100 Mbps Serial CSMA/CD Unit Overview The 82551QM’s CSMA/CD unit allows it to be connected to a 10 or 100 Mbps Ethernet network at half or full duplex. The CSMA/CD unit performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, collision handling, deferral to link traffic, etc. 2.5 10/100 Mbps Physical Layer Unit The integrated Physical Layer (PHY) unit of the 82551QM allows connection to either a 10 or 100 Mbps Ethernet network. The PHY supports Auto-Negotiation for 100BASE-TX Full Duplex, 100BASE-TX Half Duplex, 10BASE-T Full Duplex, and 10BASE-T Half Duplex. Three LED pins indicate link status, network activity, and speed.

Networking Silicon — 82551QM Datasheet 5

3.0 Performance Enhancements

All of Intel’s Fast Ethernet controllers have the ability to support full wire speeds. The 82551QM has been designed to provide improved networking throughput. Performance is limited to the system’s ability to feed data to the network controller. As networks grow, the task of servicing the network becomes a large burden on the platform. System bottlenecks prevent optimal performance in typical operating conditions. Thus, to help alleviate these issues, Network Operating System (NOS) vendors are establishing normalized off- load specifications. These specifications define the types of off-load support required by the OS and interface between the network drivers. The 82551QM provides support for these initiatives and enables an improvement in platform network efficiency. With the pervasiveness of Internet Protocols, the off-load capabilities have focused on improving IP efficiency. As part of this effort, the 82551QM includes support for Multiple Priority Transmit Queues.

3.1 Multiple Priority Transmit Queues

The 82551QM supports two queues: High Priority Queue (HPQ) and Low Priority Queue (LPQ). The 82551QM provides a method for the driver to modify the HPQ while processing data. A new read only register is defined in the Control/Status Register (CSR) that enables the driver to change the transmit priority of elements within the HPQ. When software reads this register, the address of the next Command Block to be processed by the 82551QM on the HPQ is returned. After reading this register, software can freely modify the next Command Block (for example, overwrite it with a different Command Block) and any subsequent Command Block, without any conflict with the 82551QM. Note: The 82551QM Windows* driver supports the Command Block Pointer register (in the CSR).

3.2 Early Release

Like the 82558, 82559 and 82550, the 82551QM supports a 3 KB transmit FIFO. The 82551QM provides a transmit FIFO enhancement called “early release” that effectively increases the amount of free capacity in the transmit FIFO. The enabling of early release is controlled through configuration space and occurs when the following conditions are met: 1. The transmitted frame is the olde st one in the queue (in other words, it is located at the head of the queue). 2. The transmitted frame has been completely tr ansferred to the XMT-SRAM and processed (for example, XSUM). Large frames (greater than 3 KB) are never candidates for an early release. 3. When the preemptive queue mechanism is on, a frame which satisfies condition 2 may not satisfy condition 1 and therefore will not benefit from an early release. 4. More than 128 bytes have al ready been transferred to the XMT-SYNC-FIFO. This condition guarantees that at least one slot time elapsed (collision window).

6 Datasheet

3.3 Hardware Integrity Support

opens, shorts, and degraded cable quality can be located along the wire.

3.4 Management Data Inter face MDI/MDI-X Feature

connected to the 82551QM without any additional external logic. to the start of the hardware auto negotiation algorithm. Table 1 lists the connections for both straight-through and cross-over RJ-45 ports for comparison. Table 1. RJ-45 Connections a. Straight-through connections used on DTE applications. b. Cross-over connecti ons used on Hub and Switch applications.

1 TD+ RD+

2 TD- RD-

4 Not Used Not Used

5 Not Used Not Used

7 Not Used Not Used

8 Not Used Not Used

4.0 Signal Descriptions

4.1 Signal Type Definitions

Table 2. Signal Type Descriptions IN Input The input pin is a standard input only signal. TS Tri-State The tri-state pin is a bidirectional, input/output pin. clock cycle after it has been tri-stated by the previous owner. AI Analog Input The analog input pin is used for analog input signals. AO Analog Output The analog output pi n is used for analog output signals. B Bias The bias pin is an input bias. Supply Digital power or ground for the device. Supply Analog power or ground for the device.

8 Datasheet

4.2 PCI Bus and CardBus Interface Signals

4.2.1 Address and Data Signals

4.2.2 Interface Control Signals

Table 3. Address and Data Signals and data lines contain data. phases; and the target, for read data phases. Table 4. Interface Control Signals stop the current transaction.

4.2.3 System and Power Management Signals

systems. In a CardBus system, this pin should not be connected. every bus master has its own REQ#. to-point signal and every master has its own GNT#. the 82551QM. This is an active low, level-triggered interrupt signal. Table 5. System and Power Management Signals using the Clock Run protocol. connected to an external pull-down resistor.

10 Datasheet

4.3 Local Memory Interface Signals

unnecessarily connected to a pull-up or pull-down resistor. approximately 52 ms upon detection of an incoming Magic Packet*. ISOLATE# pin should be driven by the PCI Reset signal. high to the main digital power supply. should be connected to the main digital power supply. Table 6. Local Memory Interface Signals left floating if the Flash and the CLK25 functionality are not used.

should be left floating if Flash and modem functionality are not used. left floating if Flash and modem functionality are not used. enabled, it acts as the Modem Reset signal with an active high output. this pin should be left floating. the modem is enabled, these pins carry modem address bits 6:2. pin should be left floating. modem, this pin should be left floating. assert chip select to the serial EEPROM.

12 Datasheet

4.4 System Management Bus (SMB) Interface Signals

modem functionality are not used. floating if Flash and modem functionality are not used. and modem functionality are not used. Table 7. System Management Bus (SMB) Interface Signals Alert Bus Data. This signal is stable when the Alert Bus Clock signal is high. This open drain signal should be pulled high to VCC in all cases.

4.5 Test Port Signals

Note: These test port signals are not JTAG compatible. As a result, a BSDL file is not required.

4.6 PHY Signals

Table 8. Test Port Signals Test Port. If this input pin is high, the 82551QM enables the test port. TCK IN Test Port Clock. This pin is used for the Test Port Clock signal. Table 9. PHY Signals semiconductor (MOS) level 25 MHz oscillator when X2 is left floating. 25 MHz oscillator when X2 is left floating. signals depending on the mode of operation. active low); when no activity is present, the activity LED is off. the received frame passed MAC address filtering. Link Integrity LED. The Link Integrity LED pin indicates link integrity. active low); if link is invalid, the LED is off. will be on at 100 Mbps (SPDLED# active low) and off at 10 Mbps.

14 Datasheet

4.7 Power and Ground Signals

print LOM Design Guide for more information. Table 10. Power and Ground Signals VCCR APS Analog Power. These pins should be connected directly to VCC. up or pull-down resistors should not be used.

5.0 Media Access Control Functional Description

5.1 Device Initialization

1. Internal Power-on Reset (POR)
2. Software Reset (Software Command)
3. Selective Reset (Software Command)

5.1.1 Initialization Effects

ALTRST# and RST# but not necessarily by the selective reset. Table 11. Initialization Effects

16 Datasheet

5.1.2 Initialization Effe cts on TCO Functionality

5.2 PCI and CardBus Interface

5.2.1 Bus Operations

82551QM, as a bus master device, will initiate memory cycles by way of the PCI bus. Table 12. Initialization Effects on TCO 82551QM on the trailing edge. b. SMB commands in process will be terminated immediately.

Networking Silicon — 82551QM Datasheet 17 To perform these actions, the 82551QM is controlled and examined by the CPU through its control and status structures and registers. Some of these structures reside in the 82551QM and some reside in system memory. For access to the 82551QM’s Control/Status Registers (CSR), the 82551QM acts as a slave device. The 82551QM serves as a slave also while the CPU accesses its 128 KB Flash buffer or its EEPROM. When the 82551QM is in modem mode, it also acts as a slave. Details regarding modem interface are described in Section 5.6, “Parallel Flash/Modem Interface”. Section 5.2.1.1 describes the 82551QM slave operation. It is followed by a description of the 82551QM operation as a bus master (initiator) in Section 5.2.1.2.

5.2.1.1 Bus Slave Operation

The 82551QM serves as a target device in the following cases:

• CPU accesses to the 82551QM System Control Block (SCB) Control/Status Registers (CSR)
• CPU accesses to the EEPROM through its CSR
• CPU accesses to the 82551QM PORT address through the CSR
• CPU accesses to the MDI control register in the CSR
• CPU accesses to the Flash control register in the CSR
• CPU accesses to the 128 KB Flash The CSR and the 1 MB Flash buffer are considered by the 82551QM as totally separated memory spaces. The 82551QM provides separate Base Address Registers (BARs) in the configuration space to distinguish between them. The size of the CSR memory space is 4 KB in the memory space and 64 bytes in the I/O space. The 82551QM treats accesses to these memory spaces differently.

5.2.1.1.1 Control/Status Register (CSR) Accesses

The 82551QM supports zero wait state single cycle memory or I/O mapped accesses to its CSR space. Separate BARs request 4 KB of memory space and 64 bytes of I/O space to accomplish these accesses. The 82551QM provides 4 valid KB of CSR space, which include the following elements:

• System Control Block (SCB) registers
• PORT register
• Flash control register
• EEPROM control register
• MDI control register
• Flow control registers
• CardBus registers The following figures show CSR zero wait state I/O read and write cycles. In the case of accessing the Control/Status Registers, the CPU is the initiator and the 82551QM is the target of the transaction.

18 Datasheet

Figure 2. CSR I/O Read Cycle Figure 3. CSR I/O Write Cycle

the STOP# signal. This is true for both memory mapped and I/O mapped accesses.

5.2.1.1.2 Flash Buffer Accesses

longest burst cycle to the Flash buffer contains one data access only. the Flash buffer. When TRDY# is asserted, the 82551QM drives valid data on the AD[31:0] lines. accesses can be byte or word length. Figure 4. Flash Buffer Read Cycle

20 Datasheet

signal and de-asserts it for a certain number of clocks until valid data is written to the Flash buffer. By asserting TRDY#, the 82551QM signals the CPU that the current data access has completed. Flash buffer write accesses can be byte length only. Figure 5. Flash Buffer Write Cycle

5.2.1.1.3 Retry Premature Accesses

honored. Figure 6 below depicts how a Retry looks when it occurs. Note: The 82551QM is considered the target in the above diagram; thus, TRDY# is not asserted.

• Card Information Structure (CIS) in memory is accessed in CardBus mode.
• External modem registers are accessed and the modem does not assert IOCHRDY within 7 PCI clocks from the assertion of MDMCS#.

5.2.1.1.4 Error Handling

• After accesses to the Flash buffer
• After accesses to its CSR
• After accesses to the configuration space

Figure 6. PCI Retry Cycle

22 Datasheet

System Error: The 82551QM reports parity error during the address phase using the SERR# pin. Parity Error bit and asserts SERR# for one clock. is involved in the current transaction.

5.2.1.2 Bus Master Operation

Figure 7. Memory Read Burst Cycle

82551QM may use either the Memory Write or Memory Write and Invalidate (MWI) commands. completed after an 82551QM internal arbitration. read by asserting the TRDY# signal. completed before the 82551QM internal arbitration. of a data phase by de-assertion and assertion of TRDY#. Figure 8. Memory Write Burst Cycle

82551QM — Networking Silicon

24 Datasheet

5.2.1.2.1 Memory Write and Invalidate

The 82551QM has four Direct Memory Access (DMA) channels. Of these four channels, the Receive DMA is used to deposit the large number of data bytes received from the link into system memory. The Receive DMA uses both the Memory Write (MW) and the Memory Write and Invalidate (MWI) commands. To use MWI, the 82551QM must guarantee the following: 1. Minimum transfer of one cache line 2. Active byte enable bits (or BE[3 :0]# are all low) during MWI access 3. The 82551QM may cross the cache line boundary only if it intends to transfer the next cache line too. To ensure the above conditions, the 82551QM may use the MWI command only if the following conditions are true: 1. The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16 Dwords. 2. The accessed address is cache line aligned. 3. The 82551QM has at least 8 or 16 Dwo rds of data in its receive FIFO. 4. There are at least 8 or 16 Dwords of data space left in the system memory buffer. 5. The MWI Enable bit in the PCI Configuration Command register, bit 4, must be set to 1b. 6. The MWI Enable bit in the 82551QM Configure command must be set to 1b. If any one of the above conditions is not true, the 82551QM uses the MW command. If an MWI cycle has started and one of the conditions is no longer valid (for example, the data space in the memory buffer is now less than CLS), then the 82551QM terminates the MWI cycle at the end of the cache line. The next cycle is either an MW or MWI cycle depending on the conditions listed above. If the 82551QM started a MW cycle and reached a cache line boundary, it either continues or terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the 82551QM Configure command (byte 3, bit 3). If this bit is set, the 82551QM terminates the MW cycle and attempts to start a new cycle. The new cycle is an MWI cycle if this bit is set and all of the above conditions are met. If the bit is not set, the 82551QM continues the MW cycle across the cache line boundary if required.

5.2.1.2.2 Read Align

The Read Align feature enhances the 82551QM’s performance in cache line oriented systems. In these particular systems, starting a PCI transaction on a non-cache line aligned address may cause low performance. To resolve this performance anomaly, the 82551QM attempts to terminate transmit DMA cycles on a cache line boundary and start the next transaction on a cache line aligned address. This feature is enabled when the Read Align Enable bit is set in the 82551QM Configure command (byte 3, bit 2). If this bit is set, the 82551QM operates as follows:

• When the 82551QM is almost out of resources on the transmit DMA (that is, the transmit FIFO is almost full), it attempts to terminate the read transaction on the nearest cache line boundary.

Networking Silicon — 82551QM Datasheet 25

• When the arbitration counter’s feature is enabled (in other words, the Transmit DMA Maximum Byte Count value is set in the Configure command), the 82551QM switches to other pending DMAs on cache line boundary only. This feature is not recommended for use in non-cache line oriented systems since it may cause shorter bursts and lower performance. If this feature is used, it is recommended that the CLS register in PCI Configuration space is set to 8 or 16.

5.2.1.2.3 Error Handling

Data Parity Errors: As an initiator, the 82551QM checks and detects data parity errors that occur during a transaction. If the Parity Error Response bit is set (PCI Configuration Command register, bit 6), the 82551QM also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration Status register, bit 8). In addition, if the error was detected by the 82551QM during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).

5.2.2 Clock Run Signal

The CLK_RUN# signal is used to control the PCI clock as defined in the CardBus specification and PCI Mobile design guide and is compliant with both the CardBus specification and PCI Mobile design guide. This signal is active in both the CardBus and PCI bus operating modes. The Clock Run signal is an open drain I/O signal. It is used as a bidirectional channel between the host and the devices.

• The host de-asserts the CLK_RUN# signal to indicate that the clock is about to be stopped or slowed down to a non-operational frequency.
• The host asserts the CLK_RUN# signal when the clock is either running at a normal operating frequency or about to be started.
• The 82551QM asserts the CLK_RUN# signal to indicate that the PCI clock must prevent the host from stopping or to request that the host restore the clock if it was previously stopped. Proper operation requires that the system latency from the nominal PCI CLK to CLK_RUN# assertion should be less than 0.5 µs. If the system latency is longer than 0.5 µs, there is an increase in receive overruns. In these types of systems, the Clock Run functionality should be disabled. In this case, the 82551QM claims the PCI clock even during idle time. If the CLK_RUN# signal is not used, it must be connected to a pull-down resistor.

5.2.3 Power Management Event an d Card Status Change Signals

The 82551QM supports power management indications in the PCI and CardBus mode. In CardBus systems, the CSTSCHG pin is used for power management event indication. The PME# output pin provides an indication of a power management event in PCI systems. The CSTSCHG pin is supported by four registers located in the Control/Status Register (Section 10.0, “Control/Status Registers” describes these registers in more detail).

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5.3 PCI Power Management

The 82551QM supports a larger set of wake-up packets and the capability to wake the system on a link status change from a low power state. These added power management enhancements enable the 82551QM to adhere to emerging standards. The 82551QM enables the host system to be in a sleep state and remain virtually connected to the network. After a power management event or link status change is detected, the 82551QM wakes the host system. The sections below describe these events, the 82551QM power states, and estimated power consumption at each power state.

5.3.1 Power States

The 82551QM contains two sets of power management registers, one for PCI and one for CardBus, The has one set of PCI power management registers and implements all four power states as defined in the Power Management Network Device Class Reference Specification, Revision 1.0. The four device power states, D0 through D3, vary from maximum power consumption at D0 to the minimum power consumption at D3. PCI transactions are only allowed in the D0 state, except for host accesses to the 82551QM’s PCI configuration registers. The D1 and D2 power management states enable intermediate power savings while providing the system wake-up capabilities. In the D3 cold state, the 82551QM can provide wake-up capabilities only if auxiliary power is supplied. Wake-up indications from the 82551QM are provided by the Power Management Event (PME#) signal in PCI implementations and the Card Status Change (CSTSCHG) signal in CardBus designs. In addition to providing a host interface through the PCI bus, the 82551QM provides TCO controller access through a dedicated System Management Bus (SMB). Additional information on the supported TCO functionality at all power states is described in Section 8.0, “Manageability Functionality”.

5.3.1.1 D0 Power State

As defined in the Network Device Class Reference Specification, the device is fully functional in the D0 power state. In this state, the 82551QM receives full power and should be providing full functionality. In the 82551QM the D0 state is partitioned into two substates, D0 Uninitialized (D0u) and D0 Active (D0a). D0u is the 82551QM’s initial power state following a Power-on Reset (POR) event and before the Base Address Registers (BARs) are accessed. While in the D0u state, the 82551QM has PCI slave functionality to support its initialization by the host and supports Wake on LAN mode. Initialization of the CSR, Memory, or I/O Base Address Registers in the PCI Configuration space switches the 82551QM from the D0u state to the D0a state. In the D0a state, the 82551QM provides its full functionality and consumes nominal power. In addition, the 82551QM supports wake on link status change (Section 5.3.2, “Wake-up Events”). While it is active, the 82551QM requires a nominal PCI clock signal (in other words, a clock frequency greater than 16 MHz) for proper operation. During idle time, the 82551QM supports a PCI clock signal suspension using the Clock Run signal mechanism. The 82551QM supports a dynamic standby mode. In this mode, the 82551QM is able to save almost as much power as it does in the static power-down states. The transition to or from standby is done dynamically by the 82551QM and is transparent to the software.

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5.3.1.2 D1 Power State

For a device to meet the D1 power state requirements, as specified in the Advanced Configuration and Power Interface (ACPI) Specification, Revision 1.0, it must not allow bus transmission or interrupts; however, bus reception is allowed. Therefore, device context may be lost and the 82551QM does not initiate any PCI activity. In this state, the 82551QM responds only to PCI accesses to its configuration space and system wake-up events. The 82551QM retains link integrity and monitors the link for any wake-up events such as wake-up packets or link status change. Following a wake-up event, the 82551QM asserts the PME# signal to alert the PCI system or the CSTSCHG signal for a CardBus system.

5.3.1.3 D2 Power State

The ACPI D2 power state is similar in functionality to the D1 power state. If the bus is in the B2 bus power state, the 82551QM will consume less current than it does in the D1 state. In addition to D1 functionality, the 82551QM can provide a lower power mode with wake-on-link status change capability. The 82551QM may enter this mode if the link is down while the 82551QM is in the D2 state. In this state, the 82551QM monitors the link for a transition from an invalid link to a valid link. The 82551QM will not attempt to keep the link alive by transmitting idle symbols or link integrity pulses.

1 The sub-10 mA state due to an invalid link can be enabled or disabled by a

configuration bit in the Power Management Driver Register (PMDR).

5.3.1.4 D3 Power State

In the D3 power state, the 82551QM has the same capabilities and consumes the same amount of power as it does in the D2 state. However, it enables the PCI system to be in the Bus Power 3 (B3) state. If the PCI system is in the B3 state (in other words, no PCI power is present), the 82551QM provides wake-up capabilities if it is connected to an auxiliary power source in the system. If PME is disabled, the 82551QM does not provide wake-up capability or maintain link integrity. In this mode, the 82551QM consumes minimal power. The 82551QM enables a system to be in a sub-5 watt state (low power state) and still be virtually connected. More specifically, the 82551QM supports full wake-up capabilities while it is in the D3 cold state. The 82551QM can be connected to an auxiliary power source (VAUX), which enables it to provide wake-up functionality while the PCI power is off. The typical current consumption of the 82551QM is 125 mA at 3.3 V and a dual power plane is not required. If connected to an auxiliary power source, the 82551QM receives all of its power from the auxiliary source in all power states. When connected to an auxiliary power supply, the 82551QM must have a status indicator of whether the power supply is valid (in other words, auxiliary power is stable). The indication is received at the AUXPWR pin, as described next. 1. For a topology of two 82551QM devices connected by a crossed tw isted-pair Ethernet cable, the deep power-down mode should be disabled. If it is enabled, the two devices may not detect each other if the operating system places them into a low power state before both nodes become active.

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5.3.1.4.1 Auxiliary Power Signal

The 82551QM senses whether it is connected to the PCI power supply or to an auxiliary power supply (VAUX) through the FLA1/AUXPWR pin. The auxiliary power detection pin (multiplexed with FLA1) is sampled when the 82551QM power-on reset is active. An external pull-up resistor should be connected to the 82551QM if it is fed by VAUX; otherwise, the FLA1/AUXPWR pin should be left floating. The presence of AUXPWR affects the value reported in the Power Management Capability Register (PCI Configuration Space, offset DEh). The Power Management Capability Register is described in more detail in Section 9.1.20, “Power Management Capabilities Register”.

5.3.1.4.2 Alternate Reset Signal

The 82551QM’s ALTRST# input pin functions as a power-on reset input. Following ALTRST# being driven low, the 82551QM is initialized to a known state. While this function is required, this pin is not needed for it. Since this functionality is provided by the 82551QM’s internal power-on reset signal, this pin should be pulled high to the main digital power supply. Note: A separate internal power-on reset signal is generated when power is applied to the device. This signal is active while it provides the 82551QM power-on reset function and is also used for sampling configuration inputs.

5.3.1.4.3 Isolate Signal

When the 82551QM is connected to VAUX, it can be powered on while the PCI bus is powered off. In this case, the 82551QM isolates itself from the PCI bus. The 82551QM has a dedicated ISOLATE# pin that must be connected to the PCI Reset signal. Whenever the PCI Bus is in the B3 state, the PCI Reset signal becomes active and the 82551QM isolates itself from the PCI bus. During this state, the 82551QM ignores all PCI signals including the RST# and CLK input signals. It also tristates all PCI outputs, except the PME# signal. In the transition to an active PCI power state (in other words, from B3 bus power state to B0 bus power state), the PCI Reset signal shifts high. This generates an internal hardware reset, which initializes the device (described in Section 5.1.1, “Initialization Effects”). Some designs in existence may implement the previous recommendations for the RST#, ISOLATE# and ALTRST# input pins. In these cases, the PCI Reset signal is connected to the RST# pin, the PCI power source’s stable power (power good) to the ISOLATE# pin, and the auxiliary power source’s stable power (auxiliary power good) to the ALTRST# pin. It is not necessary for existing working designs to make changes for these signals; however, it is recommended that the changes contained in this document should be included when possible. New designs should implement the recommendations contained in this document.

5.3.1.4.4 Reset Signal

The RST# signal can be activated in one of the following cases:

• Power-up
• Warm boot
• Wake-up (B3 to B0 transition)
• Set to power-down (B0 to B3 transition)

management registers, and the wake-up packet would not be affected).

• Active RST# signal while the 82551QM is the D0, D1, or D2 power state
• RST# trailing edge while the 82551QM is in the D3 power state
• ISOLATE# trailing edge The internal initialization signal resets the PCI Configuration Space, MAC configuration, and memory structure. The behavior of the RST# and ISOLATE# pins and the internal 82551QM initialization signal are shown in the following figure.

Figure 9. Initialization upon RST# and ISOLATE#

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The following tables list the functionality at the different power states for the 82551QM.

5.3.2 Wake-up Events

Control/Status Register (PMCSR)”.

• Address Resolution Protocol (ARP) Packets (with Multiple IP addresses)
• Direct Packets (with or without type qualification)
• Magic Packet*
• Neighbor Discovery Multicast Address Packet (“ARP” in IPv6 environment)
• NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)
• Internetwork Package Exchange* (IPX*) Diagnostic Packet
• TCO Packet

Table 13. Functionality at the Different Power States

• PCI slave access D0a Valid Full functionality at full power and wake on an invalid link Invalid Full functionality at full power and wake on a valid link Valid
• Wake-up on “interesting” packets and link invalid
• PCI configuration access Invalid • Wake on link valid
• PCI configuration access Valid Same functionality as D1 (link valid) Invalid Detection for valid link and no link integrity D3 (with power) Valid Same functionality as D1 (link valid) Invalid Detection for valid link and no link integrity Dx (x>0 without PME#) Don’t care No wake-up functionality Note: If the TCO bit is set in the EEPROM, the 82551QM will not disable the link function and will consume power as in the D2 state.

Networking Silicon — 82551QM Datasheet 31 This allows the 82551QM to handle various packet types. In general, the 82551QM supports programmable filtering of any packet in the first 128 bytes. When the 82551QM is in one of the low power states, it searches for a predefined pattern in the first 128 bytes of the incoming packets. The only exception is the Magic Packet, which is scanned for the entire frame. The 82551QM classifies the incoming packets into one of the following categories:

• No Match. The 82551QM discards the packet and continues to process the incoming packets.
• TCO Packet. The 82551QM implements perfect filtering of TCO packets. After a TCO packet is processed, the 82551QM is ready for the next incoming packet. There are two possible system environments: — TCO controller on the SMB. The entire TCO packet is transferred to the TCO controller. — System without TCO controller. TCO packets are treated as any other wake-up packets and may assert the PME# signal if configured to do so.
• Wake-up Packet. The 82551QM is capable of recognizing and storing the first 128 bytes of a wake-up packet. If a wake-up packet is larger than 128 bytes, its tail is discarded by the 82551QM. After the system is fully powered-up, software has the ability to determine the cause of the wake-up event through the PMDR and dump the stored data to the host memory. Magic Packets are an exception. The Magic Packets may cause a power management event and set an indication bit in the PMDR; however, it is not stored by the 82551QM for use by the system when it wakes up.

5.3.2.2 Link Status Change Event

The 82551QM link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The 82551QM reports a PME link status event in all power states. The PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command.

5.4 CardBus Power Management

The CardBus Power Management Proposal differs from the PCI Power Management Specification in the following manner:

• The PME# signal is replaced by CSTSCHG which is an active high output signal.
• An auxiliary power source, VAUX, is supplied on the same Vcc pins.
• An auxiliary power source bit in the PMC register must be set.
• The PCI clock signal and the PCI reset signal are guaranteed to be kept low in the B3 state. In addition, the 82551QM also meets the CardBus requirement for current consumption less than 70 mA in the D0u state.

5.5 Wake on LAN (Preboot Wake-up)

When the 82551QM is drawing power from an auxiliary power source (VAUX), it can support the same preboot Wake on LAN (WOL) capabilities as the 82559 device. The 82551QM enters WOL mode after the following events occur:

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• An ALTRST# is completed.
• The 82551QM reads the EEPROM and the WOL bit is set. When the 82551QM is in WOL mode:
• The 82551QM scans incoming packets for a Magic Packet. When it receives a Magic Packet, the 82551QM asserts the PME# signal (until cleared) and the CSTSCHG signal for 52 ms.
• The Activity LED changes its functionality to indicate that the received frame passed Individual Address (IA) filtering or broadcast filtering.
• The PCI Configuration registers are accessible to the host.
• Software must not attempt to access the Flash. The 82551QM switches from WOL mode to the D0a power state following a setup of the Memory or I/O Base Address Registers in the PCI Configuration space. If the 82551QM receives a Magic Packet while the it is in the D0u, D1, D2, or D3 power state, it issues a positive pulse on the CSTSCHG pin. This pulse is cleared by a later non-Wake on LAN message. For PCI systems and in designs that support the 3-pin header standard, the CSTSCHG pin acts as the WOL signal.

5.6 Parallel Flash/Modem Interface

The 82551QM’s parallel interface is used for Flash interface only or modem interface only. The 82551QM supports a glueless interface to an 8-bit wide, 128 KB, parallel memory device. The parallel local port is multiplexed with a modem interface in a LAN/modem combination card. The Flash (or boot PROM) is read from or written to whenever the host CPU performs a read or a write operation to a memory location that is within the Flash mapping window. All accesses to the Flash, except read accesses, require the appropriate command sequence for the device used. (Refer to the specific Flash data sheet for more details on reading from or writing to the Flash device.) The accesses to the Flash are based on a direct decode of CPU accesses to a memory window defined in either the 82551QM Flash Base Address Register (PCI Configuration space at offset 18h) or the Expansion ROM Base Address Register (PCI Configuration space at offset 30h). The 82551QM asserts control to the Flash when it decodes a valid access. The 82551QM supports an external Flash memory (or boot PROM) of up to 128 KB. The Expansion ROM address can be separately disabled by setting the corresponding bit in the EEPROM, word Ah.

and one byte only for a write operation. Note: In mobile applications, the MDMCS# pin enables the modem controller or Flash device.

5.7 Serial EEPROM Interface

The serial EEPROM stores configuration data for the 82551QM and is a serial in/serial out device. system to hold the heartbeat packet. The EEPROM should operate at a frequency of at least 1 MHz. will respond with a PCI Retry to both EEPROM and Flash accesses. Map and Programming Information for more details. Figure 10. 64-Word EEPROM Read Instruction Waveform

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The 82551QM EEPROM format is shown below in Table 14. Table 14. EEPROM Address Map

Note: Refer to the 82551QM/ER/IT EEPROM Map and Programming Information for more details. serial clocks run at either 25 or 2.5 MHz.

5.8.1 Full Duplex

When operating in full duplex mode the 82551QM can transmit and receive frames simultaneously. internal PHY detects a valid frame on the receive differential pair of the PHY . other words, the Configure command in software). Table 14. EEPROM Addr ess Map (Continued)

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5.8.2 Flow Control

The 82551QM supports IEEE 802.3x frame-based flow control frames in both full duplex and half duplex switched environments. The 82551QM flow control feature is not intended to be used in shared media environments. The PHY unit’s duplex and flow control enable can be selected using the NWay* Auto-Negotiation algorithm or through the Management Data Interface.

5.8.3 Address Filtering Modifications

The 82551QM can be configured to ignore one bit when checking for its Individual Address (IA) on incoming receive frames. The address bit, known as the Upper/Lower (U/L) bit, is the second least significant bit of the first byte of the IA. This bit may be used, in some cases, as a priority indication bit. When configured to do so, the 82551QM passes any frame that matches all other 47 address bits of its IA, regardless of the U/L bit value. This configuration only affects the 82551QM specific IA and not multicast, multi-IA or broadcast address filtering. The 82551QM does not attribute any priority to frames with this bit set, it simply passes them to memory regardless of this bit.

5.8.4 VLAN Support

The 82551QM supports the VLAN standard as currently defined by the IEEE 802.1 committee. All VLAN flows will be implemented by software. The 82551QM supports the reception of long frames, specifically frames longer than 1518 bytes, including the CRC, if software sets the Long Receive OK bit in the Configuration command. Otherwise, “long” frames are discarded.

5.9 Media Independent Interface (MII) Management Interface

The MII management interface allows the CPU to control the PHY unit through a control register in the 82551QM. This allows the software driver to place the PHY in specific modes such as full duplex, loopback, power down, etc., without the need for specific hardware pins to select the desired mode. This structure allows the 82551QM to query the PHY unit for status of the link. This register is the MDI Control Register and resides at offset 10h in the 82551QM CSR. (The MDI registers are described in detail in Section 11.0, “PHY Unit Registers”.) The CPU writes commands to this register and the 82551QM reads or writes the control/status parameters to the PHY unit through the MDI register. Although the 82551QM follows the MII format, the MI bus is not accessible on external pins.

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6.0 Physical Layer Functional Description

6.1 100BASE-TX PHY Unit 6.1.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal or a 25 MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY unit derives its internal transmit digital clocks from this crystal or oscillator input. The internal Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external crystal or oscillator must be ± 0.005% (30 ppm). 6.1.2 100BASE-TX Transmit Blocks The transmit subsection of the PHY unit accepts nibble-wide data from the CSMA/CD unit. The transmit subsection passes data unconditionally to a 4B/5B encoder. The 4B/5B encoder accepts nibble-wide data (4 bits) from the CSMA unit and compiles it into 5- bit-wide parallel symbols according to the IEEE 802.3u 100BASE_TX standard. Next, the symbols are scrambled to reduce electromagnetic emissions during long sequences of high-frequency data codes. The MLT-3 (multi-level signal) encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT- 3 is similar to NRZ1 coding, but three levels are output instead of two. The three output levels are positive, negative and zero. The transmit differential pair line drivers are implemented with digital slope controlled current buffers that meet the TP-PMD specifications. Current is sinked from an isolation transformer by the TDP and TDN pins. The 125 Mbps bit stream is typically driven onto Unshielded Twisted Pair (UTP) cable. 6.1.3 100BASE-TX Receive Blocks The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the PHY unit will accurately receive valid data from Category 5 (CAT5) UTP cables of lengths well in excess of 100 meters. The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer performs adaptation based on the shape of the received signal. The clock recovery circuit uses digital signal processing to compensate for various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data to the MLT-3 decoder. The PHY unit first decodes the MLT-3 data; afterwards, the descrambler reproduces the 5B symbols originated in the transmitter. The data is decoded at the 4B/5B decoder. After the 4B symbols are obtained, the PHY unit outputs the receive data to the CSMA unit. In 100BASE-TX mode, the PHY unit can detect errors in receive data in a number of ways, including link integrity failures, undetected start of stream delimiters, invalid symbols, or idles in the middle of a frame.

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6.1.4 100BASE-TX Link In tegrity Auto-Negotiation The 82551QM Auto-Negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. Auto-Negotiation is described in IEEE specification 802.3u, clause 28. The PHY unit supports 10BASE-T half duplex, 10BASE-T full duplex, 100BASE-TX half duplex, and 100BASE-TX full duplex. Speed and duplex auto-select are functions of Auto-Negotiation. However, these parameters may be manually configured through the MII management interface (MDI registers). Manual configurations override the auto-select. 6.2 10BASE-T PHY Functions 6.2.1 10BASE-T Transmit Clock Generation The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz crystal or oscillator. The PHY unit provides the transmit clock and receive clock to the internal MAC at 2.5 MHz. 6.2.2 10BASE-T Transmit Blocks After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs Manchester encoding. Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented inside the chip. The PHY unit supports both technologies through one pair of TD pins and by externally sharing the same magnetics. In 10 Mbps mode, the line drivers use a pre-distortion algorithm to improve jitter tolerance. The line drivers reduce their drive level during the second half of “wide” Manchester pulses and maintain a full drive level during narrow pulses and the first half of the wide pulses. This reduces jitter caused by overcharging the line. 6.2.3 10BASE-T Receive Blocks The PHY unit performs Manchester decoding and timing recovery when in 10 Mbps mode. The Manchester-encoded data stream is decoded from the RD pair to separate Receive Clock and Receive Data from the differential signal. This data is transferred to the CSMA unit at 2.5 MHz/ nibble. In 10 Mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. The input differential voltage range capability for the Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V . The TPE receive buffer distinguishes valid receive data, link test pulses, and idles, according to the requirements of the 10BASE-T standard. In 10 Mbps mode, the PHY unit can detect errors in the receive data, including voltage drops prior to the end-of-frame bit. Collision detection in 10 Mbps mode is initiated by simultaneous transmission and reception. If the PHY unit detects this condition, it asserts a collision indication to the CSMA/CD unit.

Networking Silicon — 82551QM Datasheet 39 6.2.4 10BASE-T Link Integrity and Full Duplex The link integrity in 10 Mbps works with link pulses. The PHY unit senses and differentiates those link pulses from fast link pulses and from 100BASE-TX idles. The link beat pulse is also used to determine if the receive pair polarity is reversed. If it is, the polarity is corrected internally. The PHY unit supports 10 Mbps full duplex by disabling the collision function, the squelch test, and the carrier sense transmit function. This allows the PHY unit to transmit and receive simultaneously, achieving up to 20 Mbps network bandwidth using Auto-Negotiation. Full duplex can only be used in point-to-point connections (no shared media).

6.3 Auto-Negotiation

The PHY unit supports Auto-Negotiation, which is an automatic configuration scheme designed to manage interoperability in multifunctional LAN environments. An Auto-Negotiation capable device can detect and automatically configure its port to take maximum advantage of common modes of operation without user intervention or prior knowledge by either station. Auto- Negotiation is described in IEEE Standard 802.3u, clause 28.

6.3.1 Description

A PHY’s capability is encoded by bursts of link pulses called Fast Link Pulses (FLPs). Connection is established by FLP exchange and handshake during link initialization time. After the link is established by this handshake, the native link pulse scheme resumes. A reset or management re- negotiate command (through the MDI interface) will restart the process. If Auto-Negotiation is unsuccessful, the 82551QM will use Parallel Detection. The PHY unit supports four technologies: 100BASE-Tx Full and Half Duplex and 10BASE-T Full and Half Duplex. Since only one technology can be used at a time (after every re-negotiate command), a prioritization scheme is used to ensure that the ability of the highest common denominator is chosen.

6.3.2 Parallel Detect and Auto-Negotiation

The PHY unit can automatically determine the speed of the link by using Parallel Detect as an alternative to Auto-Negotiation. Upon a reset, a link status fail, or a negotiate/re-negotiate command, the PHY unit inserts a long delay during which no link pulses are transmitted. This period insures that the PHY unit‘s link partner has gone into a Link Fail state before Auto- Negotiation or Parallel Detection begins. The PHY unit will look for both FLPs and link integrity pulses. The following diagram illustrates this process.

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6.4 LED Description

The PHY unit supports three LED pins to indicate link status, network activity and network speed.

• Link: This LED is off until a valid link has been detected. After a valid link has been detected, the LED will remain on (active-low).
• Activity: This LED blinks on and off when activity is detected on the wire.
• Speed: This LED will be on if a 100BASE-TX link is detected and off if a 10BASE-T link is detected. If the link fails while in Auto-Negotiation, this LED will keep the last valid link state. If 100BASE-TX link is forced this LED will be on, regardless of the link status. This LED will be off if the 10BASE-T link is forced, regardless of the link status. MDI register 27 in Section 11.3.12, “Register 27: PHY Unit Special Control Register” details the information for LED function mapping and support enhancements. Figure 12 provides possible schematic diagrams for configurations using two and three LEDs.

Figure 11. Auto-Negotiation and Parallel Detect

Figure 12. Two and Three LED Schematic Diagram

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7.0 Modem Functionality

• 8-bit data bus: FLD7:0
• Control signals: AEN (FLCS#), MCNTSM# (FLA12), MINT (FLA11), MRING# (FLA10), MRST (FLA9), RD# (FLOE#), and WR# (FLWE#)
• 4 address lines

7.1 PCI Address Mapping to the Modem

The modem can be accessed by the PCI bus through either I/O or memory mapping.

7.2 Modem Read and Write Cycles

Basic read/write cycles to the modem device are shown in the figure below. Figure 13. Modem Read/Write Cycles

7.3 Modem and Preboot eXtensi on Environment Coexistence

The 82551QM local bus can interface with a Flash device or modem without external support. Modem Chip Select (MDMCS#) and Flash Chip Select (FLCS#) signals.

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7.3.1 Programming Details

1. Set the EEPROM’s MDM bit.
2. Clear the BD bit in the EEPROM.

modem and Function 1 (Modem) Configuration space to be available.

7.3.2 Support Circuitry

enabled; MDMCS# is high, the Flash device is enabled. Figure 14. Support Circuitry Example

Networking Silicon — 82551QM Datasheet 45

8.0 Manageability Functionality

The 82551QM acts as an SMB slave when receiving alert information and as bus master to collect information.

8.1 Alert Standard Format

The 82551QM supports the Alert Standard Format (ASF) Specification, version 1.0 to monitor the health of systems connected to the network, including desktop, workstation and server systems. Intel’s ASF hardware and software enables all systems on the network to report advanced warning and system failure messages to a network management console, in the powered-up, powered-down, and pre-boot state. This data network allows an IT manager to use ASF to remotely perform corrective action on a system. An example of how ASF adds values to a managed network environment is realized when a system cooling fan fails. The client sends an alert to the network management console. In turn the network IT Manager uses the remote control capabilities of ASF to shut the system down to prevent if from overheating. Another example would be if the operating system hangs. The network manager can re-boot or re-start the system remotely to recover the system. Both of these usages are performed by the IT Manager without leaving his desk. ASF is based on Intel’s Alert on LAN* 2 technology but adds standards-based interfaces and packets. ASF incorporates the System Management Bus, version 2.0 to monitor the system and detect hardware failures. SMB sensors are placed on the motherboard to detect hardware failures that include temperature, fan, and voltage failures. When a failure is detected, ASF requires a Platform Event Trap (PET) packet (for example, SNMP or UDP packet) to be generated to inform the network management console. These bit-based packets are lightweight because they are generated in the powered-down state or boot sequence. In the OS present state, ASF uses the Common Interface Model (CIM) to interact with software components. All warning or failure messages are CIM based. ASF provides pre-boot Firmware Progress messages and Firmware Error alerts. The Firmware Progress messages detail the progress of the system BIOS as it is running. The firmware error alerts detail hardware failures that the BIOS detects as the system is booting. The Watchdog Timer and the Watchdog Register are used to deliver the alerts to the network management console even if the system fails to boot. The ASF specification supports over twenty-five firmware messages and firmware error alerts. The system is monitored through SMB sensors, which may push alerts. Otherwise, the 82551QM polls the sensors. When an alert is detected the 82551QM generates a PET compliant packet and sends it to the network management console. Intel’s 82551QM implementation also supports Remote Management Control Protocol (RMCP) features such as heartbeat, LAN leash and presence ping/pong, along with the boot path definitions. The heartbeats and LAN leash alerts are supported in both the powered-up and powered-down state.

82551QM — Networking Silicon

46 Datasheet

The 82551QM provides 128 user defined alerts to monitor system hardware. The 82551QM supports SMB, version 2.0 sensors along with eight SMB, version 1.0 sensors as stated in the ASF specification. Some common SMB, version 1.0 sensors available on the market:

• Vo l t a g e
• Temperature
• Fan Tach In addition, Intel’s 82551QM includes support for the following remote control operations:
• Presence ping/pong
• System capability request/response
• System state request/response
• Power up
• Unconditional power down
• Reset and power cycle reset
• Boot path definitions —N O P — Force PXE boot — Force hard drive boot — Force diagnostic boot — Force CD/DVD boot

8.2 Heartbeat

82551QM can be configured to send a heartbeat packet periodically. The heartbeat period (10.7 seconds to 23 minutes) is controlled by the heartbeat timer. Heartbeat and Ping/Pong are mutually exclusive features. 82551QM can also send a heartbeat packet in response to an ICH event.

8.3 Ping/Pong

Upon receiving a “presence ping” packet, 82551QM replies with a “presence pong” packet. Heartbeat and Ping/Pong are mutually exclusive features. This feature can be enabled remotely through a management packet.

Networking Silicon — 82551QM Datasheet 47

8.4 Watchdog

A watchdog packet is sent when the watchdog timer expires. Software can use these registers to indicate the state of the system. For example, the watchdog timer can be set and enabled upon initial power up. If the system hangs before reaching this point, the watchdog timer expires and the 82551QM notifies the management console. When the watchdog timer expires, 82551QM enters Force TCO mode, enables reception of management packets, and sends a watchdog SOS packet if LINK is valid. Because a hard power loss can happen without software knowledge, it is important to disable watchdog events during low power modes. If a hard power loss occurs, an EEPROM load will reload the watchdog timer and possibly set it to be enabled. At the point that PWR_GOOD transitions high, the watchdog timer will become enabled (if configured enabled) and start counting from its initial loaded value, essentially restarting the boot-up time-out timer.

8.5 Advanced Power Management Modes

Upon receiving certain packets, 82551QM can perform Advanced Power Management (APM) transitions such as reset, power-up, and power-down.

8.6 Polling

82551QM acts as a master on the SMB to poll slaves for status, or set APM bits remotely. Target addresses to be polled are stored in the 82551QM’s configuration EEPROM.

8.7 Link Loss

If 82551QM detects a link loss for more than 5 seconds, it transmits an alert packet when the link is recovered.

8.8 Acknowledge

Management packets transmitted by 82551QM can be classified in three categories: SOS packets (event notifications), one-shot packets (receive acknowledgments, heartbeats and pongs), and ARP replies. 82551QM can be configured to retransmit each SOS packet a pre-defined number of times at a predefined interval until the SOS packet has been acknowledged. This capability adds reliability to ASF data transfer.

82551QM — Networking Silicon

48 Datasheet

Note: This page intentionally left blank.

9.0 Configuration Registers

commands and pointers that allow it to process receive and transmit data.

9.1 Function 0: LAN (Ethern et) PCI Configuration Space

9.1.1 PCI Vendor ID and Device ID Registers

Figure 15. PCI Configuration Registers

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9.1.2 PCI Command Register

configuration accesses. The format of this register is shown in the Figure 16. Figure 16. PCI Command Register Table 15. PCI Command Register Bits 15:10 Reserved These bits are reserved and should be set to 0b.

8 SERR# Enable

configurable and has a default value of 0b.

6 Parity Error Control

the 82551QM, this bit is configurable and has a default value of 0b.

4 Memory Write and

configurable and has a default value of 0b.

9.1.3 PCI Status Register

format of this register is shown in the figure below. are described in the table below.

2 Bus Master

configurable and has a default value of 0b.

1 Memory Space

configurable and has a default value of 0b.

0 I/O Space

and has a default value of 0b. Figure 17. PCI Status Register Table 16. PCI Status Register Bits

31 Detected Parity Error

Parity Error bit is 0b. This bit is set until cleared by writing a 1b.

30 Signaled System Error

29 Received Master

Abort bit is 0b. This bit is set until cleared by writing a 1b.

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9.1.4 PCI Revision ID Register

9.1.5 PCI Class Code Register

2h. The middle byte is a subclass code and specifies the 82551QM as an Ethernet controller, 0h.

28 Received Target Abort

bit is 0b. This bit is set until cleared by writing a 1b.

27 Signaled Target Abort

This bit indicates whether a transaction was terminated by a target abort. with target abort. In the 82551QM, this bit is always set to 0b. In the 82551QM, these bits are always set to 1b, medium.

24 Parity Error Detected

1. The bus agent asserted PERR# itself or observed PERR# asserted.
2. The agent setting the bit acted as t he bus master for the operation in
3. The Parity Error Response bit in th e command register (bit 6) is set.

bit is set until cleared by writing a 1b.

23 Fast Back-to-Back

the 82551QM, this bit is read only and is set to 1b.

20 Capabilities List

bit is set only if the power management bit in the EEPROM is set. 19:16 Reserved These bits are reserved and should be set to 0000b.

9.1.6 PCI Cache Line Size Register

register is read. The figure below illustrates the format of this register. return a value of 0b on read.

9.1.7 PCI Latency Timer

this register defines the amount of time, in PCI clock cycles, that it may own the bus.

9.1.8 PCI Header Type

will read the next configuration registers bank at offset 100h.

9.1.9 PCI Base Address Registers

Figure 18. Cache Line Size Register

000 R W R W 000

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determine the mapping of a particular device. map to I/O space must return 1b in bit 0. reserved and must return 0b on reads, and the other bits are used to map the device into I/O space. The 82551QM contains BARs for the Control/Status Register (CSR), Flash, and Expansion ROM.

9.1.9.1 CSR Memory Mapped Base Address Register

or I/O, is used to access the 82551QM CSR registers. not prefetchable and is mapped anywhere in the 32-bit memory address space. Figure 19. Base Address Register for Memory Mapping Figure 20. Base Address Register for I/O Mapping

Networking Silicon — 82551QM Datasheet 55

9.1.9.2 CSR I/O Mapped Base Address Register

The 82551QM requires one BAR for I/O mapping. Software determines which BAR, I/O or memory, is used to access the 82551QM CSR registers. The I/O space for the 82551QM CSR I/O BAR is 64 bytes.

9.1.9.3 Flash Memory Mapped Base Address Register

The Flash Memory BAR is a Dword register. The 82551QM physically supports a 128 KB Flash device. In a CardBus system, the upper section of the memory mapped window (above the physical Flash device) is used for CIS information. The 82551QM claims a window of 128 KB in CardBus mode and always claims a Flash memory window, regardless of whether or not a Flash device is connected.

56 Datasheet

9.1.9.4 Expansion ROM Base Address Register

9.1.10 Base Address Registry Summary

9.1.11 CardBus Card Information Structure (CIS) Pointer

the CIS structure is mapped in the Flash address space.

9.1.12 PCI Subsystem Vendor ID and Subsystem ID Registers

PCI Special Interest Group (SIG). vendor indicated in the Subsystem Vendor ID field. Table 17. Base Address Register Functions

64 KB 128 KB

Table 18. CIS Pointer

The 82551QM provides support for configurable Subsystem Vendor ID and Subsystem ID fields. the EEPROM. The first of these 16-bit values is used for controlling various 82551QM functions. default values for the Subsystem ID and Subsystem Vendor ID are 0h and 0h, respectively. according to Table 19 below. of the Revision ID field are programmed by bits 10:8 of the first EEPROM word, Ah.

9.1.13 Capability Pointer

within the Configuration Space for the location of the Power Management registers.

9.1.14 Interrupt Line Register

the device’s PCI interrupt request pin (as defined in the Interrupt Pin register) is routed to.

9.1.15 Interrupt Pin Register

INTA# through INTD#, a PCI device is connected to. The 82551QM is connected the INTA# pin. Table 19. ID Fields Programming a. The Revision ID is subject to c hange according to the silicon stepping. b. If bit 15 equals 1b, the EEPROM is invalid and the default values are used.

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9.1.16 Minimum Grant Register

9.1.17 Maximum Latency Register

PCI bus. The default value of this register for the 82551QM is 18h.

9.1.18 Capability ID Register

9.1.19 Next Item Pointer

capability list. Since power management is the last item in the list, this register is set to 0b.

9.1.20 Power Management Capabilities Register

Table 20. Power Management Capability Register D0, D1, D2, and D3hot if it is fed by PCI power. able to use it. DSI is required for the 82551QM after D3-to-D0 reset.

9.1.21 Power Management Cont rol/Status Register (PMCSR)

supplied by the system for wake-up from the D3cold state. of the PCI Power Management Specification, Revision 2.2. Table 21. Power Management Control and Status Register is enabled, the PME# signal reflects the state of the PME status bit. the Function Event register. the Data register and Data Scale field. 8 0b Read Clear PME Enable. This bit enables the 82551QM to assert PME#. 7:5 000b Read Only Reserved. These bits are reserved and should be set to 000b. the power consumption dynamically. 3:2 00b Read Only Reserved. These bits are reserved and should be set to 00b. state of the 82551QM and to set the 82551QM into a new power state. The definition of the field values is as follows.

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9.1.22 Data Register

the data register is listed in Table 22.

9.2 Function 1: Modem PC I Configuration Space

active depending on the EEPROM setup. Table 22. Ethernet Data Register Figure 21. Modem PCI Configuration Registers

detail in the following subsections.

9.2.1 Modem Configur ation ID Register

The Modem Configuration ID field is a Dword register composed of the Device ID and Vendor ID. It is a read only register and its value is loaded from the EEPROM.

9.2.2 Modem Command Register

Table 23. Power Management Control and Status Register 15:10 000000b Read Only Reserved. These bits are reserved and should be set to 000000b. 9 0b Read Only Fast Back-to-Back. 8 0b Read/Write System Error Enable. 7 0b Read Only Wait Cycle Enable. 6 0b Read/Write Parity Error Enable. 5 0b Read Only VGA (define). 4 0b Read Only Memory Write and Invalidate. 3 0b Read Only Special Cycle. 2 0b Read Only Master Enable. 1 0b Read/Write Memory Access Enable. 0 0b Read/Write I/O Access Enable.

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9.2.3 Modem Status Register

The Modem Status field is a 16-bit word register. It provides basic track of CardBus related events. All bits are cleared by RST#.

9.2.4 Modem Revision ID Register

identifies the function as a modem. The Class Code and Revision ID are listed in Table 25.

9.2.5 Modem Header Type Register

multifunction card and a value of 80h is hard-coded in the silicon.

9.2.6 Modem I/O Base Address Register

82551QM’s modem. The required I/O space is 8 bytes. Table 24. Modem Status Register 15 0 Read/Write Parity Error. 14 0 Read/Write System Error Enable. 13:11 000 Read Only Signaled/Received Target Abort. 10:9 01 Read Only Device Select Timing. 8 0 Read Only Data Parity Detect. 7 0 Read Only Fast Back-to-Back Capable. 6:5 00 Read Only Reserved. These bits are reserved and should be set to 00b. 4 1 Read Only New Capability. 3:0 0000 Read Only Reserved. These bits are reserved and should be set to 0000b. Table 25. Modem Revision Register 23:16 00h Read Only Subclass. This indicates the serial controller equals 00h. compatible and initialized by EEPROM word FEh.

Networking Silicon — 82551QM Datasheet 63

9.2.7 Modem Memory Base Address Register

The Modem Memory BAR is a Dword register that specifies the memory base address for accessing the 82551QM’s modem port. The required memory space is 4 KB. The memory space is used for both control registers and CIS mapping.

9.2.8 Modem CardBus CIS Pointer

The CIS pointer is a Dword, hard-coded, read only register. The CIS pointer indicates whether or not the CIS structure is located in the memory address space. The physical location of the CIS structure is in the serial EEPROM. The EEPROM format is described in Section 5.7, “Serial EEPROM Interface”.

9.2.9 Modem Subsystem Vendor ID Register

The Modem Subsystem Vendor ID is a 16-bit read only register. Its value is loaded from the EEPROM and is a reflection of register 2Ch in Function 0, LAN (Ethernet) function.

9.2.10 Modem Subsystem ID Register

The Modem Subsystem ID is a 16-bit, read only register. Its value is loaded from the EEPROM and is a reflection of register 2Eh in Function 0, LAN (Ethernet) function.

9.2.11 Modem Capabilities Pointer

The Modem Capability Pointer is a hard-coded, byte register that contains the value DCh. It provides an offset within the Configuration Space for the location of the power management registers.

9.2.12 Modem Interrupt Register

The Modem Interrupt register specifies whether or not the modem requires an interrupt. This register is hard-coded identically to register 3Ch in Function 0, LAN (Ethernet). It indicates that the modem requires interrupt support. Note: The modem and Ethernet functions share the same INTA# pin.

9.2.13 Modem Power Manageme nt Capabilities Register

The Modem Power Management Capabilities register is a Dword field that indicates if this function has power management capability. It also identifies which power management capabilities are supported. The 82551QM reports a value of FE31h if it is connected to an auxiliary power source; and 7E21h, otherwise. Bits R/W Default Description 31:4 R 0010h Modem CIS Pointer (above the control registers) 3:0 R 2h CIS in the Memory Base Address Register

64 Datasheet

9.2.14 Modem Power Management Control/Status Register

Function 0, LAN (Ethernet) function.

9.2.15 Modem Data Register

The Modem Data register has similar functionality to register E2h in Function 0, LAN (Ethernet). power consumption and power dissipation are loaded from the EEPROM.

9.2.16 Modem Support in PCI Mode

SMB interface of the 82551QM. Table 26. Ethernet Data Register

10.0 Control/Status Registers

10.1 LAN (Ethernet) Control/Status Registers

The 82551QM’s Control/Status Register (CSR) is illustrated in the Table 22. as the Power Management Driver Register. interrupt indications in this register for the CPU to read. register. Interrupts are also acknowledged in this register. memory depending on the current SCB Command word. to dump information to main memory, or perform an internal self test. Figure 22. Control/Status Register

66 Datasheet

from the PHY unit (or an external PHY component) through the Management Data Interface. bytes of receive data have been passed into host memory via DMA. control commands to the 82551QM. that a wake-up interrupt has occurred. down state and provides the ability to disable the Clock Run functionality. applications and specifies the event that changed the status. condition that may cause a status change or interrupt.

10.1.1 System Control Block Status Word

82551QM’s Command and Receive units. Table 27. System Control Block Status Word completed executing a command with its interrupt bit set. either an idle or suspended state.

12 RNR

situation, or set suspend bit due to a filled Receive Frame Descriptor.

11 MDI

Interface Control register in the CSR).

10 SWI

9 Reserved This bit is reserved and should be set to 0b.

10.1.2 System Control Block Command Word

Commands for the 82551QM’s Command and Receive units are placed in this register by the CPU.

10.1.3 System Control Block General Pointer

structures depending on the command in the CU Command or RU Command field.

10.1.4 PORT

• Address and Data (bits 32:4)
• PORT Function Selection (bits 3:0) The 82551QM supports four PORT commands: Software Reset, Self-test, Selective Reset, and Dump.

10.1.5 Flash Control Register

The Flash Control Register is a 32-bit field that allows access to an external Flash device. 8F C P Flow Control Pause. The FCP bit is used as the flow control pause bit. 5:2 RUS Receive Unit Status. The RUS field contains the status of the Receive Unit. 1:0 Reserved These bits are reserved and should be set to 0b. Table 28. System Control Block Command Word to generate an interrupt. Writing a 0b to this bit has no effect. Interrupt Mask bits and the SI bit. 23:20 CUC Command Unit Command. This field contains the CU command. 19:16 RUC Receive Unit Command. This field contains the RU command.

68 Datasheet

10.1.6 EEPROM Control Register

10.1.7 Management Data In terface Control Register

10.1.8 Receive Direct Memo ry Access Byte Count

passed into host memory via DMA.

10.1.9 Flow Control Register

• Flow Control Command The Flow Control Command field describes the action of the flow control process (for example, pause, on, or off).
• Flow Control Threshold The Flow Control Threshold field contains the threshold value (in other words, the number of free bytes in the Receive FIFO).

Table 29. MDI Control Register 31:30 These bits are reserved and should be set to 0b. indicate the end of an MDI cycle. set this bit to 0 at the same time the command is written. 25:21 PHY Address. This field of bits contains the PHY address. 20:16 PHY Register Address. This field of bits contains the PHY Register Address. serially from the PHY unit, and software reads the data from this location.

10.1.10 Power Manageme nt Driver Register

The 82551QM provides an indication in memory and I/O space that a wake-up event has occurred. Table 30. Power Management Driver Register following a change in link status and is cleared by writing a 1b to it. Status Register. This bit is cleared by writing 1b to it. filters. This bit is cleared by writing 1b to it. Reserved. This bit is reserved and should be set to 0b. by an external TCO controller. Force TCO Indication. This bit is reserved for testing. up event and is independent of the PME Enable bit. in the Function Event register is cleared.

70 Datasheet

Note: The PMDR is initialized at ALTRST# reset only.

10.1.11 General Control Register

is used in CardBus mode only.

10.1.12 General Status Register

10.1.13 Ethernet Card St atus Change Registers

CSTSCHG . There are four event related registers.

1. Function Event Register: Specif ies the event that changed status
2. Function Event Mask Register: Masks CS TSCHG signal assertion for specified events
3. Function Present State Regist er: Reflects the current state of each condition that may cause a
4. Force Event Register: Simulates status change events for troubleshooting purposes

Table 31. General Control Register 7:2 000000b Read Only Reserved. These bits are reserved and should be set to 000000b. the D2 and D3 power states while the link is down. supported for point-to-point connection of two end stations. Table 32. General Status Register 7:3 00000b Read Only Reserved. These bits are reserved and should be set to 00000b.

the event, and to control the CSTSCHG signal. compliant OS. They are initialized by a power-up reset on the ALTRST# pin. Note: Access to the CSTSCHG registers in PCI mode is not allowed.

10.1.13.1 LAN Function Event Register

The Function Event register specified the event that changed the status.

1. For a combination LAN/modem card, the 82551Q M implements two independent sets of card status change registers. Each set controls its

Table 33. LAN Function Event Register 31:16 Reserved 0 Bits [31:16] are rese rved in the CardBus Specification.

15 INTR 0b

serviced. Writing 0b to this field has no effect. 14:5 Reserved 0 Bits [14:5] are reserved in the CardBus Specification.

4 GWAKE 0b

3 Reserved 0b Bit 3 is reserved in the CardBus Specification. 0 Reserved 0b Bit 0 is reserved in the CardBus Specification.

72 Datasheet

10.1.13.2 LAN Function Event Mask Register

The Function Event Mask register masks CSTSCHG and INTA# assertion.

10.1.13.3 LAN Function Present State Register

Table 34. LAN Function Event Mask Register 31:16 Reserved 0 Bits [31:16] are reserved in the CardBus Specification. interrupt mask bit affects the INTA# masking.

14 WKUP 0b

Function Event register. This bit is dependent on bit 4 of this register. 13:7 Reserved 0 Bits [13:7] are reserved in the CardBus Specification. (PWM BAM). Note that the PWM BAM bits are not applicable for LAN. 3 Reserved 0b Bit 3 is reserved in the CardBus Specification. 0 Reserved 0b Bit 0 is reserved in the CardBus Specification. Table 35. LAN Function Present State Register 31:16 Reserved 0 Bits [31:16] are reserved in the CardBus Specification.

15 INTR 0

14:5 Reserved 0 Bits [14:5] are reserved in the CardBus Specification.

4 GWAKE 0

is gated by the programmable filter command.

10.1.13.4 LAN Force Event Register

provides the ability to simulate events by forcing values into the Function Event register.

10.2 Statistical Counters

3 Reserved 0b Bit 3 is reserved in the CardBus Specification. 0 Reserved 0b Bit 0 is reserved in the CardBus Specification. Table 36. LAN Force Event Register 31:16 Reserved 0 Bits [31:16] are rese rved in the CardBus Specification. then it will also be activated. Writing 0b has no effect. 14:5 Reserved 0 Bits [14:5] are reserved in the CardBus Specification. is not masked, then it will also be activated. Writing 0b has no effect. 3:0 Reserved 0 Bits [3:0] are reserved in the CardBus Specification. Table 37. Statistical Counters

0 Transmit Good Frames

4 Transmit Maximum Collisions

maximum number of collisions.

8 Transmit Late Collisions

74 Datasheet

12 Transmit Underrun Errors

may be updated multiple times for a single frame.

16 Transmit Lost Carrier Sense (CRS)

the de-assertion of CRS during the transmission.

20 Transmit Deferred This counter contains the number of frames that were

deferred before transmission due to activity on the link.

24 Transmit Single Collisions This counter contains the number of transmitted frames that

28 Transmit Multiple Collisions This counter contains the number of transmitted frames that

encountered more than one collision.

32 Transmit Total Collisions

late collisions and frames that encountered MAXCOL.

36 Receive Good Frames

40 Receive CRC Errors

and Receive Short Frame Errors counters.

44 Receive Alignment Errors

CRC Errors and Receive Short Frame Errors counters.

48 Receive Resource Errors

frame, the Receive Resource Errors counter is not updated.

52 Receive Overrun Errors

frame indicator, they are not counted.

56 Receive Collision Detect (CDT) This counter contains the number of frames that encountered

collisions during frame reception.

60 Receive Short Frame Errors

• The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around to 0.
• The 82551QM updates the required counters for each frame. It is possible for more than one counter to be updated as multiple errors can occur in a single frame.
• The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1 standard. The 82551QM supports all mandatory and recommend statistics functions through the status of the receive header and directly through these Statistical Counters. The CPU can access the counters by issuing a Dump Statistical Counters SCB command. This provides a “snapshot”, in main memory, of the internal 82551QM statistical counters. The 82551QM supports 21 counters. The dump could consist of either 16 or 21 counters, depending on the status of the Extended Statistics Counters and TCO Statistics configuration bits in the Configuration command.

10.3 Modem Control/Status Registers

64 Flow Control Transmit Pause

68 Flow Control Receive Pause

frames received and Xon [PAUSE(0)] frames received.

72 Flow Control Receive Unsupported

but has an unsupported opcode.

76 Receive TCO Frames This counter contains the number of TCO packets received by

78 Transmit TCO Frames This counter contai ns the number of TCO packets transmitted.

76 Datasheet

10.3.1 Modem Base Memory Addressing

1. Modem chipset address space: 0h to Fh
2. Modem function address space: 80h to FFh (implemented in 82551QM)
3. Modem CIS address space: 100h to 1FFh (loaded from EEPROM)

10.3.2 Modem Base I/O Addressing

10.3.3 Modem CardBus CSTCHG Registers

power-up reset driven on the ALTRST# pin.

10.3.3.1 Modem Function Event Register

Ethernet Function Event register described in Section 10.1.13.1, “LAN Function Event Register”. Table 38. Modem Based Memory Address Registers Table 39. Modem Based I/O Address Registers 0h:7h Venus MIMIC port, ISA address space 7:0.

10.3.3.2 Modem Function Event Mask Register

10.3.3.3 Modem Function Present State Register

Table 40. Modem Function Event Mask Register 31:16 Reserved 0 Bits 31:16 are reserved in the CardBus Specification. bit in the System Control Block (SCB) register within the CSR space. Event register. This bit is dependent on bit 4 of this register. 13:7 Reserved 0 Bits 13:7 are reserved in the CardBus Specification. BAM 0 These bits are used for Pulse Width Modulation Binary Audio Enable. 3 Reserved 0b Bit 3 is reserved in the CardBus Specification. 0 Reserved 0b Bit 0 is reserved in the CardBus Specification. Table 41. Modem Function Present State Register 31:16 Reserved 0 Bits 31:16 are reserved in the CardBus Specification. Interrupt (MINT) input pin from the modem. 14:5 Reserved 0 Bits 14:5 are reserved in the CardBus Specification. of the Modem Ring (MRING#) input pin from the modem. 3 Reserved 0b Bit 3 is reserved in the CardBus Specification.

78 Datasheet

10.3.3.4 Modem Force Event Register

0 Reserved 0b Bit 0 is reserved in the CardBus Specification.

11.0 PHY Unit Registers

Interface (MDI) within the CSR space.

11.1 MDI Registers 0 - 7

11.1.1 Register 0: Control Register

Table 42. Register 0: Control

15 Reset This bit sets the status and control register of the PHY to

accepts a read or write transaction.

14 Loopback This bit enables loopback of transmit data nibbles from

unit’s receive circuitry is isolated from the network.

13 Speed Selection This bit controls s peed when Auto-Negotiation is disabled

and is valid on read when Auto-Negotiation is disabled.

12 Auto-Negotiation

when Auto-Negotiation is enabled.

80 Datasheet

11.1.2 Register 1: Status Register

9 Restart Auto-

8 Duplex Mode This bit controls the duplex mode when Auto-Negotiation

correspond to the mode which the PHY can operate.

7 Collision Test This bit will force a co llision in response to the assertion

of the transmit enable signal. Table 43. Register 1: Status

6 Management

5 Auto-Negotiation

4 Remote Fault 0 = No remote fault condition detected 0 RO

11.1.3 Register 2: PHY Identifier Register

11.1.4 Register 3: PHY Identifier Register

11.1.5 Register 4: Auto-Negot iation Advertisement Register

3 Auto-Negotiation

2 Link Status 1 = Valid link has been established

1 Jabber Detect 1 = Jabber condition detected

0 Extended

Table 44. Register 2: PHY Identifier Table 45. Register 3 PHY Identifier Table 46. Register 4: Auto-Negotiation Advertisement

15 Next Page Constant 0 = Transmitting primary capability data

13 Remote Fault 1 = Indicate link partner’s remote fault

to the selector field value. 00001b, IEEE Standard 802.3.

82 Datasheet

11.1.6 Register 5: Auto-Negotiati on Link Partner Ability Register

11.1.7 Register 6: Auto-Ne gotiation Expansion Register

11.2 MDI Registers 8 - 15

Registers 8 through 15 are reserved for IEEE. Table 47. Auto-Negotiati on Link Partner Ability

15 Next Page This bit reflects the PHY’s link partner’s Auto-

14 Acknowledge This bit is used to indicate that the 82551QM’s PHY

Negotiation advertising ability.

13 Remote Fault This bit reflects the PHY’s link partner’s Auto-

4 Parallel Detection

3 Link Partner Next

2 Next Page Able 1 = Local drive is Next Page able

1 Page Received 1 = New Page received

This bit will self-clear on read.

0 Link Partner Auto-

11.3 MDI Register 16 - 31

11.3.1 Register 16: PHY Unit Status and Control Register

11.3.2 Register 17: PHY Unit Special Control Register

Table 49. PHY Unit Status and Control

13 Carrier Sense

This bit enables the disconnect function.

12 Transmit Flow

11 Receive De-

receive de-serializer in-sync. 8 Polarity This bit indicates 10BASE-T polarity. 1 Speed This bit indicates the Auto-Negotiation result. 0 Duplex Mode This bit indicates the Auto-Negotiation result. Table 50. Register 17: PHY Unit Special Control

15 Scrambler By-

14 By-pass 4B/5B 1 = 4 bit to 5 bit by-pass

13 Force Transmit H-

84 Datasheet

11.3.3 Register 18: PHY Address Register

11.3.4 Register 19: 100BASE-TX Receive False Carrier Counter

12 Force 34

11 Good Link 1 = 100BASE-TX link good

9 Transmit Carrier

8 Disable Dynamic

7 Auto-Negotiation

6 MDI Tri-State 1 = MDI Tri-state (transmit driver tri-states)

5 Filter By-pass 1 = By-pass filter

4 Auto Polarity

3 Squelch Disable 1 = 10BASE-T squelch test disable

2 Extended

1 Link Integrity

0 Jabber Function

Table 51. Register 18: PHY Address Table 52. Register 19: 100BASE-TX Receive False Carrier Counter

11.3.5 Register 20: 100BASE- TX Receive Disconnect Counter

11.3.6 Register 21: 100BASE-TX Receive Error Frame Counter

11.3.7 Register 22: Recei ve Symbol Error Counter

11.3.8 Register 23: 100BASE-TX R eceive Premature End of Frame Error

11.3.9 Register 24: 10BASE-T Recei ve End of Frame Error Counter

Table 53. Register 20: 100BASE-TX Receive Disconnect Counter Table 55. Register 22: Receive Symbol Error Counter Table 56. Register 23: 100BASE-TX Receive Premature End of Frame Error Counter freezes when full and self-clears on read.

86 Datasheet

11.3.10 Register 25: 10BASE-T Tr ansmit Jabber Detect Counter

11.3.11 Register 26: Equalizer Control and Status Register

11.3.12 Register 27: PHY Unit Special Control Register

Table 58. Register 25: 10BASE-T Transmit Jabber Detect Counter Table 60. Register 27: PHY Unit Special Control

11.3.13 Register 28: MDI/ MDI-X Control Register

11.3.14 Register 29: Hardware Integrity Control Register

Table 61. Register 28: MDI/MDI-X Control

7 Auto Switch

overwrites the default value). Manual switch (valid only if bit 7 is set to 0). 1 = Forces the port to be MDI-X (cross-over). Indicates the state of the MDI pair.

4 Auto Switch

Indicates when the correct configuration is achieved. 1 = Resolution algorithm has completed. 0 = Resolution algorithm has not completed. order to switch between one configuration or another.

0000 R/W

Table 62. Register 29: Hardware Integrity Control

15 HWI Enable This bit enables the HW I feature causing the PHY unit

14 Ability Check This bit reports t he results of the HWI ability check

13 Test Execute When this bit is se t, the PHY unit launches test pulses

high or low impedance point.

88 Datasheet

Test Execute bit (bit 13 of this register) is set. defined in granularities of 80 cm (35 inches).

Networking Silicon — 82551QM Datasheet 89

12.0 Electrical and Timing Specifications

Note: This section contains information on products in sampling and early production phase of development. Do not finalize a design with this information. Revised information will be published when the product becomes available.

12.1 Absolute Maximum Ratings

Maximum ratings are listed below: Note: The 82551IT maximum rating for the Ambient Temperature is -40° C to 85° C. Stresses above the listed absolute maximum ratings may cause permanent damage to the 82551QM device. This is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

90 Datasheet

12.2 DC Specifications

1. Preferably, VIO should be 5 V ± 5% in any PCI environment (either 5 V or 3.3 V signaling). If 5 V is not
2. Typical current consumption is in nominal operating conditions (VCC = 3.3 V) and average link activity.

Maximum current consumption is in maximum VCC and maximum link activity. volts tolerant and supports both 5 V and 3.3 V signaling environments. Table 63. General DC Specifications Table 64. PCI/CardBus Interface DC Specifications

1. These values are only applicable in 3.3 V signaling environments. Outside of this limit the input buffer must

consume its minimum current.

1. Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs.
2. Signals without pull-up resistors have 3 mA low output current; and signals requiring pull-up resistors, 6 mA.
3. This value is characterized but not tested.
4. This input leakage current is the maximum allowable leakage into the PME# open drain driver when power is
5. SMB outputs (SMB_ALERT#, SMBDATA, and SMBCLK) are open drain.
6. The input leakage current through the pull-up resistor is the maximum allowable leakage into the SMB open

cause the device to assert SMB.

1. This value is characterized but not tested.

Table 65. SMB Interface DC Specifications Table 66. Flash/Modem/EEPROM Interface DC Specifications

92 Datasheet

1. Current is measured on all VCC pins (VCC = 3.3 V). Recommended starting value for RBIAS100.
2. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by
3. Current is measured on all VCC pins (VCC = 3.3 V). Recommended starting value for RBIAS10.
4. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by

Table 67. LED Voltage/Current Characteristics Table 68. 100BASE-TX Voltage/Current Characteristics Table 69. 10BASE-T Voltage/Current Characteristics

12.3 AC Specifications

1. Switching Current High specifications are not relevant to PME#, SERR#, or INTA#, which are open drain
2. Maximum current requirements will be met as drivers pull beyond the first step voltage (AC drive point).

current test point is defined for each side of the output driver.

1. This parameter is also applicable to CardBus environment.
2. Do not test. Guranteed by design.

Table 70. Digital I/O Characteristics Table 71. Crystal Input One (X1) Characteristics Table 72. AC Specifications for PCI Signaling

94 Datasheet

12.4 Timing Specifications

12.4.1 Clocks Specifications

12.4.1.1 PCI/CardBus Clock Specifications

1. The 82551QM will work with any PCI clock frequency up to 33 MHz.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the

minimum peak-to-peak portion of the clock waveform as shown in Figure 23. Table 73. AC Specifications for CardBus Signaling Figure 23. PCI/CardBus Clock Waveform Table 74. PCI/CardBus Clock Specifications

12.4.1.2 X1 Specifications

requirements from this signal.

12.4.2 Timing Parameters

12.4.2.1 Measurement and Test Conditions

Table 75. X1 Clock Specifications Figure 24. Output Timing Measurement Conditions

96 Datasheet

Figure 25. Input Timing Measurement Conditions Table 76. Measure and Test Condition Parameters

12.4.2.2 PCI/CardBus Timings

1. Timing measurement conditions are illustrated in Figure 24.
2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section
3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times

and input setup times than bussed signals. All other signals are bussed.

1. Timing measurement conditions are illustrated in Figure 25.
2. RST# is asserted and de-asserted asynchronously with respect to the CLK signal.
3. All PCI and CardBus interface output drivers are floated when RST# is active.
4. CardBus minimum times are specified with a 0 pF equivalent load. Maximum times are specified with a 30 pF

equivalent load. Actual test loads may vary but must be correlated to these loads.

12.4.2.3 Flash/Modem Interface Timings

illustrated in Figure 26 and Figure 27.

• FLA6:0, FLD7:0, FLCS#, FLOE#, and FLWE# have the same functions for Flash and modem.

Table 77. PCI/CardBu s Timing Parameters

98 Datasheet

• FLA8 acts as IOCHRDY asynchronous input in modem mode. NOTES: 1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150 timings. 2. These timing specifications apply to Flash write cycles. The Flash timings referenced are 28F020-150 timings.

Table 78. Flash Timing Parameters

100 Datasheet

12.4.2.4 EEPROM Interface Timings

Table 79. EEPROM Timing Parameters Figure 28. EEPROM Timings

12.4.2.5 PHY Timings

Table 80. 10BASE-T Normal Link Pulse (NLP) Timing Parameters Figure 29. 10BASE-T Normal Link Pulse (NLP) Timings Table 81. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters Figure 30. Auto-Negotiation Fast Link Pulse (FLP) Timings

102 Datasheet

12.4.2.6 SMB Interface Timings

Table 82. 100Base-TX Transmitter AC Specification Table 83. Flash Timing Parameters

Networking Silicon — 82551QM Datasheet 103 13.0 82551QM Test Port Functionality

13.1 Introduction

The 82551QM’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing.

13.2 Test Function Description

The 82551QM TAP mode supports two tests that can be used in board level design. These tests help verify basic functionality as well as test the integrity of solder connection on the board. The tests are described in the following subsections.

13.2.1 Tristate

The tristate command sets all 82551QM input and output pins into a tristate (high-Z) mode (all internal pull-ups and pull-downs are disabled). This mode is entered by setting the following test pin combination and resetting the device: TEST = 1 TEXEC = 0 TCK = 0 TI = 1

104 Datasheet

13.2.2 XOR Tree

Table 84. XOR Tree Chains

2 IDSEL ACTLED#

3 REQ# SPDLED#

4 AD[23]

5 SERR#

6 AD[22]

7 AD[21]

8 AD[20] ALTRST#

9 AD[19] CLK_RUN#

10 AD[18] AD[31]

11 AD[17] AD[30]

12 C/BE#[2] AD[29]

13 FRAME# AD[28]

14 IRDY# AD[27]

15 TRDY# PME#

16 CLK

17 DEVSEL# AD[26]

18 INTA# AD[25]

19 STOP# C/BE#[3]

20 GNT# AD[24]

21 PERR# FLD0

22 PAR FLD1

23 AD[16] FLD2

24 C/BE#[1] FLD3

25 AD[15] FLD4

26 AD[14] FLD5

27 AD[13] FLD6

28 AD[12] FLD7

29 AD[11] FLA0

30 AD[10] FLA1

31 AD[9] FLA2

32 AD[8] FLA3

33 C/BE#[0] FLA4

34 AD[7] FLA5

35 AD[6] FLA6

36 AD[5] FLA7

37 AD[4] FLA8

37 AD[3] FLA9

39 AD[2] FLA10

40 AD[1] FLA11

41 AD[0] FLA12

42 EECS FLA13/EEDI

43 FLA14/EEDO

44 FLA15/EESK

45 FLA16

46 FLCS#

82551QM — Networking Silicon

106 Datasheet

Note: This page is intentionally left blank.

14.0 Package and Pinout Information

14.1 Package Information

Figure 31. More information on Intel® device packaging is available in the Intel Packaging Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change. Figure 31. Dimension Diagram for the 196-pin BGA Note: All dimensions are in millimeters.

108 Datasheet

Figure 32. 196 PBGA Package Pad Detail

14.2 Pinout Information

14.2.1 Pin Assignments

Table 85. Pin Assignments

110 Datasheet

14.2.2 Ball Grid Array Diagram

Figure 33. Ball Grid Array Diagram

100 TDP TEXEC RDP FLD1 VCC FLD5 FLA0 FLA9FLA10FLA7FLA4VCCTEST

10 TDN TCK RDN FLD0 VSSPL FLD4 FLD7 NCFLA8/

82551QM — Networking Silicon

112 Datasheet

15.0 Reference Schematics

This section shows a 10/100 Mbps design using the 82551QM Fast Ethernet Multifunction PCI/ CardBus Controller.

Figure 34. Reference Schematic Layout (Sheet 1 of 2) each time activity is detected. are used on the bottom side of the board, then place decoupling under the 82551IT. should not have any direct connection. Keep trace length from magnetics to RJ-45 connector under one inch. close to the 82551 as possible. This capacitor is normally not installed; however a placement can be provided. must be taken in selecting the values used.

10 TX+

75 Ohms

11 TX- TD-

114 Datasheet

Figure 35. Reference Schematic Layout (Sheet 2 of 2) other than hard strapping the pins. following the PCI bus re-activation. acheived if this signal is connected to +5V in PCI bus systems regardless of bus voltage.