82541 INTEL
Document overview
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- PDF pages: 46
Technical content
Datasheet sections
- 1.0 Introduction
- 1.1 Document Scope
- 1.2 Reference Documents
- 1.3 Product Codes
- 2.1 External Architecture Block Diagram
- 2.2 Internal MAC Architecture Block Diagram
- 2.3 Integrated 10/100/1000Mbps PHY
- 2.4 System Interface
- 3.0 Signal Descriptions
- 3.1 Signal Type Definitions
- 3.2 PCI Bus Interface Signals (56)
- 3.2.1 PCI Address, Data and Control Signals (44)
- 3.2.2 Arbitration Signals (2)
- 3.2.3 Interrupt Signal (1)
- 3.2.4 System Signals (4)
- 3.2.5 Error Reporting Signals (2)
- 3.2.6 Power Management Signals (3)
- 3.2.7 SMB Signals (3)
- 3.3 EEPROM and Serial FLASH Interface Signals (9)
- 3.4 Miscellaneous Signals
- 3.4.1 LED Signals (4)
- 3.4.2 Other Signals (4)
- 3.5 PHY Signals
- 3.5.1 Crystal Signals (2)
- 3.5.2 Analog Signals (10)
- 3.6 Test Interface Signals (6)
- 3.7 Power Supply Connections
- 3.7.1 Digital and Analog Supplies
- 3.7.2 Grounds, Reserved Pins and No Connects
- 3.7.3 Voltage Regulation Control Signals (2)
- 4.0 Voltage, Temperature, and Timing Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 Targeted Recommended Operating Conditions
- 4.2.1 General Operating Conditions
- 4.2.2 Voltage Ramp and Sequencing Recommendations
- 4.3 DC Specifications
- 4.4 AC Characteristics
- 4.5 Timing Specifications
- 5.0 Package and Pinout Information
- 5.1 Package Information
- 5.2 Thermal Specifications
- 5.3 Pinout Information
82541 Family of Gigabit Ethernet
Networking Silicon - 82541(PI/GI/EI) Datasheet Product Features ■ PCI Bus — PCI revision 2.3, 32-bit, 33/66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands — CLK_RUN# signal — 3.3 V (5 V tolerant PCI signaling) ■ MAC Specific — Low-latency transmit and receive queues — IEEE 802.3x-compliant flow-control support with software-controllable thresholds — Caches up to 64 packet descriptors in a single burst — Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) — Wide, optimized internal data path architecture — 64 KB configurable Transmit and Receive FIFO buffers ■ PHY Specific — Integrated for 10/100/1000 Mb/s full- and half-duplex operation — IEEE 802.3ab Auto-Negotiation and PHY compliance and compatibility — State-of-the-art DSP architecture implements digital adaptive equalization, echo and cross- talk cancellation — Automatic polarity detection — Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds ■ Host Off-Loading — Transmit and receive IP, TCP, and UDP checksum off-loading capabilities — Transmit TCP segmentation and advanced packed filtering — IEEE 802.1Q VLAN tag insertion and stripping and packet filtering for up to 4096 VLAN tags — Jumbo frame support up to 16 KB — Intelligent Interrupt generation (multiple packets per interrupt) ■ Manageability — On-chip SMBus 2.0 port — ASF 1.0 and 2.0 — Compliance with PCI Power Management v1.1/ACPI v2.0 — Wake on LAN* (WoL) support — Smart Power Down mode when no signal is detected on the wire — Power Save mode switches link speed from
1000 Mb/s down to 10 or 100 Mb/s when on
■ Additional Device — Four programmable LED outputs — On-chip power regulator control circuitry — BIOS LAN Disable pin — JTAG (IEEE 1149.1) Test Access Port built in silicon (3.3 V , 5 V tolerant PCI signaling) ■ Lead-freea 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUxxxxxx. a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to th e same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales represen- tative 318138-002 Revision 2.7
Revision History
Aug 2002 0.25 • Initial Release. Sep 2002 0.75 Changed package diagram to molded plastic BGA. Added DC/AC specifications. Corrected pinout information. Oct 2002 1.0 Identified FIFO as 64 KB and verified ballout tables. July 2003 1.5 Added 82547GI coverage. Signals CLKR_CAP and XTAL_CAP changed to RSVD_NC and NC, respectively. Oct 2004 2.0 Added Architecture Overview chapter. Update signal names to match Design Guide and EEPROM Map and Program- ming Application Note. Nov 2004 2.1 Updated lead-free information. Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information. Added statement that no changes to existing soldering processes are needed for the 2-layer 0.32 mm wide-trace substrate change in the section describing “Pack- age Information”. Jan 2005 2.2 Added new maximum values for DC supply voltages on 1.2 V and 1.8 V pins. See Table 2, Recommended Operating Conditions and Table 6, DC Characteristics. Apr 2005 2.3 Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is not used then an external pull-down resistor is required. June 2006 2.4 Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is not used then an external pull-up resistor is required. Aug 2006 2.5 Removed note “b” from Table 2 and note “a” from Tables 3 and 4. Moved the note following Table 5 before Table 3. Aug 2007 2.6 Replace Intel logo, updated the Product Features title page, and document order- ing information. Dec 2007 2.7 Updated Section 3.3. Removed the internal pullup device text from the FLASH Serial Data Output / LAN Disable pin description. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82541 Family of Gigabit Ethernet Controllers may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtain ed from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708- 296-9333 Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries . Copyright © 2007, Intel Corporation. * Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit, without intent to infringe.
82541(PI/GI/EI) — Networking Silicon iv Figures Tables
v Networking Silicon — 82541(PI/GI/EI)
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Networking Silicon — 82541(PI/GI/EI)
1.0 Introduction
The Intel® 82541(PI/GI/EI) Gigabit Ethernet is a single, compact component with an integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop, workstation and mobile PC Network designs with critical space constraints, the Intel® 82541(PI/ GI/EI) allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs. The Intel® 82541(PI/GI/EI) integrates fourth generation gigabit MAC design with fully integrated, physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral Component Interconnect (PCI) 2.3 compliant interface capable of operating at 33 or 66 MHz. The 82541(PI/GI/EI) also incorporates the Clock Run protocol and hardware supported downshift capability to two-pair and three-pair 100 Mbps operation. These features optimize mobile applications. The 82541(PI/GI/EI) on-board System Management Bus (SMB) port enables network manageability implementations required by information technology personnel for remote control and alerting via the Local Area Network (LAN). With SMB, management packets can be routed to or from a management processor. The SMB port enables industry standards, such as Intelligent Platform Management Interface (IPMI) and Alert Standard Forum (ASF) 2.0, to be implemented using the 82541(PI/GI/EI). In addition, on chip ASF 2.0 circuitry provides alerting and remote control capabilities with standardized interfaces. The 82541(PI/GI/EI) Gigabit Ethernet Controller Architecture is designed for high performance and low memory latency. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. The 82541(PI/GI/EI) controller includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that maximizes efficient bus usage. The 82541(PI/GI/EI) uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached on chip. A large 64-KByte onchip packet buffer maintains superior performance as available PCI bandwidth changes. In addition, using hardware acceleration, the controller offloads tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP segmentation. The 82541(PI/GI/EI) is packaged in a 15 mm x 15 mm 196-ball grid array and is pin compatible with the 82551QM 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller, 82562EZ(EX) Platform LAN Connect devices, and the 82540EP(EM) Gigabit Ethernet Controller.
1.1 Document Scope
The 82541EI is the original device and is now being manufactured in a B0 stepping. The 82541GI (B1 stepping) and 82541PI (C0 stepping) are pin compatible, however, a different Intel software driver is required from the 82541EI. This document contains datasheet specifications for the 82541(PI/GI/EI) Gigabit Ethernet Controllers including signal descriptions, DC and AC parameters, packaging data, and pinout information.
82541(PI/GI/EI) — Networking Silicon
1.2 Reference Documents
This document assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information: 82540EP/82541(PI/GI/EI) & 825462EZ(EX) Dual Footprint Design Guide, AP-444. Intel Corporation. 82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map and Programming Information Guide, AP-446. Intel Corporation. PCI Local Bus Specification, Revision 2.3. PCI Special Interest Group (SIG). PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest Group (SIG). IEEE Standard 802.3, 2000 Edition. Incorporates various IEEE standards previously published separately. Institute of Electrical and Electronic Engineers (IEEE). PCI Mobile Design Guide, Revision 1.1. PCI Special Interest Group (SIG). Software driver developers should contact their local Intel representatives for programming information.
1.3 Product Codes
The product ordering codes for the 82541 Family of Gigabit Ethernet Controllers: GD82541PI GD82541GI GD82541EI LU82541PI LU82541GI LU82541EI
2.0 Architectural Overview
2.1 External Architecture Block Diagram
an integrated ASF controller functionality to the MAC. Figure 1. 82541(PI/GI/EI) External Architecture Block Diagram
2.2 Internal MAC Architecture Block Diagram
for reduced-cost basic ASF manageability. Figure 2. Internal Architecture Block Diagram
2.3 Integrated 10/100/1000Mbps PHY
software via MAC control registers, is used to configure and monitor the PHY operation.
2.4 System Interface
eliminates transmit under-runs by buffering the entire outgoing packet prior to transmission.
1000 Mb)
Networking Silicon — 82541(PI/GI/EI)
3.0 Signal Descriptions
3.1 Signal Type Definitions
The signals of the 82541(PI/GI/EI) controller are electrically defined as follows:
3.2 PCI Bus Interface Signals (56)
When the Reset signal (RST#) is asserted, the 82541(PI/GI/EI) will not drive any PCI output or bi- directional pins. The Power Management Event signal (PME#) can be active by configuring manageability functions. Name Definition I Input. Standard input only digital signal. O Output. Standard output only digital signal. TS Tri-state. Bi-directional tri-state digital input/output signal. STS Sustained Tri-state. An active low tri-state signal owned and driven by only one agent at a time. The agent that drives an STS pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving an STS signal any sooner than one clock after the previous owner tri-states it. A pull-up resistor is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. OD Open Drain. Wired-OR with other agents. The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the de-asserted state. A Analog. PHY analog data signal. P Power. Power connection, voltage reference, or other reference connection.
82541(PI/GI/EI) — Networking Silicon
3.2.1 PCI Address, Data and Control Signals (44)
Symbol Type Name and Function AD[31:0] TS Address and Data. Address and data signals are multiplexed on the same PCI pins. A bus transaction includes an address phase followed by one or more data phases. The address phase is the clock cycle when the Frame signal (FRAME#) is asserted low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O, this is a byte address, and for configuration and memory, a DWORD address. The 82541(PI/GI/EI) device uses little endian byte ordering. During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24] contain the most significant byte (MSB). C/BE#[3:0] TS Bus Command and Byte Enables. Bus command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/ BE#[3:0] define the bus command. In the data phase, C/BE#[3:0] are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data. C/BE[0]# applies to byte 0 (LSB) and C/BE#[3] applies to byte 3 (MSB). PAR TS Parity. The Parity signal is issued to implement even parity across AD[31:0] and C/ BE#[3:0]. PAR is stable and valid one clock after the address phase. During data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. When the 82541(PI/GI/EI) controller is a bus master, it drives PAR for address and write data phases, and as a slave device, drives PAR for read data phases. FRAME# STS Cycle Frame. The Frame signal is driven by the 82541(PI/GI/EI) device to indicate the beginning and length of a bus transaction. While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the transaction is in the final data phase. IRDY# STS Initiator Ready. Initiator Ready indicates the abilit y of the 82541(PI/GI/EI) controller (as a bus master device) to complete the current data phase of the transaction. IRDY# is used in conjunction with the Target Ready signal (TRDY#). The data phase is completed on any clock when both IRDY# and TRDY# are asserted. During the write cycle, IRDY# indicates that valid data is present on AD[31:0]. For a read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted toget her. The 82541(PI/GI/EI) controller drives IRDY# when acting as a master and samples it when acting as a slave. TRDY# STS Target Ready. The Target Ready signal indicates the ability of the 82541(PI/GI/EI) controller (as a selected device) to complete the current data phase of the transaction. TRDY# is used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed on any clock when both TRDY# and IRDY# are sampled asserted. During a read cycle, TRDY# indicates that valid data is present on AD[31:0]. For a write cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82541(PI/GI/EI) device drives TRDY# when acting as a slave and samples it when acting as a master. STOP# STS Stop. The Stop signal indicates the current target is requesting the master to stop the current transaction. As a slave, the 82541(PI /GI/EI) controller drives STOP# to request the bus master to stop the transaction. As a master, the 82541(PI/GI/EI) controller receives STOP# from the slave to stop the current transaction.
Networking Silicon — 82541(PI/GI/EI)
3.2.2 Arbitration Signals (2)
3.2.3 Interrupt Signal (1)
3.2.4 System Signals (4)
IDSEL I Initialization Device Select. The Initialization Device Select signal is used by the 82541(PI/GI/EI) as a chip select signal during configuration read and write transactions. DEVSEL# STS Device Select. When the Device Select signal is actively driven by the 82541(PI/GI/ EI), it signals the bus master that it has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. VIO P VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI signaling environment). It is used as the clamping voltage. Note: VIO should be connected to 3.3 V Aux or 5 V Aux in order to be compatible with the pull-up clamps specification. Symbol Type Name and Function REQ# TS Request Bus. The Request Bus signal is used to r equest control of the bus from the arbiter. This signal is point-to-point. GNT# I Grant Bus. The Grant Bus signal notifies the 82541(PI/GI/EI) that bus access has been granted. This is a point-to-point signal. Symbol Type Name and Function INTA# TS Interrupt A. Interrupt A is used to request an interr upt of the 82541(PI/GI/EI). It is an active low, level-triggered interrupt signal. Symbol Type Name and Function CLK I PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus and is an input to the 82541(PI/GI/EI) device. All other PCI signals, except the Interrupt A (INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other timing parameters are defined with respect to this edge. M66EN I 66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz. RST# I PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the Power Management Event signal (PME#), are floated and all input signals are ignored. The PME# context is preserved, depending on power management settings. Most of the internal state of the 82541(PI/GI/EI) is reset on the de-assertion (rising edge) of RST#. CLK_RUN# I/O OD Clock Run. This signal is used by the system to pause the PCI clock signal. It is used by the 82541(PI/GI/EI) controller to re quest the PCI clock. When the CLK_RUN# feature is disabled, leave this pin unconnected. Symbol Type Name and Function
82541(PI/GI/EI) — Networking Silicon
3.2.5 Error Reporting Signals (2)
3.2.6 Power Management Signals (3)
3.2.7 SMB Signals (3)
Note: If the SMB is disconnected, then an external pull-up resistor should be used for these pins. Symbol Type Name and Function SERR# OD System Error. The System Error signal is used by the 82541(PI/GI/EI) controller to report address parity errors. SERR# is open drain and is actively driven for a single PCI clock when reporting the error. PERR# STS Parity Error. The Parity Error signal is used by the 82541(PI/GI/EI) controller to report data parity errors during all PCI transacti ons except by a Special Cycle. PERR# is sustained tri-state and must be driven active by the 82541(PI/GI/EI) controller two data clocks after a data parity error is detected. The minimum duration of PERR# is one clock for each data phase a data parity error is present. Symbol Type Name and Function LAN_ PWR_GOOD I Power Good (Power-on Reset). The LAN_PWR_GOOD signal is used to indicate that stable power is available for the 82541(PI/GI/EI). When the signal is low, the 82541(PI/GI/EI) holds itself in reset state and floats all PCI signals. PME# OD Power Management Event. The 82541(PI/GI/EI) device drives this signal low when it receives a wake-up event and either the PME Enable bit in the Power Management Control/Status Register or the Advanced Power Management Enable (APME) bit of the Wake-up Control Register (WUC) is 1b. AUX_PWR I Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available and the 82541(PI/GI/EI) device should support the D3cold power state. Symbol Type Name and Function SMBCLK TS OD SMB Clock. The SMB Clock signal is an open drain signal for serial SMB interface. SMBDATA TS OD SMB Data. The SMB Data signal is an open drain signal for serial SMB interface. SMB_ALERT#/ LAN_PWR_ GOOD TS OD Multiplexed pin: SMB Alert, LAN Power Good. The SMB_ALERT# signal is open drain for serial SMB interface. The signal acts as an interrupt pin of a slave device on the SMBUS in TCO mode. (82559 mode). In ASF mode, this signal acts as LAN_PWR_GOOD input.
Networking Silicon — 82541(PI/GI/EI)
3.3 EEPROM and Serial FLASH Interface Signals (9)
3.4 Miscellaneous Signals
3.4.1 LED Signals (4)
Symbol Type Name and Function EEMODE I EEPROM Mode. The EEPROM Mode pin is used to select the interface and source of the EEPROM used to initialize the device. For a MIcrowire* EEPROM on the standard EEPROM pins, tie this pin to ground with a 1 K Ω pull-down resistor (for the 82541PI, use a 100 Ω pull-down resistor instead). For an Serial Peripheral Interface (SPI*) EEPROM attached to the Flash memory pins, leave this pin unconnected. EEDI O EEPROM Data Input. The EEPROM Data Input pin is used for output to the memory device. EEDO I EEPROM Data Output. The EEPROM Data Output pin is used for input from the memory device. EEDO includes an internal pull-up resistor. EECS O EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device. EESK O EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the EEPROM interface, which is approximately 1 MHz for Microwire* and 2 MHz for SPI. FLSH_CE# O FLASH Chip Enable Output. Used to enable FLASH device. FLSH_SCK O FLASH Serial Clock Output. The clock rate of the serial FLASH interface is approximately 1 MHz. FLSH_SI O FLASH Serial Data Input. This pin is an output to the memory device. FLSH_SO/ LAN_DISABLE# I FLASH Serial Data Output / LAN Disable. This pin is an input from the FLASH memory. Alternatively, the pin can be used to disable the LAN port from a system GP (General Purpose) port. If the 82541(PI/GI /EI) is not using Flash functionality, the pin should be connected to external pull-up resistor. If this pin is used as LAN_DISABLE#, the device goes to low power state and the LAN port is disabled when the pin is sampled low on rising edge of PCI reset. Symbol Type Name and Function LED0 / LINK_UP# O LED0 / LINK Up. Programmable LED indication. Defaults to indicate link connectivity. LED1 / ACTIVITY# O LED1 / Activity. Programmable LED indication. Defaults to flash to indicate transmit or receive activity. LED2 / LINK100# O LED2 / LINK 100. Programmable LED indication. Defaults to indicate link at 100 Mbps. LED3 / LINK1000# O LED3 / LINK 1000. Programmable LED indication. Defaults to indicate link at 1000 Mbps.
82541(PI/GI/EI) — Networking Silicon
3.4.2 Other Signals (4)
3.5 PHY Signals
3.5.1 Crystal Signals (2)
Note: The 82541 clock input circuit is optimized for use with an external crystal. However, an oscillator may also be used in place of the crystal with the proper design considerations. The 82540EP/ 82541(PI/GI/EI) & 825462EZ(EX) Dual Footprint Design Guide (AP-444) should be consulted for further details.
3.5.2 Analog Signals (10)
Symbol Type Name and Function SDP[3:0] TS Software Defined Pin. The Software Defined Pins are reserved and programmable with respect to input and output capability. These default to input signals upon power- up but may be configured differently by the EEPROM. The upper two bits may be mapped to the General Purpose Interrupt bits if they are configured as input signals. Symbol Type Name and Function XTAL1 I Crystal One. The Crystal One pin is a 25 MHz +/- 30 ppm input signal. It should be connected to a crystal, and the other end of the crystal should be connected to XTAL2. XTAL2 O Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation. Symbol Type Name and Function MDI[0]+/- A Media Dependent Interface [0]. 1000BASE-T: In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X configuration, MDI[0]+/- corresponds to BI_DB+/-. 100BASE_TX: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair. 10BASE-T: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair. MDI[1]+/- A Media Dependent Interface [1]. 1000BASE-T: In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X configuration, MDI[1]+/- corresponds to BI_DA+/-. 100BASE_TX: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair. 10BASE-T: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair. MDI[2]+/- A Media Dependent Interface [2]. 1000BASE-T: In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDI-X configuration, MDI[2]+/- corresponds to BI_DD+/-. 100BASE_TX: Unused. 10BASE-T: Unused.
Networking Silicon — 82541(PI/GI/EI)
3.6 Test Interface Signals (6)
3.7 Power Supply Connections
3.7.1 Digital and Analog Supplies
MDI[3]+/- A Media Dependent Interface [3]. 1000BASE-T: In MDI configuration, MDI[3]+/- corresponds to BI_DC+/-, and in MDI-X configuration, MDI[3]+/- corresponds to BI_DD+/-. 100BASE_TX: Unused. 10BASE-T: Unused. IEEE_TEST- A IEEE test pin output minus. Used to gain access to the internal PHY clock for 1000BASE-T IEEE physical layer conformance testing. IEEE_TEST+ A Analog test pin output plus. Used to gain access to the internal PHY clock for 1000BASE-T IEEE physical layer conformance testing. Symbol Type Name and Function TEST I Test Enable. Enables test mode. Normal mode: connect to VSS. JTAG_TCK I JTAG Test Access Port Clock. JTAG_TDI I JTAG Test Access Port Data In. JTAG_TDO O JTAG Test Access Port Data Out. JTAG_TMS I JTAG Test Access Port Mode Select. JTAG_TRST# I JTAG Test Access Port Reset. This is an active low reset signal for JTAG. To disable the JTAG interface, this signal should be terminated using pull- down resistor (1 KΩ for the 82541GI(EI) and 100 Ω for the 82541PI) to ground. It must not be left unconnected. Symbol Type Name and Function 3.3V P 3.3 V I/O Power Supply. ANALOG_1.8V P 1.8 V Analog Power Supply. CLKR_1.8V P 1.8 V analog power supply for the clock recovery. XTAL_1.8V P Input power for the XTAL regulator. 1.2V P 1.2 V Power supply. For analog and digital circuits. ANALOG_1.2V P 1.2 V Analog Power Supply. PLL_1.2V P Input power for the ICS regulator.
82541(PI/GI/EI) — Networking Silicon
3.7.2 Grounds, Reserved Pins and No Connects
3.7.3 Voltage Regulatio n Control Signals (2)
Symbol Type Name and Function VSS P Ground. AVSS P Shared analog Ground. RSVD_VSS P Reserved Ground. This pin is reserved by Intel and may have factory test functions. For normal operation, connect to ground. RSVD_NC P Reserved No connect. This pin is reserved by Intel and may have factory test functions. For normal operation, do not connec t any circuit to these pins. Do not connect pull-up or pull-down resistors. NC P No Connect. This pin is not connected internally. Symbol Type Name and Function CTRL12 A 1.2 V Control. LDO voltage regulator output to drive external PNP pass transistor. If 1.2 V is already present in the system, leave output unconnected. To achieve optimal D3 power consumption, leave the output unconnected and use a high-efficiency external regulator. CTRL18 A 1.8 V Control. LDO voltage regulator output to drive external PNP pass transistor. If 1.8 V is already present in the system, leave output unconnected. To achieve optimal D3 power consumption, leave the output unconnected and use a high-efficiency external regulator.
4.0 Voltage, Temperature, and Timing Specifications
4.1 Absolute Maximum Ratings
4.2 Targeted Recommended Operating Conditions
4.2.1 General Operating Conditions
Table 1. Absolute Maximum Ratings a exceeded. These values should not be used as the limits for normal device operations. steady state for an indefinite duration. d. The maximum value must also be less than VIO. Table 2. Recommended Operating Conditions (Sheet 1 of 2) a
4.2.2 Voltage Ramp and Sequencing Recommendations
its final value, all voltage rails (1.8 V and 1.2 V) have 150 ms to reach their final operating values. limits, might result in permanent damage. Table 3. 3.3V Supply Voltage Ramp Table 4. 1.8V Supply Voltage Ramp
1 MHz 280 mV
Table 2. Recommended Operating Conditions (Sheet 2 of 2) a
a. Tantalum capacitors must not be used. Table 5. 1.2V Supply Voltage Ramp
1 MHz 180 mV
1 MHz 1V
a. Tantalum capacitors must not be used.
4.3 DC Specifications
Table 6. DC Characteristics Table 7. Power Specifications - D0a
3.3 V 3 mA 5 mA 5 mA 10 mA 13 mA 15 mA 30 mA 40 mA
1.8 V 14 mA 15 mA 85 mA 85 mA 110 mA 115 mA 315 mA 320 mA
1.2 V 30 mA 35 mA 85 mA 90 mA 90 mA 100 mA 380 mA 400 mA
duplex, and PCI 33 MHz system interface.
Table 8. Power Specifications - D3cold
3.3 V 2 mA 3 mA 2 mA 3 mA 2 mA 3 mA 4 mA 5 mA
1.8 V 14 mA 15 mA 20 mA 25 mA 110 mA 115 mA 1 mA 2 mA
1.2 V 21 mA 25 mA 30 mA 35 mA 80 mA 85 mA 7 mA 10 mA
duplex, and PCI 33 MHz system interface. Table 9. Power Specifications D(r) Uninitialized
3.3 V 5 mA 10 mA
1.8 V 1 mA 2 mA
1.2 V 12 mA 15 mA
Table 10. Power Specifications - Complete Subsystem
10 Mbps
100 Mbps
1000 Mbps
3.3 V 4523677 1 2 1 9 2 1 3 6 4 6
1.8 V 1 2 20 25 110 115 85 85 110 115 315 320
1.2 V 7 1 03 03 58 08 58 59 09 0 1 0 0 3 8 0 4 0 0
plex, and PCI 33 MHz system interface. Table 11. I/O Characteristics (Sheet 1 of 2)
3.3 V PCI
4.4 AC Characteristics
b. This is only applicable to the 82541PI. Table 12. AC Characteristics: 3.3 V Interfacing Table 13. 25 MHz Clock Input Requirements Table 11. I/O Characteristics (Sheet 2 of 2) (Continued)
105 clock edges, filtered by HPF with cut off frequency 5000 Hz). Table 14. Reference Crystal Specification Requirements Table 15. Link Interface Clock Requirements a. GTX_CLK is used externally for test purposes only. Table 16. EEPROM Interface Clock Requirements
4.5 Timing Specifications
Figure 3. AC Test Loads for General Output Pins Table 17. PCI Bus Interface Clock Parameters minimum peak-to-peak portion of the clock waveform as shown. noise cannot render a monotonic signal to appear bouncing in the switching range.
- Output timing measurements are as shown.
- REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
- Input timing measurements are as shown.
Figure 4. AC Test Loads for General Output Pins Table 18. PCI Bus Interface Timing Parameters
0.6 Vcc
0.2 Vcc
0.5 Vcc
0.4 Vcc
0.3 Vcc
0.4 Vcc p-to-p
3.3 V Clock
Table 21. EEPROM Link Interface Clock Requirements a. The EEPROM clock is derived from a 125 MHz internal clock. Table 22. EEPROM Link Interface Clock Requirements a. The EEDO setup and hold time is a function of the PCI bus clock cycle time but is referenced to O_EESK.
5.0 Package and Pinout Information
signal mapping is indicated beginning with Table 14.
5.1 Package Information
15 mm. The package dimensions are detailed below. The nominal ball pitch is 1 mm. Figure 11. 82541(PI/GI/EI) Mechanical Specifications Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change.
Figure 12. 196 PBGA Package Pad Detail
5.2 Thermal Specifications
and nominal VCC. The preliminary thermal resistances are shown in Table 13. be used to assure that the 82541(PI/GI/EI) device is operating under recommended conditions. Table 13. Thermal Characteristics
5.3 Pinout Information
Table 14. PCI Address, Data and Control Signals Table 15. PCI Arbitration Signals Table 16. Interrupt Signals Table 17. System Signals
Table 18. Error Reporting Signals Table 19. Power Management Signals Table 20. SMB Signals Table 21. Serial EEPROM Interface Signals Table 22. Serial FLASH Interface Signals Table 23. LED Signals
Table 24. Other Signals Table 25. IEEE Test Signals Table 26. PHY Signals Table 27. Test Interface Signals Table 28. Digital Power Signals (Sheet 1 of 2)
Table 28. Digital Power Signals (Sheet 2 of 2) (Continued) Table 29. Analog Power Signals Table 30. Grounds and No Connect Signals Table 31. Voltage Regulation Control Signals
Table 32. Signal Names in Pin Order (Sheet 1 of 6)
Table 32. Signal Names in Pin Order (Sheet 2 of 6) (Continued)
Table 32. Signal Names in Pin Order (Sheet 3 of 6) (Continued)
Table 32. Signal Names in Pin Order (Sheet 4 of 6) (Continued)
Table 32. Signal Names in Pin Order (Sheet 5 of 6) (Continued)
Table 32. Signal Names in Pin Order (Sheet 6 of 6) (Continued)
5.4 Visual Pin Assignments
Figure 13. Visual Pin Assignments