82530-6

82530 INTEL

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intel. 82530/82530-6 SERIAL COMMUNICATIONS CONTROLLER (SCC) @ Two Independent Full Duplex Serial @ Available in Express Version Channels m Asynchronous Modes @ On Chip Crystal Oscillator, Baud-Rate — 5-8 bit Character; Odd, Even or No Generator and Digital Phase Locked Parity; 1, 1.5 or 2 Stop Bits Loop for Each Channel — Independent Transmit and Receive Clocks. 1X, 16X, 32X or 64X @ Programmable for NRZ, NRZI or FM ’ 2 Programmable Sampling Rate Data Encoding/Decoding — Error Detection: Framing, Overrun @ Diagnostic Local Loopback and and Parity Automatic Echo for Fault Detection and — Break Detection and Generation tsolation @ Bit Synchronous Modes @ System Clock Rates: — SDLC Loop/Non-Loop Operation — 4 MHz for 82530 — CRC-16 or CCITT Generation —6 MHz for 82530-6 . Detection lm Max Bit Rate (6 MHz) — Abort Generation and Detection — Externally Clocked: 1.5 Mbps — Held Residue Handling Self-Clocked: — CCITT X.25 Compatible

375 Kbps FM CODING mw Byte Synchronous Modes

187 Kbps NRZI CODING — Internal or External Character

93 Kbps Asynchronous Synchronization (1 or 2 Characters)

m Interfaces with Any INTEL CPU, DMA or — Automatic CRC Generation and 1/0 Processor Checking (CRC 16 or CCITT) @ Available in 40 Pin DIP and 44 Lead IBM Bisync Compatible PLCC The INTEL 82530 Serial Communications Controller (SCC) is a dual-channel, multi-protocol data communica- tions peripheral. It is designed to interface high speed communications lines using Asynchronous, Byte syn- chronous and Bit synchronous protocols to INTEL's microprocessors based systems. It can be interfaced with Intel's MCS51/96, iAPX86/88/186 and 188 in polled, interrupt driven or DMA driven modes of operation. The SCC is a 40-pin device manufactured using INTEL’s high-performance HMOS II technology. * HMOS is a patented process of intel Corporation. October 1987 2-152 Order Number: 230834-003

Figure 1. 82530 Internal Block Diagram

Figure 2. Pin Configurations The following section describes the pin functions of the SCC. Figure 2 details the pin assignments. Table 1. Pin Description DBo 39 44 vo and commands to and from the SCC. SCC requests an interrupt. It is an open drain output. 7 INTERRUPT ENABLE OUT: IEO is High only if IEl is High and the. interrupts from lower priority devices. interrupt under service or is raquesting an interrupt.

Table 1. Pin Description (Continued) [voc | 9 | 10 | | POWER: +5v Power supply. RDY_—/REQg function, driven High or Low when programmed for a Request function). pins act as outputs and are valid on receipt of a flag. RxDa 13 RECEIVE DATA: Thess lines receive serial data at standard TTL levels. generator, or the transmit clock in the output mode. purpose outputs or as Request lines for a DMA controller.

can be used as general-purpose outputs. transferred; a Low indicates a command. channel in which the read or write operation occurs. bus if the SCC is the highest priority device requesting an interrupt.

intel. 82530/82530-6 GENERAL DESCRIPTION inputs are monitored by the control logic under pro- gram control. All of the modem control signals are The Intel 82350 Serial Communications Controller general-purpose in nature and can optionally be (SCC) is a dual-channel, multi-protocol data commu- _used for functions other than modem control. nications peripheral, The SCC functions as a serial- to-parallel, parallel-to-serial_convertor/controller. The register set for each channel includes ten con- The SCC can be software-configured to satisfy a trol (write) registers, two synchronous character wide range of serial communications applications. _ (write) registers, and four status (read) registers. In The device contains sophisticated internal functions addition, each baud rate generator has two (read/ including on-chip baud rate generators, digital phase write) registers for holding the time constant that de- locked loops, various data encoding and decoding _termines the baud rate. Finally, associated with the schemes, and crystal oscillators that reduce the __ interrupt logic is a write register for the interrupt vec- need for external logic. tor accessible through either channel, a write-only Master Interrupt Control register and three read reg- In addition, diagnostic capabilities—automatic echo _isters; one containing the vector with status informa- and local loopback—allow the user to detect and _ tion (Channel B only), one containing the vector isolate a failure in the network. They greatly improve _ without status (A only), and one containing the Inter- the reliability and fault isolation of the system. rupt Pending bits (A only). 2 | The SCC handles Asynchronous formats, Synchro- The registers for each channel are designated as nous byte-oriented protocols such as IBM Bisync, _ follows: and Synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports © WRO-WR15—Write Registers 0 through 15. virtually any serial data transfer application (Termi- — RRO-RR3, RR10, RR12, AA13, RR15—Read Reg- nal, Personal Computer, Peripherals, Industrial Con-_isters 0 through 3, 10, 12, 13, 15. trolier, Telecommunication sytem, etc.). ___ Table 2 lists the functions assigned to each read or The 82530 can generate and check CRC codes in —_—write register. The SCC contains only one WR2 and any Synchronous mode and can be programmed to —_ WR, but they can be accessed by either channel. check data integrity in various modes. The SCC also lll other registers are paired (one for each channel). has facilities for modem control in both channels. In applications where these controls are not needed, the modem control can be used for general purpose. ~=—s DATA PATH The transmit and receive data path illustrated in Fig- The Intel 82530 is designed to support Intel’s ure 3 is identical for both channels. The receiver has MCS51/96, iAPX 86/88 and iAPX 186/188 families. _three 8-bit buffer registers in a FIFO arrangement, in addition to the 8-bit receive shift register. This scheme creates additional time for the CPU to serv- ARCHITECTURE ice an interrupt at the beginning of a block of high- 1d data. Incoming data is routed through one of The 82590 internal structure includes two fullduplex Sbectar eutne (asta wr CHIC) depending on the se- channels, two baud rate generators, internal control —_ jected mode (the character length in asynchronous and interrupt logic, and a bus interface to a non-mul- modes also determines the data path). tiplexed CPU bus. Associated with each channel are a number of read and write registers for mode con- —_—The transmitter has an 8-bit transmit data buffer reg- ' trol and status information, as well as logic neces- _ister loaded from the internal data bus and a 20-bit sary to interface modems or other external devices. _ transmit shift register that can be loaded either from . the syne-character registers or from the transmit The logic for both channels provides formats, syn- —_data register. Depending on the operational mode, chronization, and validation for data transferred to —_gutgoing data is routed through one of four main and from the channel interface. The modem control___ paths before it is transmitted from the Transmit Data output (TxD). 2-157

intel. 82530/82530-6 . Table 2. Read and Write Register Functions READ REGISTER FUNCTIONS WRITE REGISTER FUNCTIONS RRO Transmit/Receive buffer status and Exter- © WRO CRC initialize, initialization commands for nal status the various modes, shift right/shift left RR1 Special Receive Condition status command RR2 Modified interrupt vect WR1 = Transmit/Receive interrupt and data (Channel B on) vector transfer mode definition Unmodified interrupt WR2 Interrupt vector (accessed through either (Channel A only) channel) RR3_ Interrupt Pending bits WR3 Receive parameters and control (Channel A only) WR4 Transmit/Receive miscellaneous parame- ters and modes RRB Receive buffer , RRO Miscellaneous status WRS5 Transmit parameters and controls , WR6 = Sync characters or SDLC address field R12 Lower byte of baud rate generator time constant WR7 Sync character or SDLC flag RR13 Upper byte of baud rate generator time WR8 Transmit buffer constant WR9 Master interrupt control and reset (ac- R15 External/Status interrupt information cessed through either channel) WR10 Miscellaneous transmitter/receiver control bits WR11 Clock Mode control WR12 Lower Byte of baud rate generator time constant WR13 Upper Byte of baud rate generator time constant WR14 Niscellaneous control bits . WR15_External/Status interrupt control 2-158

1 Hi oar

Figure 3. Data Path

the CPU and provides vectored interrupts and hand- not start. protocol. Figure 4 and the following description brief- begins. put at any time. The receiver break-detection logic for functions such as monitoring a ring indicator. Figure 4. SCC Protocols

allowing character synchronization with a 6-bit or this status change so that an abort may be issued. ‘SYNC pin (an interrupt can also be programmed). checks against the bit pattern 0001110100001111. tion. A special command can be used to abort a modes are available in synchronous modes. flag when the transmitter underruns. The transmitter _ trol to provide high-speed reception or transmission. Figure 5. Detecting 5- or 7-Bit Synchronous Characters

CPU when the first character of a message is re- and easily recognized. normal SOLC. In a loop topology, there is a primary recognizing an EOP). ary station while an SCC operating in regular SDLC_ + SDLC Loop mode. mode can act as a controller (Figure 6). Figure 6. An SDLC Loop both. It can also drive the digital phase-locked loop delay. The secondary station can place its ownmes- — TAXC pin.

Table 3. Time Constant Values for Standard In NRZ encoding, a 1 is represented by a High level sition is 1/0 the bit is a 1. detected, the DPLL makes a count adjustment (dur- _ter interrupts and REA /REQUEST on transmit. NRZI or FM coding of the data stream. The SCC may be programmed to encode and de- 880 Kbps/1.3 Mbps. For self-clocked operation, i.

Figure 7. Data Encoding Methods Table 4. Maximum Bit Rates

4 MHz 45 880 Kbps —_| Serial clocks and system clock

6 MHz 32 187 Kbps

6 MHz 16 375 Kbps

transfer data, status, and control information to and _tents indicate the need for data to be transferred. All interrupts are disabled. Three status registers in _one register. the SCC are automatically updated whenever any .

the vector is read in Channel A, status is never in- _terrupts. tion of the IE bits is straightforward. If the IE bit is set rupted when the transmit buffer becomes empty. The other two bits are related to the interrupt priority Receive condition. quest an interrupt only when no higher-priority de- Receive condition. vice is requesting one, e.g., when IEI is High. If the * Interrupt on Special Receive condition only. er be set. The IP bits are readable in RASA. Figure 8. Daisy Chaining SCC’s

‘SYNC pins; however, an External/Status interrupt is _ allows full-duplex operation under DMA control. (SDLC mode) or EOP (SDLC Loop mode) sequence . to interrupt when the Abort or EOP sequence is de- _figure the functional personality of each channel. initialization of the next message, and the accurate _terrupt information. trollers, The Block Transfer mode uses the READY/ —_—ragisters 0 through 7 as shown on Table 5. ‘ADY line in the CPU Block Transfer mode (WR1; __ ations. Table 5. Register Addressing

Channel A/Channel B selection is made by the A/B read register. within the selected mode. For example, the Asyn- _read from a single register (RR1). ber of stop bits, even or odd parity might be set first. receiver or transmitter enable. Figure 9. Read Register Bit Functions

Figure 9. Read Register Bit Functions (Continued)

[Co] 7 | reser nx crc CHECKER .

18 SPECIAL CONDITION

[1 | 1 _Jrx wrt ON SPECIAL CONDITION ONLY. Figure 10. Write Register Bit Functions

Figure 10. Write Register Bit Functions (Continued)

[eT] Fist our - reansant cLoc.

82530 TIMING volving the SCC to the falling edge of WA or AD in

and RD that are related to CLK. Since CLK has no _the 62530-6.

intel. 82530/82530-6 ABSOLUTE MAXIMUM RATINGS* cations are subject to change without notice. deo cccsseesss0*Cto +70°¢ {WARNING Srossing the device bayond the “Absolute ‘Maximum Ratings” may cause permanent damage. ‘Storage Temperature These are stress ratings only. Operation beyond the Voltage on Any Pin with may affect device reliability. D.C. CHARACTERISTICS Tc = 0°C to 70°C; Voc = +5V +5% [“‘symbor [Parameter [Min [Max [unite | Test Conditions _| [vu | imputtowvotage | -os | +oe | vo [| [vm | inputtighVotage [+24 | Vec+os |v [| [Vo | outputtowvotage | | tous [VT = 20mA_| [Vou | Outputtighvotage | +24 | |v ton = -250nA_| [a | imputtecarage Curent [| 10 | wa | oavtozav | [tor | OutputLeakege Curent [| 10 | wa | oavtozav | [ico] Veesueeiv Curent | [a0 | m |_| CAPACITANCE Tc = 25°C; Voc = GND = OV [symbot [Parameter [| Min [Max | Units | TestConattions _| [cw | _tmputGapactance || to [or | t= tM | [ Cour | OutputCapacitance || ts |r| Unmeasured pins [vo | ImputvOuput Capacitance [| 20 [pr | “otumedtoGND 2-177

intel. 82530/82530-6 A.C CHARACTERISTICS Tc = 0°C to +70°C; Voc = +5V +5% READ AND WRITE TIMING Cd oe ee [+ fice [ouxtowTime | 108 [2000 | 70 | 1000 [ns | | 2 [ron [ouxwigntime [105 | 2000 | 70 [1000 | ns | [| 3 [wv [oukrautime TT a fT 0 | oe | [4 | [erknisotme TT ao [5 [oe | |_s |ty [crkoydetime | 250 [4000 | 165 | 2000 | ns | | 8 [ww [AddosstoWAl sewptime [ao [| o | | ns | |_7 [Wa | AddosstoWRT Holdtime | o [| o || ns | |_e [tr | AddrosstoRDL soup time | ao | fo | | ns | | 9 [tra [AddresstoABT Holdtime [| o [ [oo | | ns | | 10 [uc [WTAwcKt sewptime [ss [fos [| os | [11 [iw [TATA WAL Souptime(woier) [20 [7 [ss [| ns | [12 [om [iTAwWATHoWTme To [To [| ts | | 13 [un [INTAtORDL setup Time note) | 200 [| ss || ns | | 14 [iu [WTAtROT HoWwTime | oo | | oT rs | | 15 [tr |INTAtoGLKT Hodtime | 00 [| too | ns | |_ 16 [tcLw [CStowtoWAl sewptime | o [fo | | ns | [17 [wes [esiowat Hodtim | o [fo [os | | te [icrw [CSHightoWRL Souptime | 100 [| os [| ts | |_ 19 [rcun [CStowtoAOL soup time woe) | o | [ o [| ns | | 20 [trcs | CStoRDT Hodtimo ote | o | [0 | | ns | |_ 21 [1cHR [CStightoRBL sotup Time note) | 100 [| s || ns | |_22 [inn [ROLowTime vores) | 00 || sso | | | 20 [nun [Parameterdeoted | TTT | 24 [enor [ROT todatanotvaidoely | o | fo | ns | |_26 [sndv [ROL todetavaisdetay || a50 [| 105 | rs | [_26 [wr [ROT wouputrioatDelaywore2 | [70 [| 45 | os | 1 Parmeter does not apply to Interrupt Acknowledge transactions. 2.178

Figure 14. Read and Write Timing

intel. 82530/82530-6 INTERRUPT ACKNOWLEDGE TIMING, RESET TIMING, CYCLE TIMING tascam | ase ME! unt teonw|erme| teem | a a Valid Delay | 28 |tww [WRtowtime | goo | | oo | os | | 20 [tow [DatatoWR1 sowptime | oo | | oo [| ns | | 30 [wo [DatatoWAT HolaTime | oo | | oo [| ns | | 31_[twav [WR toReadyvaliddelay (Notes) | | 240. | | 200 | ns | |_a2 [trv [ROL toneadyvaiaDelayinotes) | | 240 | | 200 | ns | |_3¢ [tnt [RD toREADY/REGNotvaid Delay | | 240 | | 200 | ns | | four [wer eomnsprevcowy || ts| | Se] ™ | +300 +250 Se a remem [el eg | +300 +250 I da (Note 5) | 36__|u [RB (Acknowledge) LowTime | aes || 25 [| ns | Hee telat Valid Delay |_40_ [tei [iEito DL (Acknowledge) Soup time] 120 | | 100 | | ns | [41 [ue [ieitoRBT Acknowledge) Hoidtime | o | | o | | ns | | 42 [tio [ieitoieodelaytime || v0 || 100 | ns | | 43 [tea [okt toeodey | aso || 250 | | |_4¢ [ran [ADT toiNT inactive Delay nota) | | s00 | | s00 | ns | |_ 45 [tnw | ROT toWRI Dolaytornoneset | ao | | 15 [| ns | [46 [twa [WAT tAD Delaytornoreset_ | 30 | | 30 | | ns | |_47 [wes | WRandABCoincidentLowtorReset | 260 | | 250 | | ns | I ia Eee) (Note 3) +200 +430 NOTES: 3, Parameter applies only between transactions involving the SCC. 4, Open-drain output, measured with open-drain test load. 5. Parameter is system dependent. For any SCC in the daisy chain, tlID must be greater than the sum of tCEQ for the highest priority device in the daisy chain, tEl for the SCC and tEIEO for each device separating them in the daisy chain. 2-180

intel. 82530/82530-6 GENERAL TIMING perce sme] tee eae [min | Max | win [Max _| |_+ [tree [FACT toGLKT Setup Time Notes 1.4)[ 100 [| 100 [ns | Oa lca (Note 1) =a Mal (Note 1) ON adc (Notes 1, 5) == eee Pele {Notes 1, 5) |_s_[tsrc_|SYNCtoMCT Setup Time Note 1) | -200[ | —200 [ns | CS reser Tey Pst +200 +200 [8 _[trcc [TEI toClkT Setup Time (Notes2,4)| 100 | [100 || ns | |_9 [trot [TC toTxD Delay X1 Mode) Notea | | s00 || 300 | ns | i = (Notes 2, 5) [11 [err |txot0 TAHT Delay (Send Clock Echo) |” [200 | [200 | ns | [12 [ton [RTC higntime | 80 [50 Ts | [19 _froce [RTC Lowtime | t80 [80 Ts | [14 |iwoy [RtCoycetim atv | atcy [Ts | [|_15__[tcLct | Crystal Oscitator Period Notes) | a80_ | 1000 | 165 | 1000 | ns | [16 [tach [TRC righ Time a0 P50 | [a7 [rice [rmCowtime a0 | aso | [12 [wrcy [Tre oycieTime woos | ato [| atcy [| | [19 [roc [eooreTS ruse win | 00 || 200 Ts | [2 [iss [SYNC Pusewith [00 [| 200 Tn | [21 [war [WRioRTSVaiddewy [ewe || acy [ns | [22 [wor |WrioDTAVaiddey || icy | sic [ns | NOTES: 1. Rx is RTxC or TAXC, whichever is supplying the receive clock. 2. TxC is TRxC or ATC, whichever is supplying the transmit clock. 3. Both RTxC and SYNC have 30 pF capacitors to ground connected to them. 4, Parameter applies only if the data rate is one-fourth the system clock (CLK) rate. In all other cases, no phase relationship between RxC and CLK or TxC and CLK is required. 5. Parameter applies only to FM encoding/decoding. 6. Only applies to transmitter and receiver. For DPLL and Baud Rate Generator Timings, the requirements are identical to system clock, CLK, specifications. 2-182

Figure 18. General Timing