82344

82344 INTEL

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i t \\ ADVANCE INFORMATION The 82344 ISA Bus Controller replaces several of the LS! controllers used in PC/AT*-type designs with one single 160-pin quad flatpack. The Bus Controller provides the functions of DMA, page address register, timer, interrupt control, Port B logic, slot bus refresh address generation, and real time clock. The Bus Controller directly drives the refresh addresses onto the AT slot address bus during refresh cycles in response to a refresh cycle command from the System Controller. To avoid problems with sensitive slot bus add-in cards, the Bus Controller features “bus quiet’ mode. When no valid slot bus accesses are occurring, the SA bus and control lines do not change states. Rather, they retain their previous logic state. Built-in sleep mode features work together with System Controller sleep features to provide a low power system idle state for extension of battery life in portable systems. When activated by the CPU via !/O write to an internal indexed configuration register, the DMA sybsystem clock is stopped and the AT slot bus remains in BUS QUIET state, The SYSCLK can be individually controlled. The interrupt controllers and the timers contin- ue to operate. If an interrupt occurs due to an external source or any of the timers, the Bus Controller “wakes up” and in turn wakes the System Controller. Block Diagram BES #, BEO # SAO #, SBHE # IOCHROY DATA CONVERSION ATE XDREAD #, SDSWAP#, ROME # SDHL/LH #, LATLO #, LATHI # CHM /I0 #, 264, 266 syseu ‘oneness BNE STORY CONTROL MEMR #, MEMW #, ‘SMEMR #, SMEMW 4 XD7=XD9 DACK7 #, DACKS #, CHM /10#, DACK3 #, DACKO # POWERGOOD DMAHRQ, NMi, ARO1S~IROS,IROT PERIPHERAL INTR, OUT1 BAT, PS, RTCOSC CONTROL REFRESH # DuaDA ‘—_ | wn 7 WARs-LAt7 ADDRESS eseonnt BLKA20 # Re ——> (240843-1 386 is a trademark of Intel Corporation. *PC/AT is a registered trademark of International Business Machines Corporation. ett 1-24 Order Number: 240843-001

intel noses ADVANCE INFORMATION The upgraded DMA channels provide a superset of reduce bus ringing. A —ROM8 pin selects the bus AT functionality by allowing DMA to the entire 64 and bus size to use for BIOS ROM accesses. The Mbyte memory range of the 82340DxX chip set. Addi- choices are 8- or 16-bit wide ROMs. tional functionality is provided via DMA wait state, clock, and —MEMR timing programmability. A three-state test control pin has been added for board level testability. A—HIDRAIVE pin can be externally strapped to pro- vide for 12 mA or 24 mA drive to the slot bus. If eft The Bus Controller features several megacells, im- open, an internal pull-up causes the drive current to plemented in 1.5-micron CMOS technology, and is default to 24 mA. This allows systems designed with intended to work in 386™ SX or 386™ DX micro- ‘one to four slots to select a lower drive level and processor-based systems with CPU clock speeds up to 33 MHz and bus speeds up to 16 MHz. PERIPHERAL CONTROL BLOCK DIAGRAM | wr oy roy ca g.uouw - Bord : TST HOorX0y x ‘pRo6-Drob,clx bo, Rais Dg-O7 AswAis) wor2]s [Hee J on wom Phcxoy = otcee - : - Bekes one pm gusewe, O50, neser eum me % port 60 | Ki GRg6=R08, ctx Do, wore 1 Dg=07 Asm Ars} onoo-pr0s | WuDA onos-os07 ue J0g=D7. AvemAzs Forr 8 Lose Ssciag ‘oom Ghee ousses 4 ‘ rex Pc meres meats XTALIN Times: CHIP aout wc) nn ontess | Steer 208 for [I] Port 8 cs. vat once ard 2408452 1-25

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intel 82344 ADVANCE INFORMATION SIGNAL DESCRIPTIONS [nome [are] te | tom A25, A24 43-44 | O-TS | Address Bus—These pins are outputs during DMA, master, or standard refresh modes. They are high impedance at all other times, A25 and A24 are driven from the alternate 612 registers during DMA and refresh cycles and are driven low during master cycles. 45-58, | IO-TTL | Address Bus—These pins are outputs during OMA, master, or 61-68 standard refresh modes. They are inputs at all other times. As 1 inputs, they are passed to the SA and LA buses and A15~A2 are used to address I/O registers internal to the bus control chip. As outputs, they are driven from different sources depending on which mode the Bus Controller is in. While in refresh mode, these pins are driven from the 612 and refresh address counter. While in DMA mode, they are driven from the 612 and DMA controller subsection. If the Bus Controller is in master mode, the pins A23- ‘A17 are driven from the inputs LA23-LA17 and the pins A16-A2 are driven from the inputs SA16-SA2. 69 10-TTL | Byte Enable 3, active low—This pin is an output during DMA, master, or standard refresh modes. itis an input at all other times. As an input in 386DX mode, it is decoded along with the other byte enable signals to generate SA1, SAO and —SBHE. As an output in 3860X mode SA1, SAO, and —SBHE are used to determine the value of —BE3. This pin should be left unconnected when using this part in 286 mode. The pin has an internal pull-up. —BE2/A1 70 10-TTL | Byte Enable 2, active low, or Ai—This pin has a dual function depending on the state of the 286/-386Dx input. If 286/-386DX is high (286 mode), then the pin is treated as address bit 1. If 286/ ~386DxX is low (386DX mode), the pin is treated as —BE2. This pin is an output during DMA, master, or standard refresh modes. Itis an input at all other times. As an input in 386DX mode, itis decoded along with the other byte enable signals to generate SA1, SAO, and —SBHE. As an output in 386DX mode. SA1, SAO, and —SBHE are used to determine the value of —BE2. When in 286 mode, itis interpreted as address A1 and passed to SA1. As an output in 286 mode it is driven from the SA1 input. —BE1/—BHE n 10-TTL | Byte Enable 1 or Byte High Enable, active low—This pin has a dual function depending on the state of the 286/—386DX input. If 286/—386DX is high (286 mode), then the pins treated as —BHE. If 286/—386 is low (386 mode), the pin is treated as —BE1. This pin is an output during DMA, master, or standard refresh modes. Itis an input at all other times. As an input in 386 mode, it is decoded along with the other byte enable signals to generate SA1, SAO, and —SBHE. As an output in 386 mode, SA1, SAO, and —SBHE are used to determine the value of —BE1. When in 286 mode, it is interpreted as —BHE and passed to —SBHE. As an output in 286 mode, it is driven from the — ‘SBHE input. 1-27

intel 82344 ADVANCE INFORMATION SIGNAL DESCRIPTIONS (Continued) (eile te) ome —BEO/AO 72 | 10-TTL | Byte Enable 0, active low, or AO—This pin has a dual function depending on the state of the 286/—386DX input. If 286/—386DX is high (286 mode), then the pin is treated as address bit 0. if 286/—386DX is low (386 mode), the pin is treated as —BEO. This pin is an output during DMA, master, or standard refresh modes. It is an input at all other times. As an input in 386 mode, it is decoded along with the other Byte Enable signals to generate SA1, SAO, and —SBHE. As an output in 386 mode, SA1, SAO, and —SBHE are used to determine the value of —BEO. When in 286 mode, itis interpreted as AO and passed to SAO. As an output in 286 mode, itis driven from the SAO input. 286/—386Dx | 73 F-TPU | CPU is 286 or 386DX—This pin defines the type of address bus to which the bus controller chip is interfaced. If the pin is tied high, the address bus is assumed to be emulating 286 signals. In this mode, A25, A24, and —BE3 would be left unconnected. The pins —BE2/A1, —BE1/—BHE and —BEO/AO would take on the 286 functions. If the pins tied low, A25, A24 can be used to generate up to 64 Mbyte addressing for DMA, and the byte enable pins will take on the normal 386DX addressing functions. This pin has an internal pull-up to cause the chip to default to 286 mode if left unconnected. This pin is a hard wiring option and must not be changed dynamically during operation. When strapped for 286 mode, the Bus Controller is assumed to be interfaced to the

82343 System Controller which in turn may be strapped for 286 or

386SX operation. The 82344 is strapped for 286 operation when used with the 82843 strapped for 386SX operation HLDA 74 LTTL | Hold Acknowledge—This is the hold acknowledge pin directly from the CPU. It is used to control direction on address and command pins. When HLDA is low, the Bus Controller is defined as being in the CPU mode. In the CPU mode, the local address bus (A bus) pins are inputs. The system address bus (SA and LA) pins along with the command pins (—MEMR, —MEMW, —IOR and —IOW) are outputs. When HLDA is high, the Bus Controller can be in DMA, refresh, or master modes. In both DMA and retresh modes, the commands and all address buses (A, SA and LA) are outputs. In master mode, the commands and system address bus (SA and LA) pins are inputs and the local address bus (A bus) pins are outputs. The SA bus is passed directly to the Abus except bits 17, 18, and 19 are ignored. LA23-LA17 is passed directly to A23-A17. INTR 75 Interrupt Request—INTR is used to interrupt the CPU and is generated by the 8259 megacells any time a valid interrupt request input is received.

76 Non-Maskable Interrupt—This output is used to drive the NMI

input to the CPU. This signal is asserted by either a parity error (indicated by —PCK being asserted after the ENPARCK bit in Port B has been asserted), or an I/O channel error (indicated by —IOCHCK being asserted after the ENIOCK bit in Port B has been asserted). The NMI output is enabled by writing a 0 to bit D7 of 1/0 port 70h. NMI is disabled on reset. 1-28

intel 92344 ADVANCE INFORMATION a SIGNAL DESCRIPTIONS (Continued) Sw atle | SYSTEM CONTROLLER INTERFACE —cHso/—Mw | 77 | 10-TTL | Channel Status 0 or active low Memory Write—This input is used along with —CHSt and CHM/—IO to determine what type of bus cycle the Bus Controller is to perform. This input has the same meaning and timing requirements as the SO signal for a 286 microprocessor. —CHSO going active indicates a write cycle unless —CHS1 is also active. When both status inputs are active itindicates an interrupt acknowledge cycle. This input is synchronized to the BUSCLK input. Activation of CPUHLDA reverses this signal to become an output to the System Controller. Itis then a —MEMW signal for DMA or bus master access to system memory. —CHS1/—MR 78 | 10-TTL | Channel Status 1 or active low Memory Read—This input is used along with —CHSO and CHM/—iO to determine the bus cycle type. This input has the same meaning and timing requirements as the S1 signal for a 286 microprocessor —CHS1 going active indicates a read cycle unless —CHS0 is also active. When both status inputs are active it indicates an interrupt acknowledge cycle. This input is synchronized to the BUSCLK input. Activation of CPUHLDA reverses this signal to become an output to the System Controller. It is then a —MEMR signal for DMA or bus master access to system memory. CHM/—IO L-TTL | Channel Memory or active low 1/0 select—This input is used along with —CHSO and —CHS to determine the bus cycle type. This input has the same meaning and timing requirements as the M/—IO signal for a 286 microprocessor. CHM/—IO is sampled anytime —CHSO or —CHS'1 is active. If sampled high, it indicates a memory read or write cycle. If sampled low, an 1/0 read or write cycle should be executed. This input is synchronized to the BUSCLK input —EALE ETTL | Early Address Latch Enable, active low—This input is used to latch the A25-A2 and Byte Enable signals. The latches are open when —EALE is low and hold their value when —EALE is high. The latched addresses are fed directly to the LA23-LA17 bus to provide more address setup time on the bus before a command goes active. The lower latched addresses are latched again with an internal ALE signal as soon as —CHSO or —CHS1 is sampled active and fed to the SA19-SAO and —SBHE outputs. In a 386DX system, this input is connected directly to the —ADS output from the CPU. In a 286 system, this input is connected to the —EALE output from the 82343 System Controller. —BRDRAM ETTL | On-board DRAM, active low—An input from the System Controller indicating that the on-board DRAM is being addressed. 1-29

intel azsaa ADVANGE INFORMATION SIGNAL DESCRIPTIONS (Continued) SYSTEM CONTROLLER INTERFACE (Continued) —CHREADY Channel Ready, active low—This output is maintained in the active state when no bus accesses are active. This indicates that the Bus Controller is ready to accept a new command. During normal bus accesses, —CHREADY is negated as soon as a valid bus requested is sampled on the —CHSO and —CHS1 inputs. Itis asserted again to indicate that the Bus Controller is ready to complete the current cycle. The bus command signals are then terminated on the next falling edge of the BUSCLK input. BUSCLK 1-CMOS | Bus Clock—This is the main clock input for the Bus Controller. It runs at twice the frequency desired for the SYSCLK output. All inputs are synchronous with the falling edge of this input. —BLKA20 87 LTTE Block A20, active low—This input is used while CPUHLDA is low to force the LA20 and SA20 outputs low anytime it is active. When —BLKA20 is negated LA20 and SA20 are generated from A20. DMAHRQ 89 Hold Request—This output is generated by the DMA controller any time a valid DMA request is received. It is connected to the DMAHRQ pin on the System Controller. DMAHLDA -TTL DMA Hold Acknowledge—An input from the System Controller which indicates that the current hold acknowledge state is for the DMA controller or other bus master. OuT1 Output 1—Indicates a refresh request to the System Controller. This is the 15 4s output of timer channel 1. —ROM8 1-TPU 8/16 bit ROM select—This input indicates the width of the ROM BIOS. If —-ROM8 is low, the Bus Controller chip generates 8- to 16-bit conversions for ROM accesses. Data buffer controls are generated assuming the ROM is on the MD bus. If —ROM8 is high, data buffer controls are generated assuming 16-bit wide ROMs are on the MD bus. BUS INTERFACE —OR 10-TTL | I/O Read, active low—This signal is an input when CPUHLDA is high and —MASTER is low. It is an output at all other times. When CPUHLDA is low, —IOR is driven from the 288 bus controller megacell. When CPUHLDA is high and —MASTER is high, it is driven by the 8237 DMA controller megacells. This pin requires an external 10 KM. pull-up resistor. ow 1O-TTL | 1/0 Write, active low—This signal is an input when CPUHLDA is high and —MASTER is low. It is an output at all other times. When CPUHLDA is low, —lOW is driven from the 288 bus controller megacell. When CPUHLDA is high and —MASTER is high, it is driven by the 8237 DMA controller megacells. This pin requires an external 10 K9. pull-up resistor. 1-30

intel e220 «= «ADVANCE INFORMATION ee SIGNAL DESCRIPTIONS (Continued) ieee || | —MEMR 1O-TTL | Memory Read, active low—This signal is an input when CPUHLDA is high and —-MASTER is low. It is an output at all other times. When CPUHLDA is low, —MEMR is driven from the 288 bus controller megacell. When CPUHLDA is high and —MASTER is high, it is driven by the 8237 DMA controller megacells. This signal does not pulse low for DMA addresses above 16 Mbytes. DMA above 16 Mbytes is only performed to. the system board, never to the slot bus. This pin requires an 1 external 10 K®? pull-up resistor. 10-TTL | Memory Write, active low—This signal is an input when CPUHLDA is high and —MASTER is low. It is an output at all other times. When CPUHLDA is low, —MEMW is driven from ‘the 288 bus controller megacell. When CPUHLDA is high and —MASTER is high, it is driven by the 8237 DMA controller megacells. This pin requires an external 10 K pull-up resistor. 10-TTL | Memory Read, active low—This signal is an input when CPUHLDA is high and —MASTER is low. It is an output at all other times. When CPUHLDA is low, —MEMR is driven from the 288 bus controller megacell. When CPUHLDA is high and —MASTER is high, it is driven by the 8237 DMA controller megacells. —SMEMR is active on memory read cycles to addresses below 1 Mbyte. This pin requires an external 10 Ko pull-up resistor. —SMEMW 127 10-TTL | Memory Write, active low—This signal is an input when (CPUHLDA is high and —MASTER is low. It is an output at alt other times. When CPUHLDA is low, —MEMW is driven from the 288 bus controller megacell. When CPUHLDA is high and —MASTER is high, it is driven by the 8237 DMA controller megacells. —SMEMW is active on memory write cycles to addresses below 1 Mbyte. This pin requires an external 10 Ko pull-up resistor. LA23-LA17 | 16, 18, 22,24, | IO-TTL | Latchable Address bus—This bus in an input when CPUHLDA 26, 28, 31 is high and —MASTER is low. It is an output bus at all other times. When CPUHLDA is low, the LA bus is driven by the latched values for the A bus. When CPUHLDA is high and —MASTER is high, the SA bus is driven by the 612 memory mapper for DMA cycles and normal refresh. The LA bus is latched internally with the —EALE input. SA19-SAO 191, 133, 135, | 1O-TTL | System Address bus—This bus is an input when CPUHLDA is 437, 141, 143, high and —MASTER is low. It is an output bus at all other 145, 147,149, times. When CPUHLDA is low, the SA bus is driven by the 152. 154, 156, latched values from the A bus. When CPUHLDA is high and 158, 1,3, 5,7, —MASTER is high, the SA bus is driven by the 8237 OMA 8 1 1 2 , controller megacells or refresh address generator. The SA ee bus will become valid in the middle of the status cycle generated by the —CHS0 and —CHS1 inputs. They are latched with an internally generated ALE signal. 1-31

intel 2344 ADVANCE INFORMATION SIGNAL DESCRIPTIONS (Continued) [name | ater | | Detention | BUS INTERFACE (Continued) —SBHE 10-TTL | System Byte High Enable, active low—This pin is controlled the ‘same way as the SA bus. It is generated from a decode of the —BE inputs in CPU made. It is forced low for 16-bit DMA cycles and forced to the opposite value of SAO for 8-bit DMA cycles. —REFRESH 146 'T-OD | Refresh signal, active low—This |/O signal is pulled low whenever a decoupled refresh command is received from the System Controller. It is used as an input to sense refresh requests from external sources such as the System Controller for coupled refesh cycles or bus masters. It is used internally to clock the refresh address counter and select a location in the memory mapper which drives A23-A17. —REFRESH is an open drain output capable of sinking 24 mA and requires an external pull-up resistor. SYSCLK ‘System Clock—This output is half the frequency of the BUSCLK input. The bus contro! outputs BALE and the —IOR, —IOW, —MEMR and —MEMW are synchronized to SYSCLK. osc -TTL Oscillator—This is the buffered input of the external 14.318 MHz oscillator. RSTDRV Reset Drive, active high—This output is a system reset generated from the POWERGOOD input. RSTDRV is synchronized to the BUSCLK input. BALE Buffered Address Latch Enable, active high—A pulse which is generated at the beginning of any bus cycle initiated from the CPU. BALE is forced high anytime CPUHLDA is high. AEN Address Enable—This output goes high anytime the inputs. CPUHLDA and —MASTER are both high. are 4 Terminal Count—This output indicates that one of the DMA channels termina count has been reached. This signal directly drives the system bus. —DACK7- 39, 37, DMA Acknowledge, active low—These outputs are the —DACKS, 34, 136, acknowledge signals for the corresponding DMA requests. The —DACK3- 2, 142, active polarity of these lines is set active low on reset. Since the —DACKO 29 8237 megacells are internally cascaded together, the polarity of the —DACK signals must not be changed. This signal directly drives the system bus. DRQ7-DRQS 41, 38, |-TSPU | DMA Request—These asynchronous inputs are used by an DRQ3-DRQO | 36, 138, external device to indicate when they need service from the 124, internal DMA controllers. DRQO-DRQ3 are used for transfers 144, 32 from 8-bit |/O adapters to/from system memory. DRQ5-DRQ7 are used for transfers from 16-bit I/O adapters to/from system memory. DRQ4 is not available externally as it is used to cascade the two DMA controllers together. All DRQ pins have internal pull- ups. 1:32

intel 82344 ADVANCE INFORMATION ee SIGNAL DESCRIPTIONS (Continued) [name [eer | te | Bermton BUS INTERFACE (Continued) IRQ15-IRQ9, | 25,27, | -TPSU | Internal Request—These are the asynchronous interrupt 1RQ7-IRQ3, 110, 23, request inputs for the 8259 megacells. IRQO, IRQ2, and |ROS IRat 21,17, are not available as external inputs to the chip, but are used 123, 151, internally. 1RQO is connected to the output of the 8254 counter 153, 155, 0. IRQ2 is used to cascade the two 8259 megacells together. 157, 159, IRQB is output from the RTC megacell to the 8259 megacell. All 109 IRQ input pins are active high and have internal pull-ups. { —MASTER L-TTL | Master, active low—This input is used by an external device to disable the internal DMA controllers and get access to the system bus. When asserted it indicates that an external bus master has control of the bus. —MEMCS16 13 I-TTL | Memory Chip Select 16-bit—This input is used to determine when a 16-bit to 8-bit conversion is needed for CPU accesses. ‘16 to 8 conversion is done anytime the System Controller requests a 16-bit memory cycle and —MEMCS'16 is sampled high. —I0CS16 TTL 1/0 Chip Select 16-bit—This input is used to determine when a 16-bit to B-bit conversion is needed for CPU accesses. A 16 to 8 conversion is done anytime the System Controller requests a 16-bit I/O cycle and —IOCS16 is sampled high. —IOCHK 421 t-ttL_ | 1/0 Channel Check, active low—This input is used to indicate that an error has taken place on the I/O bus. If I/O checking is, enabled, an —IOCHK assertion by a peripheral device generates an NMI to the processor. The state of the IOCHK signal is read as data bit D6 of the Port B register. IOCHRDY L-TTL | 1/0 Channel Ready—This input is pulled low in order to extend the read or write cycles of any bus access when required. The cycle can be initiated by the CPU, DMA controllers or refresh controller. The default number of wait states for cycles intiated by the CPU are four wait states for 8-bit peripherals, one wait state for 16-bit peripherals and three wait states for ROM cycles. One DMA wait state is inserted as the default for all DMA cycles. Any peripheral that cannot present read data, or strobe-in write data in this amount of time must use —IOCHRDY to extend these cycles. —Wwso 125 L-TTL | Wait State 0, active low—This input is pulled low by a peripheral on the S bus to terminate a CPU controlled bus cycle earlier than the default values defined internally on the chip. POWERGOOD | 115 | F-TSPU | System power on reset—This input signals that power to the board is stable. A Schmitt-trigger input is used. This allows the input to be connected directly to an RC network, PERIPHERAL INTERFACE —Cs8042 108 Chip select for 8042. This output is active any time an SA address is decoded at 60h or 64h. It is intended to be connected to the chip select of the keyboard controller. If BUSCTL[6] = 1, this pin is also active for RTC accesses at 70h and 7th, This is for use when the internal RTC is disabled and an external RTC is used. 1-33

intel 82344 ADVANCE INFORMATION SIGNAL DESCRIPTIONS (Continued) [name | liter | 9° | Description PERIPHERAL INTERFACE (Continued) XTALIN 1-CMOS. | Crystal Input—An internal oscillator input for the real time clock crystal. It requires a 32.768 KHz external crystal or stand-alone osciltator. XTALOUT 419 Crystal Output—An internal oscillator output for the real time clock crystal. See XTALIN. This pin is ano connect when an external oscillator is used. Ps/—RcLR/ | 117 | L-TSPU | The Power Sense input (active high) is used to reset the status of IRQS the Valid RAM and Time (VRT) bit. This bit is used to indicate that the power has failed, and that the contents of the RTC may not be valid. This pin is connected to an external RC network. When BUSCTLI6] = 1, this pin becomes —IRQ8 input for use with an external RTC. VBAT Voltage Battery—Connected to the RTC hold-up battery between 2.4 and 5V. 107 Speaker—This output drives an externally buffered speaker. This signal is created by gating the output of timer 2. Bit 1 of Port B, 61H, is used to enable the speaker output, and bit 0 is used to gate the output timer. DATA BUFFER INTERFACE XD7-XD0 91,92, | IO-TTL | Peripheral data bus—The bidirectional X data bus outputs data on 94-99 an INTA cycle or 1/0 read cycle to any valid address within the . Bus Controller. It is configured as an input at all other times. —SDSWAP System Data Swap, active low during some 8-bit accesses—It indicates that the data on the SD bus rhust be swapped from low byte to high byte or vice versa depending on the state of the SDLH/—HL pin. -SDSWAP is active for 8-bit DMA cycles when an odd address access occurs for data more than one byte wide. For non-DMA accesses. —SDSWAP is active for any bus cycle to an 8-bit peripheral that is addressing the odd byte. SDLH/—HL System Data Low to High, or High to Low—This signal is used to determine which direction data bytes must be swapped when —SDSWAP is active. When SDLH/—HL is high, it indicates that data on the low byte must be transferred to the high byte. When SDLH/—HL is low, it indicates that data on the high byte must be transferred to the low byte, SDLH/—HL is low for 8-bit DMA memory read cycles. For non-DMA accesses, SDLH/—HL is low for any memory write or I/O write when —SBHE is low. SDLH/—HL is high at all other times. —XDREAD Peripheral Data Read—This output is active low any time an INTA cycle occurs or an I/O read occurs to the address space from 0000h to OOF Fh, which is defined as being resident on the peripheral bus. 4-34

intel 82344 ADVANCE INFORMATION a SIGNAL DESCRIPTIONS (Continued) DATA BUFFER INTERFACE (Continued) —LATLO 104 Latch Low byte—This output is generated for all 1/0 read and memory read bus accesses to the low byte. It is active with the same timing as the read command and returns high at the same time as the read command. This signal latches the data into the data butfer chip so that it can be presented to the CPU at a later time. This step is required due to the asynchronous interface between the System Controller and Bus Controller. { —LATHI Latch High byte—This output is generated for all I/O read and memory read bus accesses to the high byte. itis active with the same timing as the read command and returns high at the same time as the read command. This signal latches the data into the data buffer chip 0 that it can be presented to the CPU at a later time. This step is required due to the asynchronous interface between the System Controller and Bus Controller. —PCK 1 1-TPU | Party Check input, active low with pull-up—indicates that a parity error has occurred in the on-board memory array. Assertion of this signal (if enabled) generates an NMI to the processor. The state of the —PCK signal is read as data bit D7 of the Port B register. —HIDRIVE | 113 | /-TPU | High Drive Enable—This pin is a wire strap option. When this input is low, all bus drivers defined with an IOL spec of 24 mA will sink the full 24 mA of current. When this input is high, all pins defined as 24 mA have the output low drive capability cut in half to 12 mA. Note that all ‘AC specifications are done with the outputs in the high drive mode and a 200 pF capacitive load —HIDRIVE has an internal pull-up and can be left unconnected if 12 mA drive is desired. Its tied low if 24 mA drive is desired. —TRI E-TPU | Three-state—This pin is used to control the three-state drive of all ‘outputs and bidirectional pins on the chip. If this pin is pulled low, all pins on the chip except XTALOUT are in a high impedance mode. This is useful during system test when test equipment or other chips drive the signals or for hardware fault tolerant applications. —TRI has an internal pull-up. POWER AND GROUND PINS The power connections are split into an internal supply for the core-logic, and a pad-ring supply for the 1/0 drivers. Each supply should be individually bypassed wih decoupling capacitors. VODR 19, 59, Pad-ring power connection, nominally +5V. These pins along with 100, 139 the VSSR pins should be separately bypassed. VSSR 10, 20, Pad-ring ground connection, nominally OV. These pins along with the 30, 40, DDR pins should be separately bypassed. 60, 80, 93, 106, 120, 130, 140, 150, 160 voDI 79 Internal core-logic power connection, nominally + SV. This pin along with the VSSI pin should be separately bypassed. vssi GND | Internal core-logic ground connection, nominally OV. This pin along with the VDDI pin should be separately bypassed. 1-35

intel azsaa ADVANCE INFORMATION Signal Type Legend [0-00 | tnputor pen Drain, Siow Tun On| Lo moana TTL Level Compatible Output | [tT taputusedtor Testing Purposes | aS a 1-36