N80C251TB24 INTEL
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 36
Technical content
Datasheet sections
- 1.0 INTRODUCTION
- 2.0 NOMENCLATURE
- 3.0 PINOUT
- 4.0 SIGNALS
- 5.0 ADDRESS MAP
- 6.0 ELECTRICAL CHARACTERISTICS
- 6.2 Definition of AC Symbols
- 6.3.1 External Bus Cycles, Nonpage Mode
- 6.3.2 External Bus Cycles, Page Mode
- 6.3.3 Definition of Real-Time Wait Symbols
- 6.3.4 External Bus Cycles, Real-Time Wait States
- 6.5 External Clock Drive
- 7.0 THERMAL CHARACTERISTICS
Datasheet sections
© INTEL CORPORATION December 2003 Order Number: 273129-002 8xC251TB/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Commercial/Express ■ Real-time and Programmed Wait State Bus Operation ■ Binary-code Compatible with MCS® 51 ■ Pin Compatible with 44-pin PLCC and 40-pin PDIP MCS 51 Sockets ■ Register-based MCS® 251 Architecture — 40-byte Register File — Registers Accessible as Bytes, Words, or Double Words ■ Enriched MCS 51 Instruction Set — 16-bit and 32-bit Arithmetic and Logic Instructions — Compare and Conditional Jump Instructions — Expanded Set of Move Instructions ■ Linear Addressing ■ 256-Kbyte Expanded External Code/Data Memory Space ■ ROM Options:
16 Kbytes or without ROM
■ 16-bit Internal Code Fetch ■ 64-Kbyte Extended Stack Space ■ On-chip Data RAM Options: 512-Byte ■ 8-bit, 2-clock External Code Fetch in Page Mode ■ Fast MCS 251 Instruction Pipeline ■ User-selectable Configurations: — External Wait States (0-3 wait states) — Address Range & Memory Mapping — Page Mode — Extended Data Float Timings or 8xC251Sx Compatible AC Timings ■ 32 Programmable I/O Lines ■ Eight Maskable Interrupt Sources with Four Programmable Priority Levels ■ Three Flexible 16-bit Timer/counters ■ Hardware Watchdog Timer ■ Programmable Counter Array — High-speed Output — Compare/Capture Operation — Pulse Width Modulator — Watchdog Timer ■ Two Programmable Serial I/O Ports — Framing Error Detection — Automatic Address Recognition ■ High-performance CHMOS Technology ■ Static Standby to 24-MHz Operation ■ Complete System Development Support — Compatible with Existing Tools — MCS 251 Tools Available: Compiler, Assembler, Debugger, ICE ■ Package Options (PDIP and PLCC)
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 8xC251TB/TQ may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver CO 80217-9808 or call 1-800-548-4725. Many documents are available for download from Intel’s website at http://www.intel.com. Copyright © Intel Corporation 1997, 2003. *Third party brands and names are the property of their respective owners.
REVISION HISTORY: Date Revision Description November 1997 001 Initial release of this document December 2003 002 Removed references to 8XC251TA, 8XC251TP
512 Bytes
1024 Bytes
8 Kbytes
16 Kbytes
1.0 INTRODUCTION
Figure 1. 8xC251TB/TQ Block Diagram
2.0 NOMENCLATURE
Figure 2. The 8xC251TB/TQ Family Nomenclature Table 1. Description of Product Nomenclature without Intel standard burn-in.
3 ROM
Ta bl e 2 lists the proliferation options. See Figure 2 for the 8xC251TB/TQ family nomenclature. Ta bl e lists the 8xC251TB/TQ package definitions. Table 2. Proliferation Options Table 3. Package Information
3.0 PINOUT
Figure 3. 8xC251TB/TQ 44-pin PLCC Package
Figure 4. 8xC251TB/TQ 40-pin PDIP Packages
Table 4. 8xC251TB/TQ Pin Assignment
1 VSS1 23 V SS2
12 VCC2 34 V SS2
Table 5. 8xC251TB/TQ PLCC/DIP Pin Assignments Arranged by Functional Category
4.0 SIGNALS
Table 6. Signal Descriptions (Sheet 1 of 3) and RD1 in configuration byte UCONFIG0. See also RD# and PSEN#. compare mode and PCA PWM mode. ration byte UCONFIG0 (see RD#).
bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN#). capacitor between this pin and VCC . the chip to normal operation. and receives data in serial I/O modes 1, 2, and 3. a falling edge on the T1:0 pin increments the count. mode, this signal determines the count direction: 1 = up, 0 = down. and transmits serial data in serial I/O modes 1, 2, and 3. Table 6. Signal Descriptions (Sheet 2 of 3)
(WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H. period of one-half the oscillator frequency. clock source for internal timing. external oscillator is used, leave XTAL2 unconnected. address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0). Table 7. Memory Signal Selections (RD1:0) Table 6. Signal Descriptions (Sheet 3 of 3)
5.0 ADDRESS MAP
Table 8. 8xC251TB/TQ Address Map reserved for the configuration array. 16Kbytes FF:0000H - FF:3FFFH). access on-chip code memory in region FF: (16 Kbyte devices only).
- 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
- The special function registers (SFRs) and the register file have separate internal address spaces.
- Data in this area is accessible by indirect addressing only.
- Devices reset into internal or external starting locations depending on the state of EA# and configuration byte information
- The 16-Kbyte ROM devices allow internal locations FF:2000H–FF:3FFFH to map into region 00:. In this case, if EA# = 1,
- This reserved area returns indeterminate values.
- Data is accessible by direct and indirect addressing.
- Data is accessible by direct, indirect, and bit addressing.
- Data is accessible by direct, indirect, and register addressing.
6.0 ELECTRICAL CHARACTERISTICS
Parameter values apply to all devices unless otherwise indicated. permanent damage. These are stress ratings only. Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Sheet 1 of 2)
- Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
greater than the listed test conditions.
- Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and
exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
- Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address
Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed. Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Sheet 2 of 2)
Test Conditions: Capacitive load on all pins = 50 pF. affected by a PSEN#/RD#/WR# wait state. Table 10. AC Timing Symbol Definitions Figure 6 through Figure 8 show the bus cycles with the timing parameters. Table 11. AC Characteristics (Sheet 1 of 4)
Table 11. AC Characteristics (Sheet 2 of 4)
34.7 TOSC -7
Table 11. AC Characteristics (Sheet 3 of 4)
- Specifications for PSEN# are identical to those for RD#.
- In the formula, M = number of wait states (0 or 1) for ALE and N = Number of wait states (0,1,2 or 3) for
- Device configured with the default data float timing for fast memory interface (EDF# = 1).
- Device configured with extended data float timing for slow memory interface (EDF# = 0).
Table 11. AC Characteristics (Sheet 4 of 4)
6.3.1 External Bus Cycles, Nonpage Mode
Figure 5. External Bus Cycle: Code Fetch (Nonpage Mode) † The value of this parameter depends on wait states. See the table of AC characteristics.
† The value of this parameter depends on wait states. See the table of AC characteristics. Figure 6. External Bus Cycle: Data Read (Nonpage Mode)
Figure 7. External Bus Cycle: Data Write (Nonpage Mode) † The value of this parameter depends on wait states. See the table of AC characteristics.
6.3.2 External Bus Cycles, Page Mode
Figure 8. External Bus Cycle: Code Fetch (Page Mode) † The value of this parameter depends on wait states. See the table of AC characteristics. state (2TOSC ); a page miss requires two states (4TOSC ). ††† During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
Figure 9. External Bus Cycle: Data Read (Page Mode) † The value of this parameter depends on wait states. See the table of AC characteristics.
Figure 10. External Bus Cycle: Data Write (Page Mode) † The value of this parameter depends on wait states. See the table of AC characteristics.
6.3.3 Definition of Real-Time Wait Symbols
6.3.4 External Bus Cycles, Real-Time Wait States
Figure 11. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode) Table 12. Real-time Wait Timing Symbol Definitions
Figure 12. External Bus Cycle: Data Write (Nonpage Mode)
Figure 13. External Bus Cycle: Code Fetch/Data Read (Page Mode)
Figure 14. External Bus Cycle: Data Write (Page Mode) Table 13. Real-Time Wait AC Timing
- W = 0, 1, 2 — is the number of real time wait states.
- Device configured with the extended data float timing.
6.4 AC Characteristics — Serial Port, Shift Register Mode
Figure 15. Serial Port Waveform — Shift Register Mode Table 14. Serial Port Timing — Shift Register Mode †TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
6.5 External Clock Drive
Figure 16. External Clock Drive Waveforms Figure 17. AC Testing Input, Output Waveforms Table 15. External Clock Drive
0.7 VCC
a min of VIH for a logic 1 and VOL for a logic 0.
Figure 18. Float Waveforms
7.0 THERMAL CHARACTERISTICS
thermal impedance test methodology. Table 16. Thermal Characteristics