7540

7540_M RENESAS

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RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER

740 FAMILY / 740 SERIES

7540 Group8

Rev. 2.00 Revision date: Jun 21, 2004 User's Manual www.renesas.com Before using this material, please visit our website to confirm that this is the most current document available. REJ09B0018-0200Z

Keep safety first in your circuit designs! Notes regarding these materials 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, pro- grams, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con- tact Renesas Technology Corp. or an authorized Renesas Technology Corp. product dis- tributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by vari- ous means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liabil- ity or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or repro- duce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be im- ported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

REVISION HISTORY

Rev. Date Description Page Summary

7540 Group User’s Manual

1.00 Sep. 17, 2002

1.10 May 28, 2003

[Pull-up control register] PULL; Note added. Fig.15; Note 2 eliminated. Fig.17; (2) Ports P0 1,P02 revised. Fig.29; Port P03 direction register block, Port P01 direction register block and Port P02 direction register block revised. (3) RC oscillation revised. Fig.2.4.12; RTI → RTS Fig.2.4.16; Prescaler X 1/4 → 1/2, CNTR0 pin output 4 MHz → 4 kHz Fig.2.4.17; The second CPUM setting 00000X002 → 11000X002 Prescaler X 0316 → 0116, Note 2 revised. Fig.2.4.26; The followings are revised. The second setting of CNTR 0 interrupt enable bit and Timer X interrupt enable bit. The second setting of timer X mode register. Fig.3.3.5; NOP added. 1-17 1-19 1-34 1-45 2-49 2-52 2-53 2-61 3-86 2.00 Jun. 21, 2004 Words standardized: On-chip oscillator, A/D converter Fig. 8: “Under development” eliminated. Table 2: “Under development” eliminated. CPU: Description revised. [Pull-up control register] PULL: Note added Fig.17 (2) Ports P0 1, P02 revised. Fig. 29 P03/TXOUT , P01/TYOUT , P02/TZOUT revised. Note on A/D converter added. Fig. 49 revised. Note on A/D converter added. Notes on clock generating circuit: On-chip oscillator operation added. Note on Power Source Voltage, and Electrical Characteristic Difference Among Mask ROM and One Time PROM Version MCUs added. Fig.2.1.6: Note 2 eliminated. Fig.2.2.3: Note 2 eliminated. 2.2.7 Notes on timer A, (2): Register name revised. Fig.2.3.2: Description revised. Fig.2.5.7: Description revised. 2.8.4 Notes on A/D converter: (3) added. 2.9.6 Notes on oscillation stop detection circuit, (1): ➁ added. 3.3.10 Notes on A/D converter: (3) added. 3.3.11 Notes on oscillation stop detection circuit, (1): ➁ added. 3.3.19 Note on Power Source Voltage and 3.3.20 Electrical Characteristic Differ- ence Among Mask ROM and One Time PROM Version MCUs added. All pages 1-9 1-10 1-11 1-17 1-19 1-34 1-42 1-45 1-51 1-52 2-5 2-14 2-35 2-36 2-66 2-134 2-145 3-82 3-83 3-91 (1/2)

Rev. Date Description Page Summary Fig.3.5.5: Note 2 eliminated. Fig.3.5.15: Description revised. Fig.3.5.19: Description revised. 32P6U-A revised. Fig.3.11.1: Memory address of 7531 Group revised. 3-100 3-106 3-108 3-120 3-140 2.00 Jun. 21, 2004 (2/2)

This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. You must refer to that chapter. 1. Organization G CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. G CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. G CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the list of registers. 2. Structure of register The figure of each register structure describes its functions, contents at reset, and attributes as follows : only and read and write. In the figure, these attributes are represented as follows : : Bit in which nothing is arranged 0 1 : Name Function At resetRWB 0 ✕ b0b1b2b3b4b5b6b7 Contents immediately after reset release Bit attributes (Note 1) Processor mode bits Stack page selection bit Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are “0.” Fix this bit to “0.” Main clock (XIN-XOUT ) stop bit Internal system clock selection bit 0 0 : Single-chip mode 1 0 : 1 1 : Not available b1 b0 0 : 0 page 1 : 1 page 0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN -XCOUT selected : Bit that is not used for control of the corresponding function Note 1:. Contents immediately after reset release (Note 2) CPU mode register (CPUM) [Address : 3B16] Bits 3. Supplementation For details of software, refer to the “740 FAMILY SOFTWARE MANUAL.” For development tools, refer to the “Renesas Technology tool Index for 740 Family.” Homepage (http:/ /www.renesas.com/eng/products/mpumcu/toolhp/mcu/740_e.htm).

i

7540 Group

I Electric Characteristic Differences Among Mask ROM and One Time PROM Version MCUs ....1-52

Fig. 21 Connection example when using key input interrupt and port P0 block diagram 1-23

v

Fig. 3.1.3 Switching characteristics measurement circuit diagram (Extended operating temperature)3-20 Fig. 3.1.5 Switching characteristics measurement circuit diagram (Extended operating temperature Fig. 3.2.6 VCC -ICC characteristics (addition when operating A/D conversion, f(XIN) = 8 MHz in Fig. 3.2.7 VCC -ICC characteristics (addition when operating A/D conversion, f(XIN) = 6 MHz in Fig. 3.2.8VCC -ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation Fig. 3.2.9 VCC -ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction Fig. 3.2.14 Ta-ICC characteristics (When system is operating by on-chip oscillator, Ceramic Fig. 3.2.15 Ta-ICC characteristics (When system is operating by on-chip oscillator, at WIT

Fig. 3.2.28 VOL -IOL characteristics of N-channel (VCC = 3.0 V, LED drive port: Mask ROM version) Fig. 3.2.29 VOL -IOL characteristics of N-channel (VCC = 5.0 V, LED drive port: Mask ROM version) Fig. 3.2.30 VCC -IIL characteristics (Port “L” input current when connecting pull-up transistor: Fig. 3.2.31 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 8 Fig. 3.2.32 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 6 Fig. 3.2.33 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 4 Fig. 3.2.49 VCC -ICC characteristics (addition when operating A/D conversion, f(XIN) = 8 MHz in Fig. 3.2.50 VCC -ICC characteristics (addition when operating A/D conversion, f(XIN) = 6 MHz in Fig. 3.2.51 VCC -ICC characteristics (When system is operating by on-chip oscillator, Ceramic Fig. 3.2.52 VCC -ICC characteristics (When system is operating by on-chip oscillator, at WIT Fig. 3.2.57 Ta-ICC characteristics (When system is operating by on-chip oscillator, Ceramic

x List of figures Fig. 3.2.58 Ta-ICC characteristics (When system is operating by on-chip oscillator, at WIT Fig. 3.2.67 VOH -IOH characteristics of P-channel (VCC = 3.0 V, normal port: One Time PROM Fig. 3.2.68 VOH -IOH characteristics of P-channel (VCC = 5.0 V, normal port: One Time PROM Fig. 3.2.69 VOL -IOL characteristics of N-channel (VCC = 3.0 V, normal port: One Time PROM Fig. 3.2.70 VOL -IOL characteristics of N-channel (VCC = 5.0 V, normal port: One Time PROM Fig. 3.2.71 VOL -IOL characteristics of N-channel (VCC = 3.0 V, LED drive port: One Time PROM Fig. 3.2.72 VOL -IOL characteristics of N-channel (VCC = 5.0 V, LED drive port: One Time PROM Fig. 3.2.73 VCC -IIL characteristics (Port “L” input current when connecting pull-up transistor: Fig. 3.2.74 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 8 Fig. 3.2.75 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 6 Fig. 3.2.76 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 4 Fig. 3.2.79 R-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) 3-67 Fig. 3.2.80 C-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) 3-67 Fig. 3.2.82 Ta-f(XIN) characteristics (RC oscillation frequency: One Time PROM version)3-68

Table 2.6.1 Setting example of baud rate generator (BRG) and transfer bit rate values .. 2-112 CHAPTER 3 APPENDIX

DESCRIPTION

FEATURES

DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD FUNCTIONAL DESCRIPTION SUPPLEMENT

Rev.2.00 Jun 21, 2004 HARDWARE The 7540 Group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 7540 Group has a serial I/O, 8-bit timers, a 16-bit timer, and an A/D converter, and is useful for control of home electric appli- ances and office automation equipment. (at 6 MHz oscillation frequency, double-speed mode for the shortest instruction) (low-power dissipation by an on-chip oscillator enabled) (connect to external ceramic resonator or quartz-crystal oscilla- tor permitting RC oscillation)

• Power source voltage XIN oscillation frequency at ceramic oscillation, in double-speed mode XIN oscillation frequency at ceramic oscillation, in high-speed mode X IN oscillation frequency at RC oscillation in high-speed mode or middle-speed mode
• Power dissipation (–40 to 85 °C for extended operating temperature version) (–40 to 125 °C for extended operating temperature 125 °C ver- sion (Note 2)) APPLICATION Office automation equipment, factory automation equipment, home electric appliances, consumer electronics, car, etc. Notes 1: Serial I/O2 can be used in the following cases; (1) Serial I/O1 is not used, (2) Serial I/O1 is used as UART and BRG output divided by 16 is selected as the synchronized clock. 2: In this version, the operating temperature range and total time are limited as follows; 55 °C to 85 °C: within total 6000 hours, 85 °C to 125 °C: within total 1000 hours. DESCRIPTION/FEATURES/APPLICATION

Rev.2.00 Jun 21, 2004 Fig. 2 Pin configuration (36P2R-A type) Package type: 36P2R-A P00/CNTR 1 CNV SS XOUT XIN VSS P01/TYOUT P02/TZOUT P03/TXOUT P04 P30(LED0) Vcc VREF P05 P10/RXD 1 P26/AN6 P27/AN7 P11/TXD 1P12/SCLK1 /SCLK2 P13/SRDY1 /SDATA2 P23/AN3 P22/AN2 P21/AN1 P20/AN0 P31(LED1) P36(LED6)/INT1 P24/AN4 P25/AN5 P06 P07 P37/INT0 RESET M37540Mx-XXXFPM37540MxT-XXXFPM37540MxV-XXXFPM37540E8FPM37540E8T-XXXFPM37540E8V-XXXFP P14/CNTR 0 P35(LED5) P34(LED4) P33(LED3) P32(LED2) PIN CONFIGURATION (TOP VIEW) Fig. 1 Pin configuration (32P6U-A type) Package type: 32P6U-A P07 P10/RXD 1 P11/TXD 1 P12/SCLK1 /SCLK2 P13/SRDY1 /SDATA2 P14/CNTR 0 P20/AN 0 P21/AN 1 32 P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) VSS XOUT XIN9 2 876531 4 V CC CNV SS RESETP2 2/AN 20 1718192124 2/TZ OUT 3/TX OUT 23 22 1/TY OUT 0/CNTR 7/INT M37540Mx-XXXGP M37540MxT-XXXGP M37540MxV-XXXGP M37540ExGP M37540E8T-XXXGP M37540E8V-XXXGP 3/AN 4/AN 5/AN V REF PIN CONFIGURATION

Rev.2.00 Jun 21, 2004 HARDWARE Fig. 4 Pin configuration (42S1M type) Outline 42S1M P00/CNTR 1 CNV SS XOUT XIN VSS P01/TYOUT P02/TZOUT P03/TXOUT P04 P30(LED0) Vcc VREF P05 P12/SCLK1 /SCLK2 P25/AN5 P26/AN6 P13/SRDY1 /SDATA2P14/CNTR 0 NC P22/AN2 NC P21/AN1 P20/AN0 P31(LED1) P36(LED6)/INT1 P23/AN3 P24/AN4 P06 P07 P37/INT0 RESET M37540RSS NC P35(LED5) P34(LED4) P33(LED3) P32(LED2) NC P10/RXD 1 P11/TXD 1 NC NC P27/AN7 Fig. 3 Pin configuration (32P4B-A type) CNV SS P12/SCLK1 /SCLK2 P13/SRDY1 /SDATA2 P14/CNTR 0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 VCC XIN XOUT VSS P11/TXD 1 P10/RXD 1 P07 P06 P05 P04 P30(LED0) P25/AN5 VREF RESET P00/CNTR 1 P33(LED3) P32(LED2) P31(LED1) M37540Mx-XXXSPM37540ExSP P01/TYOUT P02/TZOUT P03/TXOUT P37/INT0 P34(LED4) Package type: 32P4B PIN CONFIGURATION

Rev.2.00 Jun 21, 2004 Fig. 5 Functional block diagram (32P6U package) FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U) X IN OU T X SI/O1(8) RAM ROM CPU A X Y S PC H PC L PS V SS 11 RESET V CC 8 CNV SS P1(5) 30 28 P2(6) P3(6) 15 13 Reset input I/O port P2 I/O port P1 I/O port P3 Clock generating circuit Clock input Clock output A/D converter (10) V REF Watchdog timer Reset INT SI/O2(8) CNTR I/O port P0 Prescaler Y (8)Prescaler Z (8) Timer X (8) Timer Z (8)Timer Y (8) Key-on wakeup TY OUT TZ OUT Prescaler X (8) CNTR Timer A (16) P0(8) 23 21 20 18 INT Timer 1 (8) Prescaler 1 (8) TX OUT

Rev.2.00 Jun 21, 2004 HARDWARE

7540 Group FUNCTIONAL BLOCK

Fig. 6 Functional block diagram (36P2R package) FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R) A/D converter (10) X IN OUT X CPU V SS 18 RESET V CC 15 CNV SS P0(8) 32 30 29 27 P1(5) P2(8) P3(8) 23 21 19 I/O port P2 I/O port P0 I/O port P1 I/O port P3 16 17 26 24 SI/O1(8) RAM ROM A X Y S PC H PC L PS Reset input Clock generating circuit Clock input Clock output V REF Watchdog timer Reset INT SI/O2(8) CNTR Prescaler Y (8)Prescaler Z (8) Timer X (8) Timer Z (8)Timer Y (8) Key-on wakeup TY OUT TZ OUT Prescaler X (8) CNTR Timer A (16) INT Timer 1 (8) Prescaler 1 (8) TX OUT INT

Rev.2.00 Jun 21, 2004 Fig. 7 Functional block diagram (32P4B package) FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B) P1(5) P2(6) P3(6) 20 18 P0(8) 28 26 25 23 A/D converter (10) X IN OUT X CPU V SS RESET V CC CNV SS I/O port P2 I/O port P0 I/O port P1 I/O port P3 SI/O1(8) RAM ROM A X Y S PC H PC L PS Reset input Clock generating circuit Clock input Clock output V REF Watchdog timer Reset INT SI/O2(8) CNTR Prescaler Y (8)Prescaler Z (8) Timer X (8)Timer Z (8)Timer Y (8) Key-on wakeup TY OUT TZ OUT Prescaler X (8) CNTR Timer A (16) INT Timer 1 (8) Prescaler 1 (8) TX OUT

Rev.2.00 Jun 21, 2004 HARDWARE

• Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss.
• Reference voltage input pin for A/D converter
• Chip operating mode control pin, which is always connected to Vss.
• Reset input pin for active “L”
• Input and output pins for main clock generating circuit
• Connect a ceramic resonator or quartz crystal oscillator between the X IN and XOUT pins.
• For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• When the on-chip oscillator is selected as the main clock, connect XIN pin to VSS and leave XOUT open. Function expect a port functionName Power source (Note 1) Analog reference voltage CNVss Reset input Clock input I/O port P0 I/O port P1 Pin Vcc, Vss V REF CNVss RESET X IN P00/CNTR 1 P01/TYOUT P02/TZOUT P03/TXOUT P04–P07 Notes 1: VCC = 2.4 to 5.5 V for the extended operating temperature version and the extended operating temperature 125 °C version. 2: P26/AN6 and P27/AN7 do not exist for the 32-pin version, so that Port P2 is a 6-bit I/O port. 3: P35 and P36/INT1 do not exist for the 32-pin version, so that Port P3 is a 6-bit I/O port.
• Key-input (key-on wake up interrupt input) pins
• Timer Y, timer Z, timer X and timer A function pin
• 8-bit I/O port.
• I/O direction register allows each pin to be individually pro- grammed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Whether a built-in pull-up resistor is to be used or not can be de- termined by program.
• 5-bit I/O port
• I/O direction register allows each pin to be individually pro- grammed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• CMOS/TTL level can be switched for P1 0, P12 and P13
• 8-bit I/O port having almost the same function as P0
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit I/O port 0/RxD1 P11/TxD1 P12/SCLK1 /SCLK2 P13/SRDY1 /SDATA2 P14/CNTR 0 P20/AN0–P27/AN7 P30–P3 5 P36/INT1 P37/INT0 I/O port P2 (Note 2) I/O port P3 (Note 3)
• Serial I/O1 function pin
• Serial I/O1 function pin
• Serial I/O2 function pin
• Timer X function pin
• Input pins for A/D converter
• Interrupt input pins
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37).
• CMOS 3-state output structure
• P3 0 to P36 can output a large current for driving LED. XOUT Clock output
• Whether a built-in pull-up resistor is to be used or not can be de- termined by program. PIN DESCRIPTION

Rev.2.00 Jun 21, 2004 We plan to expand the 7540 group as follow: Memory type Support for Mask ROM version, One Time PROM version, and Emulator MCU . Memory size Package Fig. 8 Memory expansion plan 3 8 4 3 2 K R O M s i z e b y t e s R A M s i z e b y t e s )512 7 6 8 1 6 K M 3 7 5 4 0 E 8 M37540M4 M37540M4T M 3 7 5 4 0 E 8 T M 3 7 5 4 0 E 8 V M37540M2T M37540M2 M 3 7 5 4 0 E 2 M37540M2V M 3 7 5 4 0 M 4 V GROUP EXPANSION

Rev.2.00 Jun 21, 2004 HARDWARE Currently supported products are listed below. Table 2 List of supported products Part Number (P) ROM size (bytes) ROM size for User () 8192 (8062) 16384 (16254) 8192 (8062) 32768 (32638) RAM size (bytes) 384 512 384 768 768 Package 32P4B 36P2R-A 32P6U-A 32P4B 36P2R-A 32P6U-A 32P4B 36P2R-A 32P6U-A 32P4B 36P2R-A 32P6U-A 42S1M Remarks Mask ROM version Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 °C version) Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 °C version) Mask ROM version Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 °C version) Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 °C version) One Time PROM version (blank) One Time PROM version (blank) One Time PROM version (blank) One Time PROM version (blank) One Time PROM version (blank) One Time PROM version (shipped after programming, extended operating temperature version) One Time PROM version (shipped after programming, extended operating temperature 125 °C version) One Time PROM version (blank) One Time PROM version (shipped after programming, extended operating temperature version) One Time PROM version (shipped after programming, extended operating temperature 125 °C version) Emulator MCU M37540M2-XXXSP M37540M2-XXXFP M37540M2T-XXXFP M37540M2V-XXXFP M37540M2-XXXGP M37540M2T-XXXGP M37540M2V-XXXGP M37540M4-XXXSP M37540M4-XXXFP M37540M4T-XXXFP M37540M4V-XXXFP M37540M4-XXXGP M37540M4T-XXXGP M37540M4V-XXXGP M37540E2SP M37540E2FP M37540E2GP M37540E8SP M37540E8FP M37540E8T-XXXFP M37540E8V-XXXFP M37540E8GP M37540E8T-XXXGP M37540E8V-XXXGP M37540RSS GROUP EXPANSION

Rev.2.00 Jun 21, 2004 X b7 b0 S b7 b0 Y b7 b0 PC L Processor Status Register (PS) Carry Flag b7 b0 b7 b0 A b15 PC H Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Program Counter Stack Pointer Index Register Y Index Register X Accumulator CZIDBTVN FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The MCU uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL for details on each instruction set. Machine-resident 740 family instructions are as follows: 1. The FST and SLW instructions cannot be used. 2. The MUL and DIV instructions can be used. 3. The WIT instruction can be used. 4. The STP instruction can be used. (This instruction cannot be used while an on-chip oscillator is operating.) Accumulator (A) The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. Index register X (X), Index register Y (Y) Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to “1”, the value contained in index register X becomes the address for the second OPERAND. Stack pointer (S) The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack ad- dress are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is “0”, then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is “1”, then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcom- puter types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing reg- ister contents onto the stack and popping them from the stack are shown in Fig. 10. Program counter (PC) The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PCL. It is used to indicate the address of the next instruction to be executed. Fig. 9 740 Family CPU register structure

Rev.2.00 Jun 21, 2004 HARDWARE

7540 Group FUNCTIONAL DESCRIPTION

M (S) (PCH ) (S) (S – 1) M (S) (PCL) Execute RTS (PCL) M (S) (S) (S – 1) (S) (S + 1) (S) (S + 1) (PCH ) M (S) Subroutine Restore Return Address Store Return Address on Stack M (S) (PS) Execute RTI (PS) M (S) (S) (S – 1) (S) (S + 1) Interrupt Service Routine Restore Contents of Processor Status Register M (S) (PCH ) (S) (S – 1) M (S) (PCL) (S) (S – 1) (PCL) M (S) (S) (S + 1) (S) (S + 1) (PCH ) M (S) Restore Return Address I Flag “0” to “1” Fetch the Jump Vector Store Return Address on Stack Store Contents of Processor Status Register on Stack Interrupt request (Note) Note : The condition to enable the interrupt Interrupt enable bit is “1” Interrupt disable flag is “0” Table 3 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 10 Register push and pop at interrupt generation and subroutine call

Rev.2.00 Jun 21, 2004 Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to “1”, but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. When an interrupt occurs, this flag is automatically set to “1” to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are ex- ecuted in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was gener- ated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to gener- ate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed be- tween accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is “1”, direct arithmetic operations and direct data trans- fers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory lo- cation 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal ad- dressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location oper- ated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 4 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag I flag SEI CLI D flag SED CLD B flag T flag SET CLT V flag CLV N flag

Rev.2.00 Jun 21, 2004 HARDWARE [CPU mode register] CPUM The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16. Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of program af- ter releasing Reset in the following method. Fig. 12 Switching method of CPU mode register Fig. 11 Structure of CPU mode register O s c i l l a t i o n m o d e s e l e c t i o n b i t N o t e C e r a m i c o s c i l l a t i o n R C o s c i l l a t i o n C P U m o d e r e g i s t e r C P U M a d d r e s s i n i t i a l v a l u e S t a c k p a g e s e l e c t i o n b i t p a g e p a g e C l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b b f (φ) f XI N ) H i g h s p e e d m o d e f (φ) f XI N ) M i d d l e s p e e d m o d e a p p l i e d f r o m o n c h i p o s c i l l a t o r f (φ) f XI N ) D o u b l e s p e e d m o d e N o t e O n c h i p o s c i l l a t o r o s c i l l a t i o n c o n t r o l b i t O n c h i p o s c i l l a t o r o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r o s c i l l a t i o n s t o p XI N o s c i l l a t i o n c o n t r o l b i t C e r a m i c o r R C o s c i l l a t i o n e n a b l e d C e r a m i c o r R C o s c i l l a t i o n s t o p P r o c e s s o r m o d e b i t s N o t e b b S i n g l e c h i p m o d e N o t a v a i l a b l e b 7 b 0 2 : T h e s e b i t s a r e u s e d o n l y w h e n a c e r a m i c o s c i l l a t i o n i s s e l e c t e d . Note 1: The bit can be rewritten only once after releasing reset. After rewriting i t i s d i s a b l e t o w r i t e a n y d a t a t o t h e b i t . H o w e v e r , b y r e s e t t h e b i t i s i n i t i a l i z e d a n d c a n b e r e w r i t t e n a g a i n I t i s n o t d i s a b l e t o w r i t e a n y d a t a t o t h e b i t f o r e m u l a t o r M C U M R S S D o n o t u s e t h e s e w h e n a n R C o s c i l l a t i o n i s s e l e c t e d . After releasing reset Switch the oscillation mode selection bit (bit 5 of CPUM) Switch the clock division ratio selection bits (bits 6 and 7 of CPUM) Main routine Start with an on-chip oscillator An initial value is set as a ceramic oscillation mode. When it is switched to an RC oscillation, its oscillation starts. Select 1/1, 1/2, 1/8 or on-chip oscillator. Wait by on-chip oscillator operation until establishment of oscillator clock When using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. When using an RC oscillation, wait time is not required basically (time to execute the instruction to switch from an on-chip oscillator meets the requirement).

Rev.2.00 Jun 21, 2004 Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. Zero page The 256 bytes from addresses 0000 16 to 00FF16 are called the zero page area. The internal RAM and the special function regis- ters (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF00 16 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Ac- cess to this area with only 2 bytes is possible in the special page addressing mode. Fig. 13 Memory map diagram 010016 000016 004016 044016 FF0016 FFDC 16 FFFE 16 FFFF 16 3 8 4 XXXX 16 0 1 B F1 8 1 9 2 E00016 C000 16 800016 E 0 8 01 C Y Y Y Y1 ZZZZ 16 RAM ROM R e s e r v e d a r e a S F R a r e a Not used I n t e r r u p t v e c t o r a r e a R O M a r e a Reserved ROM area (128 bytes) Z e r o p a g e Special page R A M a r e a R A M c a p a c i t y b y t e s address XXXX 16 R O M c a p a c i t y b y t e s a d d r e s s Y Y Y Reserved ROM area a d d r e s s Z Z Z

Rev.2.00 Jun 21, 2004 HARDWARE Fig. 14 Memory map of special function register (SFR) Note : Do not access to the SFR area including nothing. 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Pull-up control register (PULL) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Port P1P3 control register (P1P3C) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 Timer count source set register (TCSS) A/D conversion register (low-order) (ADL) Prescaler 1 (PRE1) Timer 1 (T1) One-shot start register (ONS) Timer X mode register (TXM) Prescaler X (PREX) Timer X (TX) Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2) A/D control register (ADCON) A/D conversion register (high-order) (ADH) MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt control register 1 (ICON1) Timer A mode register (TAM) Timer A (low-order) (TAL) Timer A (high-order) (TAH) Timer Y, Z mode register (TYZM) Prescaler Y (PREY) Timer Y secondary (TYS) Timer Y primary (TYP) Timer Y, Z waveform output control register (PUM) Prescaler Z (PREZ) Timer Z secondary (TZS) Timer Z primary (TZP) Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2)

Rev.2.00 Jun 21, 2004 [Direction registers] PiD The I/O ports have direction registers which determine the input/ output direction of each pin. Each bit in a direction register corre- sponds to one pin, and each pin can be set to be input or output. When “1” is set to the bit corresponding to a pin, this pin becomes an output port. When “0” is set to the bit, the pin becomes an in- put port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are float- ing, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating. [Pull-up control register] PULL By setting the pull-up control register (address 0016 16), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control. Note: P2 6/AN6 , P27/AN7, P35 and P36 do not exist for the 32-pin version. Accordingly, the following settings are required;

• Set direction registers of ports P2 6 and P27 to output.
• Set direction registers of ports P35 and P36 to output. [Port P1P3 control register] P1P3C By setting the port P1P3 control register (address 0017 16), a CMOS input level or a TTL input level can be selected for ports 0, P12, P13, P36, and P37 by program. Fig. 16 Structure of port P1P3 control register Fig. 15 Structure of pull-up control register Port P1P3 control register (P1P3C: address 001716, initial value: 0016) b7 b0 P37/INT0 input level selection bit 0 : CMOS level 1 : TTL level 6/INT1 input level selection bit 0 : CMOS level 1 : TTL level 0,P12,P13 input level selection bit 0 : CMOS level 1 : TTL level Not used Note: Keep setting the P36/INT1 input level selection bit to “0” (initial value) for 32-pin version. Pull-up control register (PULL: address 001616, initial value: 0016) P00 pull-up control bit b7 b0 0 : Pull-up Off 1 : Pull-up On P37 pull-up control bit P35, P36 pull-up control bit P34 pull-up control bit P30 – P33 pull-up control bit P04 – P07 pull-up control bit P02, P03 pull-up control bit P01 pull-up control bit Note: Pins set to output ports are disconnected from pull-up control.

Rev.2.00 Jun 21, 2004 HARDWARE Table 5 I/O port function table Pin P00/CNTR 1 P01/TYOUT P02/TZOUT P03/TXOUT P04–P0 7 P10/RxD1 P11/TxD1 P12/SCLK1 /SCLK2 P13/SRDY1 /SDATA2 P14/CNTR 0 P20/AN0– P27/AN7 P30–P3 5 P36/INT1 P37/INT0 Input/output I/O individual bits I/O format

• CMOS compatible input level
• CMOS 3-state output (Note 1) Non-port function Key input interrupt Timer X function output Timer Y function output Timer Z function output Timer A function input Serial I/O1 function input/output Serial I/O2 function input/output Timer X function input/output A/D conversion input External interrupt input Related SFRs Pull-up control register Timer Y mode register Timer Z mode register Timer X mode register Timer Y,Z waveform output control register Timer A mode register Serial I/O1 control register Serial I/O1 control register Serial I/O2 control register Timer X mode register A/D control register Interrupt edge selection register Diagram No. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level. 2: P26/AN 6 and P27/AN7 do not exist for the 32-pin version. 3: P35 and P36/INT1 do not exist for the 32-pin version. Name I/O port P0 I/O port P1 I/O port P2 (Note 2) I/O port P3 (Note 3)

Rev.2.00 Jun 21, 2004 Fig. 17 Block diagram of ports (1) (6)Port P11 Data bus P o r t l a t c h S e r i a l I / O 1 o u t p u t P11/TxD 1 P-channel output disable bit ( 5 ) P o r t P 10 (4)Ports P04–P07 ( 1 ) P o r t P 00 D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h P u l l - u p c o n t r o l T o k e y i n p u t i n t e r r u p t g e n e r a t i n g c i r c u i t C N T R 1 i n t e r r u p t i n p u t (2)Ports P01, P02 P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e Timer output (7)Port P12 S e r i a l I / O 1 , s e r i a l I / O 2 c l o c k o u t p u t S e r i a l I / O 1 m o d e s e l e c t i o n b i t S e r i a l I / O 1 e n a b l e b i t Serial I/O1 enable bit S e r i a l I / O 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t SCLK2 pin selection bit ( 3 ) P o r t P 03 D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h Pull-up control T o k e y i n p u t i n t e r r u p t g e n e r a t i n g c i r c u i t D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h P u l l - u p c o n t r o l To key input interrupt generating circuit Timer output P 03/ T XO U T o u t p u t v a l i d D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h Pull-up control To key input interrupt generating circuit D i r e c t i o n r e g i s t e r Data bus P o r t l a t c h Serial I/O1 enable bit Receive enable bit Serial I/O1 input P 10, P 12, P 13 i n p u t l e v e l s e l e c t i o n b i t Direction register S e r i a l I / O 1 e n a b l e b i t T r a n s m i t e n a b l e b i t D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h Serial I/O1, serial I/O2 clock input P10, P12, P13 input level selection bit P 10, P 12, P 13, P 36, a n d P 37 i n p u t l e v e l a r e s w i t c h e d t o t h e C M O S / T T L l e v e l b y t h e p o r t P 1 P 3 c o n t r o l r e g i s t e r . P 00 k e y - o n w a k e u p s e l e c t i o n b i t W h e n t h e T T L l e v e l i s s e l e c t e d , t h e r e i s n o h y s t e r e s i s c h a r a c t e r i s t i c s . P 02/T ZO U P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e P r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e P r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n m o d e

Rev.2.00 Jun 21, 2004 HARDWARE Fig. 18 Block diagram of ports (2) Pull-up control INT interrupt input P3 input level selection bit (11) Ports P30–P35 Pull-up control (9) Port P14 Data bus Serial I/O1 ready output Serial I/O2 output Serial I/O2 input SDATA2 pin selection bit Port latch Direction register SDATA2 output in operation signal CNTR 0 interrupt input Pulse output mode Timer outputP10, P12, P13 input level selection bit Serial I/O mode selection bit Serial I/O1 enable bit SRDY1 output enable bit P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. Data bus Port latch Direction register Data bus Port latch Direction register Data bus Port latch Direction register A/D converter input Analog input pin selection bit (12) Ports P36, P37 Data bus Port latch Direction register (10) Ports P20–P27 (8) Port P13 When the TTL level is selected, there is no hysteresis characteristics.

Rev.2.00 Jun 21, 2004 Interrupts occur by 15 different sources : 5 external sources, 9 in- ternal sources and 1 software source. Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the in- terrupt request bit are set to “1” and the interrupt disable flag is set to “0”, an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt operation Upon acceptance of an interrupt the following operations are auto- matically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status reg- ister are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. I Notes on use When setting the followings, the interrupt request bit may be set to “1”.

• When switching external interrupt active edge Related register: Interrupt edge selection register (address 003A 16) Timer X mode register (address 2B16) Timer A mode register (address 1D16) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit (active edge switch bit). ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). Table 6 Interrupt vector address and priority Vector addresses (Note 1) High-orderPriority Low-order Interrupt request generating conditions RemarksInterrupt source FFFC 16 FFFA 16 FFF8 16 FFF6 16 FFF4 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFE8 16 FFE6 16 FFE4 16 FFE2 16 FFE0 16 FFDE 16 FFDC 16 FFFD 16 FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF 16 FFDD 16 Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: It is an interrupt which can use only for 36 pin version. Non-maskable Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling) External interrupt (active edge selectable) External interrupt (active edge selectable) STP release timer underflow Non-maskable software interrupt At reset input At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or when transmit buffer is empty At detection of either rising or falling edge of INT 0 input At detection of either rising or falling edge of INT1 input At falling of conjunction of input logical level for port P0 (at input) At detection of either rising or falling edge of CNTR 0 input At detection of either rising or falling edge of CNTR 1 input At timer X underflow At timer Y underflow At timer Z underflow At timer A underflow At completion of transmit/receive shift At completion of A/D conversion At timer 1 underflow Not available At BRK instruction execution Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit INT0 INT1 (Note 3) Key-on wake-up CNTR CNTR 1 Timer X Timer Y Timer Z Timer A Serial I/O2 A/D conversion Timer 1 Reserved area BRK instruction

Rev.2.00 Jun 21, 2004 HARDWARE Fig. 19 Interrupt control Fig. 20 Structure of Interrupt-related registers Interrupt disable flag I Interrupt request Interrupt request bit Interrupt enable bit BRK instruction Reset b 7 b 0 b7 b0 b 7 b 0 Interrupt edge selection register INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT 1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (returns “0” when read) 0 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled ( I N T E D G E : a d d r e s s 0 0 3 A 6, i n i t i a l v a l u e : 0 01 Interrupt request register 1 Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit INT 0 interrupt request bit INT1 interrupt request bit Key-on wake up interrupt request bit CNTR 0 interrupt request bit CNTR 1 interrupt request bit Timer X interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C 16, initial value : 0016) b 7 b 0 I n t e r r u p t c o n t r o l r e g i s t e r 1 S e r i a l I / O 1 r e c e i v e i n t e r r u p t e n a b l e b i t S e r i a l I O t r a n s m i t i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t D o n o t w r i t e t o t h i s b i t f o r p i n v e r s i o n K e y o n w a k e u p i n t e r r u p t e n a b l e b i t C N T R 0 i n t e r r u p t e n a b l e b i t C N T R 1 i n t e r r u p t e n a b l e b i t T i m e r X i n t e r r u p t e n a b l e b i t 0 : Interrupts disabled 1 : Interrupts enabled ( I C O N 1 : a d d r e s s 0 0 3 E1 6, i n i t i a l v a l u e : 0 01 I n t e r r u p t r e q u e s t r e g i s t e r 2 T i m e r Y i n t e r r u p t r e q u e s t b i t T i m e r Z i n t e r r u p t r e q u e s t b i t T i m e r A i n t e r r u p t r e q u e s t b i t S e r i a l I O i n t e r r u p t r e q u e s t b i t A D c o n v e r s i o n i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t N o t u s e d r e t u r n s w h e n r e a d ) 0 : No interrupt request issued 1 : Interrupt request issued ( I R E Q 2 : a d d r e s s 0 0 3 D 1 6, i n i t i a l v a l u e : 0 01 b 7 b 0 I n t e r r u p t c o n t r o l r e g i s t e r 2 T i m e r Y i n t e r r u p t e n a b l e b i t T i m e r Z i n t e r r u p t e n a b l e b i t T i m e r A i n t e r r u p t e n a b l e b i t S e r i a l I O i n t e r r u p t e n a b l e b i t A D c o n v e r s i o n i n t e r r u p t e n a b l e b i t T i m e r i n t e r r u p t e n a b l e b i t N o t u s e d r e t u r n s w h e n r e a d D o n o t w r i t e t o t h i s b i t 0 : Interrupts disabled 1 : Interrupts enabled ( I C O N 2 : a d d r e s s 0 0 3 F1 6, i n i t i a l v a l u e : 0 01

Rev.2.00 Jun 21, 2004 Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying “L” level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 21, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P0 0 to P03 as input ports. Fig. 21 Connection example when using key input interrupt and port P0 block diagram Port PXx “L” level output PULL register bit 3 = “0” Port P0 latch Port P07 Direction register = “1” *** P07 output Key input interrupt request Port P0 Input read circuit * P-channel transistor for pull-up CMOS output buffer PULL register bit 3 = “0” Port P0 latch Port P06 Direction register = “1” * P06 output PULL register bit 3 = “0” Port P05 latch Port P05 Direction register = “1” * P05 output PULL register bit 3 = “0” Port P04 latch Port P04 Direction register = “1” * P04 output PULL register bit 2 = “1” Port P03 latch Port P03 Direction register = “0” * P03 input PULL register bit 2 = “1” Port P02 latch Port P02 Direction register = “0” * P02 input PULL register bit 1 = “1” Port P01 latch Port P01 Direction register = “0” * P01 input PULL register bit 0 = “1” Port P00 latch Port P00 Direction register = “0” * P00 input Falling edge detection Falling edge detection Falling edge detection Falling edge detection Falling edge detection Falling edge detection Falling edge detection Falling edge detection Port P00 key-on wakeup selection bit

Rev.2.00 Jun 21, 2004 HARDWARE The 7540 Group has 5 timers: timer 1, timer A, timer X, timer Y and timer Z. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches “0”, an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to “1”. G Timer 1 Timer 1 is an 8-bit timer and counts the prescaler output. When Timer 1 underflows, the timer 1 interrupt request bit is set to “1”. Prescaler 1 is an 8-bit prescaler and counts the signal which is the oscillation frequency divided by 16. Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. The value of prescaler 1 latch is set to Prescaler 1 when Prescaler 1 underflows.The value of timer 1 latch is set to Timer 1 when Timer 1 underflows. When writing to Prescaler 1 (PRE1) is executed, the value is writ- ten to both the prescaler 1 latch and Prescaler 1. When writing to Timer 1 (T1) is executed, the value is written to both the timer 1 latch and Timer 1. When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is ex- ecuted, each count value is read out. Timer 1 always operates in the timer mode. Prescaler 1 counts the signal which is the oscillation frequency di- vided by 16. Each time the count clock is input, the contents of Prescaler 1 is decremented by 1. When the contents of Prescaler 1 reach “00 16”, an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into Prescaler 1 and count contin- ues. The division ratio of Prescaler 1 is 1/(n+1) provided that the value of Prescaler 1 is n. The contents of Timer 1 is decremented by 1 each time the under- flow signal of Prescaler 1 is input. When the contents of Timer 1 reach “00 16”, an underflow occurs at the next count clock, and the timer 1 latch is reloaded into Timer 1 and count continues. The di- vision ratio of Timer 1 is 1/(m+1) provided that the value of Timer 1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is 1/((n+1)✕ (m+1)) provided that the value of Prescaler 1 is n and the value of Timer 1 is m. Timer 1 cannot stop counting by software. G Timer A Timer A is a 16-bit timer and counts the signal which is the oscil- lation frequency divided by 16. When Timer A underflows, the timer A interrupt request bit is set to “1”. Timer A consists of the low-order of Timer A (TAL) and the high-or- der of Timer A (TAH). Timer A has the timer A latch to retain the reload value. The value of timer A latch is set to Timer A at the timing shown below.

• When Timer A undeflows.
• When an active edge is input from CNTR 1 pin (valid only when period measurement mode and pulse width HL continuously mea- surement mode). When writing to both the low-order of Timer A (TAL) and the high- order of Timer A (TAH) is executed, the value is written to both the timer A latch and Timer A. When reading from the low-order of Timer A (TAL) and the high-or- der of Timer A (TAH) is executed, the following values are read out according to the operating mode.
• In timer mode, event counter mode: The count value of Timer A is read out.
• In period measurement mode, pulse width HL continuously mea- surement mode: The measured value is read out. Be sure to write to/read out the low-order of Timer A (TAL) and the high-order of Timer A (TAH) in the following order; Read Read the high-order of Timer A (TAH) first, and the low-order of Timer A (TAL) next and be sure to read out both TAH and TAL. Write Write to the low-order of Timer A (TAL) first, and the high-order of Timer A (TAH) next and be sure to write to both TAL and TAH. Timer A can be selected in one of 4 operating modes by setting the timer A mode register. (1) Timer mode Timer A counts the oscillation frequency divided by 16. Each time the count clock is input, the contents of Timer A is decremented by 1. When the contents of Timer A reach “0000 16”, an underflow oc- curs at the next count clock, and the timer A latch is reloaded into Timer A. The division ratio of Timer A is 1/(n+1) provided that the value of Timer A is n. (2) Period measurement mode In the period measurement mode, the pulse period input from the 0/CNTR 1 pin is measured. CNTR 1 interrupt request is generated at rising/falling edge of CNTR 1 pin input singal. Simultaneousuly, the value in the timer A latch is reloaded inTimer A and count continues. The active edge of CNTR 1 pin input signal can be selected from rising or falling by the CNTR 1 active edge switch bit .The count value when trigger input from CNTR1 pin is accepted is retained until Timer A is read once.

Rev.2.00 Jun 21, 2004 (3) Event counter mode Timer A counts signals input from the P00/CNTR 1 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR1 pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit . (4) Pulse width HL continuously measurement mode In the pulse width HL continuously measurement mode, the pulse width (“H” and “L” levels) input to the P00/CNTR 1 pin is measured. CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. The count value when trigger input from the CNTR 1 pin is ac- cepted is retained until Timer A is read once. Timer A can stop counting by setting “1” to the timer A count stop bit in any mode. Also, when Timer A underflows, the timer A interrupt request bit is set to “1”. Note on Timer A is described below; I Note on Timer A CNTR 1 interrupt active edge selection CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at the falling edge of the CNTR1 pin input signal. When this bit is “1”, the CNTR 1 interrupt request bit is set to “1” at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR 1 pin input signal regardless of the setting of CNTR 1 active edge switch bit. Fig. 22 Structure of timer A mode register Timer A mode register (TAM : address 001D16, initial value: 0016) b7 b0 Not used (return “0” when read) Timer A operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR 1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge period in period measurement mode Falling edge active for CNTR 1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR1 interrupt Timer A count stop bit 0 : Count start 1 : Count stop G Timer X Timer X is an 8-bit timer and counts the prescaler X output. When Timer X underflows, the timer X interrupt request bit is set to “1”. Prescaler X is an 8-bit prescaler and counts the signal selected by the timer X count source selection bit. Prescaler X and Timer X have the prescaler X latch and the timer X latch to retain the reload value, respectively. The value of prescaler X latch is set to Prescaler X when Prescaler X underflows.The value of timer X latch is set to Timer X when Timer X underflows. When writing to Prescaler X (PREX) is executed, the value is writ- ten to both the prescaler X latch and Prescaler X. When writing to Timer X (TX) is executed, the value is written to both the timer X latch and Timer X. When reading from Prescaler X (PREX) and Timer X (TX) is ex- ecuted, each count value is read out. Timer X can can be selected in one of 4 operating modes by set- ting the timer X operating mode bits of the timer X mode register. (1) Timer mode Prescaler X counts the count source selected by the timer X count source selection bits. Each time the count clock is input, the con- tents of Prescaler X is decremented by 1. When the contents of Prescaler X reach “00 16”, an underflow occurs at the next count clock, and the prescaler X latch is reloaded into Prescaler X and count continues. The division ratio of Prescaler X is 1/(n+1) pro- vided that the value of Prescaler X is n. The contents of Timer X is decremented by 1 each time the under- flow signal of Prescaler X is input. When the contents of Timer X reach “00 16”, an underflow occurs at the next count clock, and the timer X latch is reloaded into Timer X and count continues. The di- vision ratio of Timer X is 1/(m+1) provided that the value of Timer X is m. Accordingly, the division ratio of Prescaler X and Timer X is 1/((n+1)✕ (m+1)) provided that the value of Prescaler X is n and the value of Timer X is m. (2) Pulse output mode In the pulse output mode, the waveform whose polarity is inverted each time timer X underflows is output from the CNTR 0 pin. The output level of CNTR0 pin can be selected by the CNTR0 ac- tive edge switch bit. When the CNTR0 active edge switch bit is “0”, the output of CNTR0 pin is started at “H” level. When this bit is “1”, the output is started at “L” level. Also, the inverted waveform of pulse output from CNTR 0 pin can be output from TXOUT pin by setting “1” to the P03/TXOUT output valid bit. When using a timer in this mode, set the port P1 4 and P03 direc- tion registers to output mode. (3) Event counter mode The timer A counts signals input from the P14/CNTR 0 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR 0 pin input signal can be selected from rising or falling by the CNTR0 active edge switch bit .

Rev.2.00 Jun 21, 2004 HARDWARE (4) Pulse width measurement mode In the pulse width measurement mode, the pulse width of the sig- nal input to P14/CNTR 0 pin is measured. The operation of Timer X can be controlled by the level of the sig- nal input from the CNTR 0 pin. When the CNTR 0 active edge switch bit is “0”, the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is “H”. The count is stopped while the pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR 0 pin is “L”. The count is stopped while the pin is “H”. Timer X can stop counting by setting “1” to the timer X count stop bit in any mode. Also, when Timer X underflows, the timer X interrupt request bit is set to “1”. Note on Timer X is described below; I Note on Timer X CNTR 0 interrupt active edge selection CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is “0”, the CNTR 0 interrupt request bit is set to “1” at the falling edge of CNTR0 pin input signal. When this bit is “1”, the CNTR 0 interrupt request bit is set to “1” at the rising edge of CNTR 0 pin input signal. Fig. 23 Structure of timer X mode register Fig. 24 Timer count source set register Timer X mode register (TXM : address 002B16, initial value: 0016) CNTR 0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge (in event counter mode) 1 : Interrupt at rising edge Count at falling edge (in event counter mode) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode Not used (return “0” when read) Timer X count stop bit 0 : Count start 1 : Count stop b7 b0 P03/TXOUT output valid bit 0 : Output invalid (I/O port) 1 : Output valid (Inverted CNTR 0 output) Timer count source set register (TCSS : address 002E16, initial value: 0016) b7 b0 Timer X count source selection bits b1 b0 0 0 : f(X IN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available Notes 1: f(XIN) can be used as timer X count source when using a ceramic resonator or on-chip oscillator. Do not use it at RC oscillation. 2: System operates using an on-chip oscillator as a count Source by setting the on-chip oscillator to oscillation enabled by bit 3 of CPUM. Timer Y count source selection bits b3 b2 0 0 : f(X IN)/16 0 1 : f(XIN)/2 1 0 : On-chip oscillator output (Note 2) 1 1 : Not available Timer Z count source selection bits b5 b4 0 0 : f(X IN)/16 0 1 : f(XIN)/2 1 0 : Timer Y underflow 1 1 : Not available Fix this bit to “0”. Not used (return “0” when read)

Rev.2.00 Jun 21, 2004 Timer Y is an 8-bit timer and counts the prescaler Y output. When Timer Y underflows, the timer Y interrupt request bit is set to “1”. Prescaler Y is an 8-bit prescaler and counts the signal selected by the timer Y count source selection bit. Prescaler Y has the prescaler Y latch to retain the reload value. Timer Y has the timer Y primary latch and timer Y secondary latch to retain the reload value. The value of prescaler Y latch is set to Prescaler Y when Prescaler Y underflows.The value of timer Y primary latch or timer Y secondary latch are set to Timer Y when Timer Y underflows. As for the value to transfer to Timer Y, either of timer Y primary or timer Y secondary is selected depending on the timer Y operating mode. When writing to Prescaler Y (PREY), timer Y primary (TYP) or timer Y secondary (TYS) is executed, writing to “latch only” or “latch and prescaler (timer)” can be selected by the setting value of the timer Y write control bit. Be sure to set the timer Y write con- trol bit because there are some notes according to the operating mode. When reading from Prescaler Y (PREY) is executed, the count value of Prescaler Y is read out. When reading from timer Y pri- mary (TYP) is executed, the count value of Timer Y is read out. The count value of Timer Y can be read out by reading from the timer Y primary (TYP) even when the value of timer Y primary latch or timer Y secondary latch is counted. When reading the timer Y secondary (TYS) is executed, the undefined value is read out. Timer Y can be selected in one of 2 operating modes by setting the timer Y operating mode bits of the timer Y, Z mode register. (1) Timer mode Prescaler Y counts the count source selected by the timer Y count source selection bits. Each time the count clock is input, the con- tents of Prescaler Y is decremented by 1. When the contents of Prescaler Y reach “00 16”, an underflow occurs at the next count clock, and the prescaler Y latch is reloaded into Prescaler Y. The division ratio of Prescaler Y is 1/(n+1) provided that the value of Prescaler Y is n. The contents of Timer Y is decremented by 1 each time the under- flow signal of Prescaler Y is input. When the contents of Timer Y reach “00 16”, an underflow occurs at the next count clock, and the timer Y primary latch is reloaded into Timer Y and count continues. (In the timer mode, the contents of timer Y primary latch is counted. Timer Y secondary latch is not used in this mode.) The division ratio of Timer Y is 1/(m+1) provided that the value of Timer Y is m. Accordingly, the division ratio of Prescaler Y and Timer Y is 1/((n+1)✕ (m+1)) provided that the value of Prescaler Y is n and the value of Timer Y is m. In the timer mode, writing to “latch only” or “latches and Prescaler Y and timer Y primary” can be selected by the setting value of the timer Y write control bit. (2) Programmable waveform generation mode In the programmable waveform generation mode, timer counts the setting value of timer Y primary and the setting value of timer Y secondary alternately, the waveform inverted each time Timer Y underflows is output from TY OUT pin. When using this mode, be sure to set “1” to the timer Y write con- trol bit to select “write to latch only”. Also, set the port P0 1 direction registers to output mode. The active edge of output waveform is set by the timer Y output level latch (b5) of the timer Y, Z waveform output control register (PUM). When “0” is set to b5 of PUM, “H” interval by the setting value of TYP or “L” interval by the setting value of TYS is output alternately. When “1” is set to b5 of PUM, “L” interval by the setting value of TYP or “H” interval by the setting value of TYS is output alternately. Also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer Y primary wave- form extension control bit (b2) and the timer Y secondary waveform extension control bit (b3) of PUM to “1”. As a result, the waveforms of more accurate resolution can be output. When b2 and b3 of PUM are used, the frequency and duty of the output waveform are as follows; Waveform frequency: FYOUT= Duty: DYOUT= TMYCL: Timer Y count source (frequency) TYP: Timer Y primary (8bit) TYS: Timer Y secondary (8bit) EXPYP: Timer Y primary waveform extension control bit (1bit) EXPYS: Timer Y secondary waveform extension control bit (1bit) In the programmable waveform generation mode, when values of the TYP, TYS, EXPYP and EXPYS are changed, the output wave- form is changed at the beginning (timer Y primary waveform interval) of waveform period. When the count values are changed, set values to the TYS, EXPYP and EXPYS first. After then, set the value to TYP. The val- ues are set all at once at the beginning of the next waveform period when the value is set to TYP . (When writing at timer stop is executed, writing to TYP at last is required.) Notes on programmable waveform generation mode is described below; 2✕ TMYCL 2✕ (TYP+1)+2✕ (TYS+1)+(EXPYP+EXPYS) 2✕ (TYP+1)+EXPYP (2✕ (TYP+1)+EXPYP)+(2✕ (TYS+1)+EXPYS)

Rev.2.00 Jun 21, 2004 HARDWARE I Notes on programmable generation waveform mode

• Count set value In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the set- ting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again.
• Write timing to TYP In the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function The waveform extension function by the timer Y waveform exten- sion control bit can be used only when “00 16” is set to Prescaler Y. When the value other than “0016” is set to Prescaler Y, be sure to set “0” to EXPYP and EXPYS.
• Timer Y write mode When using this mode, be sure to set “1” to the timer Y write con- trol bit to select “write to latch only”. Timer Y can stop counting by setting “1” to the timer Y count stop bit in any mode. Also, when Timer Y underflows, the timer Y interrupt request bit is set to “1”. Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.)

Rev.2.00 Jun 21, 2004 Timer Z is an 8-bit timer and counts the prescaler Z output. When Timer Z underflows, the timer Z interrupt request bit is set to “1”. Prescaler Z is an 8-bit prescaler and counts the signal selected by the timer Z count source selection bit. Prescaler Z has the prescaler Z latch to retain the reload value. Timer Z has the timer Z primary latch and timer Z secondary latch to retain the reload value. The value of prescaler Z latch is set to Prescaler Z when Prescaler Z underflows.The value of timer Z primary latch or timer Z second- ary latch are set to Timer Z when Timer Z underflows. As for the value to transfer to Timer Z, either of timer Z primary or timer Z secondary is selected depending on the timer Z operating mode. When writing to Prescaler Z (PREZ), timer Z primary (TZP) or timer Z secondary (TZS) is executed, writing to “latch only” or “latches and Prescaler Z and Timer Z” can be selected by the set- ting value of the timer Z write control bit. Be sure to set the write control bit because there are some notes according to the operat- ing mode. When reading from Prescaler Z (PREZ) is executed, the count value of Prescaler Z is read out. When reading from timer Z pri- mary (TZP) is executed, the count value of Timer Z is read out. The count value of Timer Z can be read out by reading from the timer Z primary (TZP) even when the value of timer Z primary latch or timer Z secondary latch is counted. When reading the timer Z secondary (TZS) is executed, the undefined value is read out. Timer Z can be selected in one of 4 operating modes by setting the timer Z operating mode bits of the timer Y , Z mode register. (1) Timer mode Prescaler Z counts the count source selected by the timer Z count source selection bits. Each time the count clock is input, the con- tents of Prescaler Z is decremented by 1. When the contents of Prescaler Z reach “00 16”, an underflow occurs at the next count clock, and the prescaler Z latch is reloaded into Prescaler Z. The division ratio of Prescaler Z is 1/(n+1) provided that the value of Prescaler Z is n. The contents of Timer Z is decremented by 1 each time the under- flow signal of Prescaler Z is input. When the contents of Timer Z reach “00 16”, an underflow occurs at the next count clock, and the timer Z primary latch is reloaded into Timer Z and count continues. (In the timer mode, the contents of timer Z primary latch is counted. Timer Z secondary latch is not used in this mode.) The division ratio of Timer Z is 1/(m+1) provided that the value of Timer Z is m. Accordingly, the division ratio of Prescaler Z and Timer Z is 1/((n+1)✕ (m+1)) provided that the value of Prescaler Z is n and the value of Timer Z is m. In the timer mode, writing to “latch only” or “latches and Prescaler Z and timer Z primary” can be selected by the setting value of the timer Z write control bit. (2) Programmable waveform generation mode In the programmable waveform generation mode, timer counts the setting value of timer Z primary and the setting value of timer Z secondary alternately, the waveform inverted each time Timer Z underflows is output from TZ OUT pin. When using this mode, be sure to set “1” to the timer Z write con- trol bit to select “write to latch only”. Also, set the port P0 2 direction registers to output mode. The active edge of output waveform is set by the timer Z output level latch (b4) of the timer Y, Z waveform output control register (PUM). When “0” is set to b4 of PUM, “H” interval by the setting value of TZP or “L” interval by the setting value of TZS is output al- ternately. When “1” is set to b4 of PUM, “L” interval by the setting value of TZP or “H” interval by the setting value of TZS is output alternately. Also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer Z primary wave- form extension control bit (b0) and the timer Z secondary waveform extension control bit (b1) of PUM to “1”. As a result, the waveforms of more accurate resolution can be output. When b0 and b1 of PUM are used, the frequency and duty of the output waveform are as follows; Waveform frequency: FZOUT= Duty: DZOUT= TMZCL: Timer Z count source (frequency) TZP: Timer Z primary (8bit) TZS: Timer Z secondary (8bit) EXPZP: Timer Z primary waveform extension control bit (1bit) EXPZS: Timer Z secondary waveform extension control bit (1bit) In the programmable waveform generation mode, when values of the TZP, TZS, EXPZP and EXPZS are changed, the output wave- form is changed at the beginning (timer Z primary waveform interval) of waveform period. When the count values are changed, set values to the TZS, EXPZP and EXPZS first. After then, set the value to TZP. The val- ues are set all at once at the beginning of the next waveform period when the value is set to TZP . (When writing at timer stop is executed, writing to TZP at last is required.) 2✕ TMZCL 2✕ (TZP+1)+2✕ (TZS+1)+(EXPZP+EXPZS) 2✕ (TZP+1)+EXPZP (2✕ (TZP+1)+EXPZP)+(2✕ (TZS+1)+EXPZS

Rev.2.00 Jun 21, 2004 HARDWARE Notes on the programmable waveform generation mode are de- scribed below; I Notes on programmable waveform generation mode

• Count set value In the programmable waveform generation mode, values of TZS, EXPZP, and EXPZS are valid by writing to TZP because the set- ting to them is executed all at once by writing to TZP . Even when changing TZP is not required, write the same value again.
• Write timing to TZP In the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function The waveform extension function by the timer Z waveform exten- sion control bit can be used only when “00 16” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used.
• Timer Z write mode When using this mode, be sure to set “1” to the timer Z write con- trol bit to select “write to latch only”. (3) Programmable one-shot generation mode In the programmable one-shot generation mode, the one-shot pulse by the setting value of timer Z primary can be output from TZ OUT pin by software or external trigger. When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. Also, set the port P0 2 direction registers to output mode. In this mode, TZS is not used. The active edge of output waveform is set by the timer Z output level latch (b5) of the timer Y, Z waveform output control register (PUM). When “0” is set to b5 of PUM, “H” pulse during the interval of the TZP setting value is output. When “1” is set to b5 of PUM, “L” pulse during the interval of the TZP setting value is output. Also, in this mode, the interval of the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (b2) of PUM to “1”. As a result, the waveforms of more accurate resolution can be output. In the programmable one-shot generation mode, the trigger by software or the external INT 0 pin can be accepted by writing “0” to the timer Z count stop bit after the count value is set. (At the time when “0” is written to the timer Z count stop bit, Timer Z stops.) By writing “1” to the timer Z one-shot start bit, or by inputting the valid trigger to the INT 0 pin after the trigger to the INT0 pin be- comes valid by writing “1” to the INT0 pin one-shot trigger control bit, Timer Z starts counting, at the same time, the output of TZOUT pin is inverted. When Timer Z underflows, the output of TZOUT pin is inverted again and Timer Z stops. When also the trigger of INT0 pin is accepted, the contents of the one-shot start bit is changed to “1” by hardware. The falling or rising can be selected as the edge of the valid trig- ger of INT 0 pin by the INT0 pin one-shot trigger edge selection bit. During the one-shot pulse output interval, the one-shot pulse out- put can be stopped forcibly by writing “0” to the timer Z one-shot start bit. In the programmable one-shot generation mode, when the count values are changed, set value to the EXPZP first. After then, set the value to TZP. The values are set all at once at the beginning of the next one-shot pulse when the value is set to TZP. (When writ- ing at timer stop is executed, writing to TZP at last is required.) Notes on the programmable one-shot generation mode are de- scribed below; I Notes on programmable one-shot generation mode
• Count set value In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again.
• Write timing to TZP In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer un- derflow simultanesously.
• Usage of waveform extension function The waveform extension function by the timer Z waveform exten- sion control bit can be used only when “00 16” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used.
• Timer Z write mode When using this mode, be sure to set “1” to the timer Z write con- trol bit to select “write to latch only”.

Rev.2.00 Jun 21, 2004 (4) Programmable wait one-shot generation mode In the programmable wait one-shot generation mode, the one-shot pulse by the setting value of timer Z secondary can be output from TZ OUT pin by software or external trigger to INT0 pin after the wait by the setting value of the timer Z primary. When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. Also, set the port P0 2 direction registers to output mode. The active edge of output waveform is set by the timer Z output level latch (b5) of the timer Y, Z waveform output control register (PUM). When “0” is set to b5 of PUM, after the wait during the in- terval of the TZP setting value, “H” pulse during the interval of the TZS setting value is output. When “1” is set to b5 of PUM, after the wait during the interval of the TZP setting value, “L” pulse during the interval of the TZS setting value is output. Also, in this mode, the intervals of the wait and the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting EXPZP and EXPZS of PUM to “1”. As a result, the waveforms of more accurate resolution can be output. In the programmable one-shot generation mode, the trigger by software or the external INT 0 pin can be accepted by writing “0” to the timer Z count stop bit after the count value is set. (At the time when “0” is written to the timer Z count stop bit, Timer Z stops.) By writing “1” to the timer Z one-shot start bit, or by inputting the valid trigger to the INT 0 pin after the trigger to the INT0 pin be- comes valid by writing “1” to the INT0 pin one-shot trigger control bit, Timer Z starts counting. While Timer Z counts the TZP, the initial value of the TZ OUT pin output is retained. When Timer Z underflows, the value of TZS is reloaded, at the same time, the output of TZ OUT pin is inverted. When Timer Z underflows, the output of TZOUT pin is inverted again and Timer Z stops. When also the trigger of INT0 pin is ac- cepted, the contents of the one-shot start bit is changed to “1” by hardware. The falling or rising can be selected as the edge of the valid trig- ger of INT 0 pin by the INT0 pin one-shot trigger edge selection bit. During the wait interval and the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing “0” to the timer Z one-shot start bit. In the programmable wait one-shot generation mode, when the count values are changed, set values to the TZS, EXPZP and EXPZS first. After then, set the value to TZP. The values are set all at once at the beginning of the next wait interval when the value is set to TZP . (When writing at timer stop is executed, writing to TZP at last is required.) Notes on the programmable wait one-shot generation mode are described below; I Notes on programmable wait one-shot generation mode

• Count set value In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again.
• Write timing to TZP In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by soft- ware in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function The waveform extension function by the timer Z waveform exten- sion control bit can be used only when “00 16” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used.
• Timer Z write mode When using this mode, be sure to set “1” to the timer Z write con- trol bit to select “write to latch only”. Timer Z can stop counting by setting “1” to the timer Z count stop bit in any mode. Also, when Timer Z underflows, the timer Z interrupt request bit is set to “1”. Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.)

Rev.2.00 Jun 21, 2004 HARDWARE Fig. 26 Structure of timer Y, Z waveform output control register Fig. 27 Structure of one-shot start register Fig. 25 Structure of timer Y, Z mode register b7 b0 Timer Y, Z mode register (TYZM : address 002016, initial value: 0016) Timer Y operating mode bit 0 : Timer mode 1 : Programmable waveform generation mode Not used (return “0” when read) Timer Y write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Y count stop bit 0 : Count start 1 : Count stop Timer Z operating mode bits b5 b4 0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode Timer Z write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Z count stop bit 0 : Count start 1 : Count stop b7 b0 Timer Y, Z waveform output control register (PUM : address 0024 16, initial value: 0016) Timer Y primary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Y secondary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Z primary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Z secondary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Y output level latch 0 : “L” output 1 : “H” output Timer Z output level latch 0 : “L” output 1 : “H” output INT 0 pin one-shot trigger control bit 0 : INT0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid INT0 pin one-shot trigger active edge selection bit 0 : Falling edge trigger 1 : Rising edge trigger b7 b0 One-shot start register (ONS : address 002A16, initial value: 0016) Timer Z one-shot start bit 0 : One-shot stop 1 : One-shot start Not used (return “0” when read)

Rev.2.00 Jun 21, 2004 Fig. 28 Block diagram of timer 1 and timer A Timer A (low-order) latch (8) Timer A (low-order) (8) Timer A (high-order) latch (8) Timer A (high-order) (8) Data busP00/CNTR 1 CNTR 1 active edge switch bit f(XIN)/16 Rising edge detected Falling edge detected Timer A operation mode bit Timer A count stop bit Prescaler 1 latch (8) Prescaler 1 (8) Timer 1 latch (8) Timer 1 (8)f(XIN)/16 Data bus Timer A interrupt request bit Timer 1 interrupt request bit Pulse width HL continuously measurement mode Period measurement mode

Rev.2.00 Jun 21, 2004 HARDWARE Fig. 29 Block diagram of timer X, timer Y and timer Z Q Q TToggle flip-flop Timer Y count stop bit Programmable waveform gengeration mode f(XIN)/16 f(XIN)/2 Timer Y count source selection bits Waveform extension function Timer Y primary waveform extension control bit P01/TYOUT Timer Y output level latch Q Q T f(XIN)/16 Waveform extension function Timer Z primary waveform extenstion control bit P02/TZOUT INT0 interrupt request bit 7/INT0 f(XIN)/2 Timer Z count stop bit On-chip oscillator clock RING (on-chip oscillator output in Fig. 51, 52) Q Q P14/CNTR 0 R T f(XIN)/16 f(XIN)/2 Timer X interrupt request bit Toggle flip-flop Timer X count stop bit Pulse width measurement mode Event counter mode CNTR interrupt request bit Pulse output mode Port P1 latchPort P14 direction register CNTR 0 active edge switch bit Timer mode Pulse output mode CNTR 0 active edge switch bit Timer X count source selection bits f(XIN) P03/ TX OUT Prescaler X latch (8) Prescaler X (8) Timer X latch (8) Timer X (8) Data bus “0” “1” “0” “1” Writing to timer X latch Pulse output mode P03/TXOUT output valid Port P03 latch Port P03 direction register Prescaler Y latch (8) Prescaler Y (8) Timer Y primary latch (8) Timer Y (8) Data bus Timer Y secondary latch (8) Timer Y interrupt request bit Port P0 1 latch Port P01 direction register Timer Y secondary waveform extension control bit Prescaler Z latch (8) Prescaler Z (8) Timer Z primary latch (8) Timer Z (8) Data bus Timer Z secondary latch (8) Timer Z interrupt request bit Timer Z count source selection bits One-shot pulse trigger input INT 0 pin trigger active edge selection bit Programmable one-shot generation mode Programmable wait one-shot generation mode Timer Z one-shot start bit Timer Z secondary waveform extenstion control bit Port P02 latch Port P02 direction register Toggle flip flop Timer Z output level latch Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode

Rev.2.00 Jun 21, 2004 Fig. 30 Block diagram of clock synchronous serial I/O1 Fig. 31 Operation of clock synchronous serial I/O1 function Serial I/O G Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6) to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. F/F P12/SCLK1 Serial I/O1 status register Serial I/O1 control register P13/SRDY1 P10/RXD 1 P11/TXD 1 XIN Receive buffer register Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuitShift clock Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 BRG count source selection bit Clock control circuitFalling-edge detector Transmit buffer register Data bus Address 001816 Shift clock Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 001916 Data bus Address 001A16 Transmit shift register D 7 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD Write pulse to receive/transmit buffer register (address 0018 16) Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal SRDY1

Rev.2.00 Jun 21, 2004 HARDWARE Fig. 32 Block diagram of UART serial I/O1 (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. XIN OE PE FE Data bus Receive buffer register Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Baud rate generator Frequency division ratio 1/(n+1) Address 001C16 ST/SP/PA generator Transmit buffer register Data bus Transmit shift register Address 001816 Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Address 001916 ST detector SP detector UART control register Address 001B16 Character length selection bit Address 001A16 BRG count source selection bit Transmit interrupt source selection bit Serial I/O1 synchronous clock selection bit Clock control circuit Character length selection bit 7 bits 8 bits Serial I/O1 control register P12/SCLK1 Serial I/O1 status register P10/RXD 1 P11/TXD 1 The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 33 Operation of UART serial I/O1 function TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1 STD 0 D 1 SP D 0 D 1ST SP Transmit or receive clock Transmit buffer write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Serial output TXD Serial input RXD Receive buffer read signal

Rev.2.00 Jun 21, 2004 [Transmit buffer register/receive buffer register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O1 status register (SIO1STS)] 0019 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit of the serial I/O1 control regis- ter has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O1 control register (SIO1CON)] 001A The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART control register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the P1 1/TXD1 pin. [Baud rate generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. I Notes on serial I/O

• Serial I/O interrupt When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➄ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O1 is enabled. The functions of P1 2 and P13 are switched with the setting values of a serial I/O1 mode selection bit and a serial I/O1 synchronous clock selection bit as follows. (1) Serial I/O1 mode selection bit → “1” : Clock synchronous type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0” : P1 2 pin turns into an output pin of a synchronous clock. “1” : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY) “0” : P1 3 pin can be used as a normal I/O pin. “1” : P13 pin turns into a SRDY output pin. (2) Serial I/O1 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0”: P1 2 pin can be used as a normal I/O pin. “1”: P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin.

Rev.2.00 Jun 21, 2004 HARDWARE Fig. 34 Structure of serial I/O1-related registers b7b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) Serial I/O1 status register Serial I/O1 control register b0 b0 BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. S RDY1 output enable bit (SRDY) 0: P13 pin operates as ordinary I/O pin 1: P13 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P1 0 to P13 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P1 0 to P13operate as serial I/O pins) b7 UART control register Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 1/TXD 1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) (SIO1STS : address 001916, initial value: 0016) (SIO1CON : address 001A16, initial value: 0016) (UARTCON : address 001B16, initial value: E016)

Rev.2.00 Jun 21, 2004 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2 the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. Note: Serial I/O2 can be used in the following cases; (1) Serial I/O1 is not used, (2) Serial I/O1 is used as UART and BRG output divided by 16 is selected as the synchronized clock. [Serial I/O2 control register] SIO2CON The serial I/O2 control register contains 8 bits which control vari- ous serial I/O functions.

• Set “0” to bit 3 to receive.
• At reception, clear bit 7 to “0” by writing a dummy data to the se- rial I/O2 register after completion of shift. Fig. 35 Structure of serial I/O2 control registers Fig. 36 Block diagram of serial I/O2 Internal synchronous clock selection bits 000 : f(XIN)/8 001 : f(XIN)/16 010 : f(XIN)/32 011 : f(XIN)/64 110 : f(XIN)/128 111 : f(XIN)/256 b7 b0 Not used (returns “0” when read) Transfer direction selection bit 0 : LSB first 1 : MSB first S CLK2 pin selection bit 0 : External clock (SCLK2 is an input) 1 : Internal clock (SCLK2 is an output) Transmit / receive shift completion flag 0 : shift in progress 1 : shift completed Note : When using it as a SDATA input, set the port P13 direction register to “0”. Serial I/O2 control register (SIO2CON: address 003016, initila value: 0016) SDATA2 pin selection bit (Note) 0 : I/O port / SDATA2 input 1 : SDATA2 output “1” “0” “0” “1” “0” “1” XIN Data bus Serial I/O2 interrupt request SDATA2 pin selection bit Serial I/O counter 2 (3) Serial I/O shift register 2 (8) SCLK2 pin selection bit Internal synchronous clock selection bits Divider P12/SCLK2 P13/SDATA2 P12 latch SCLK2 pin selection bit SCLK P13 latch SDATA2 pin selection bit

Rev.2.00 Jun 21, 2004 HARDWARE By writing to the serial I/O2 register (address 003116) the serial I/ O2 counter is set to “7”. After writing, the S DATA2 pin outputs data every time the transfer clock shifts from “H” to “L”. And, as the transfer clock shifts from “L” to “H”, the SDATA2 pin reads data, and at the same time the contents of the serial I/O2 register are shifted by 1 bit. When the internal clock is selected as the transfer clock source, the following operations execute as the transfer clock counts up to

• Serial I/O2 counter is cleared to “0”.
• Transfer clock stops at an “H” level.
• Interrupt request bit is set.
• Shift completion flag is set. Also, the S DATA2 pin is in a high impedance state after the data transfer is completed (refer to Fig.37). When the external clock is selected as the transfer clock source, the interrupt request bit is set as the transfer clock counts up to 8, but external control of the clock is required since it does not stop. Notice that the S DATA2 pin is not in a high impedance state on the completion of data transfer. Also, after the receive operation is completed, the transmit/receive shift completion flag is cleared by reading the serial I/O2 register. At transmit, the transmit/receive shift completion flag is cleared and the transmit operation is started by writing to serial I/O2 regis- ter. Fig. 37 Serial I/O2 timing (LSB first) D 0 Note : Synchronous clock Serial I/O2 register write signal Transfer clock (Note) SDATA2 at serial I/O2 input receive SDATA2 at serial I/O2 output transmit Serial I/O2 interrupt request bit set Transmit/receive shift completion flag set D 1 D 2 D 3 D 4 D 5 D 6 D 7 When the internal clock is selected as the transfer and the direction register of P1 3/SDATA2 pin is set to the input mode, the SDATA2 pin is in a high impedance state after the data transfer is completed.

Rev.2.00 Jun 21, 2004 The functional blocks of the A/D converter are described below. [A/D conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during an A/ D conversion. [A/D control register] ADCON The A/D control register controls the A/D converter. Bit 2 to 0 are analog input pin selection bits. Bit 4 is the AD conversion comple- tion bit. The value of this bit remains at “0” during A/D conversion, and changes to “1” at completion of A/D conversion. A/D conversion is started by setting this bit to “0”. [Comparison voltage generator] The comparison voltage generator divides the voltage between AV SS and VREF by 1024, and outputs the divided voltages. [Channel selector] The channel selector selects one of ports P27/AN7 to P20/AN0, and inputs the voltage to the comparator. [Comparator and control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A/D conver- sion register. When A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Because the comparator is constructed linked to a capacitor, set f(X IN) to 500 kHz or more during A/D conversion. I Note on A/D converter As for AD translation accuracy, on the following operating condi- tions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensi- tive to noise when V REF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where V REF voltage and Vcc voltage are set up to the same value. Fig. 38 Structure of A/D control register Fig. 39 Structure of A/D conversion register Fig. 40 Block diagram of A/D converter A / D c o n t r o l r e g i s t e r A D C O N a d d r e s s i n i t i a l v a l u e N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d ) N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d ) A D c o n v e r s i o n c o m p l e t i o n b i t C o n v e r s i o n i n p r o g r e s s C o n v e r s i o n c o m p l e t e d b 7 b 0 A n a l o g i n p u t p i n s e l e c t i o n b i t s P 20/ A N 0 P 21/ A N 1 P 22/ A N 2 P 23/ A N 3 P 24/ A N 4 P 25/ A N 5 P 26/ A N 6 N o t e P 27/ A N 7 N o t e Note: These can be used only for 36 pin version. Read 8-bit (Read only address 003516) b7 b0 b9 b8 b7 b6 b5 b4 b3 b2(Address 003516) Read 10-bit (read in order address 003616, 003516) b7 b0 b9 b8(Address 003616) b7 b0 b7 b6 b5 b4 b3 b2 b1 b0(Address 003516) Note: High-order 6-bit of address 003616 returns “0” when read. A / D c o n t r o l r e g i s t e r A d d r e s s C h a n n e l s e l e c t o r A / D c o n t r o l c i r c u i t R e s i s t o r l a d d e r VR E F Comparator A / D i n t e r r u p t r e q u e s t b7 b0 D a t a b u s 1 0 P 20/ A N 0 P 21/ A N 1 P 22/ A N 2 P 23/ A N 3 P 24/ A N 4 P 25/ A N 5 P 26/ A N 6 P 27/ A N 7 A / D c o n v e r s i o n r e g i s t e r ( l o w - o r d e r ) ( A d d r e s s 0 0 3 61 ( A d d r e s s 0 0 3 51 A / D c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) VS S (2) When VREF voltage is lower than [3.0 V], the accuracy at the low temperature may become extremely low compared with that at room temperature When the system would be used at low temperature, the use at V REF =3.0 V or more is recom- mended.

Rev.2.00 Jun 21, 2004 HARDWARE The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8-bit watchdog timer L, being a 16-bit counter. Standard operation of watchdog timer The watchdog timer stops when the watchdog timer control regis- ter (address 0039 16) is not set after reset. Writing an optional value to the watchdog timer control register (address 003916) causes the watchdog timer to start to count down. When the watchdog timer H underflows, an internal reset occurs. Accord- ingly, it is programmed that the watchdog timer control register (address 0039 16) can be set before an underflow occurs. When the watchdog timer control register (address 003916) is read, the values of the high-order 6-bit of the watchdog timer H, STP instruction disable bit and watchdog timer H count source se- lection bit are read. Initial value of watchdog timer By a reset or writing to the watchdog timer control register (ad- dress 0039 16), the watchdog timer H is set to “FF16” and the watchdog timer L is set to “FF16”. Operation of watchdog timer H count source selection bit A watchdog timer H count source can be selected by bit 7 of the watchdog timer control register (address 0039 16). When this bit is “0”, the count source becomes a watchdog timer L underflow sig- nal. The detection time is 131.072 ms at f(X IN)=8 MHz. When this bit is “1”, the count source becomes f(XIN)/16. In this case, the detection time is 512 µs at f(XIN)=8 MHz. This bit is cleared to “0” after reset. Operation of STP instruction disable bit When the watchdog timer is in operation, the STP instruction can be disabled by bit 6 of the watchdog timer control register (ad- dress 003916). When this bit is “0”, the STP instruction is enabled. When this bit is “1”, the STP instruction is disabled, and an inter- nal reset occurs if the STP instruction is executed. Once this bit is set to “1”, it cannot be changed to “0” by program. This bit is cleared to “0” after reset.Fig. 41 Block diagram of watchdog timer Fig. 42 Structure of watchdog timer control register XIN Data bus “0” “1”1/16 Watchdog timer H count source selection bit Reset circuit STP Instruction disable bit Watchdog timer H (8) Write "FF16" to the watchdog timer control register Internal resetRESET Watchdog timer L (8) STP Instruction Write “FF16” to the watchdog timer control register Watchdog timer control register (WDTCON: address 003916, initial value: 3F16) Watchdog timer H (read only for high-order 6-bit) STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(XIN)/16 b7 b0

Rev.2.00 Jun 21, 2004 The microcomputer is put into a reset status by holding the RE- SET pin at the “L” level for 2 µs or more when the power source voltage is 2.2 to 5.5 V and XIN is in stable oscillation. After that, this reset status is released by returning the RESET pin to the “H” level. The program starts from the address having the contents of address FFFD16 as high-order address and the con- tents of address FFFC16 as low-order address. In the case of f(φ) ≤ 6 MHz, the reset input voltage must be 0.9 V or less when the power source voltage passes 4.5 V. In the case of f(φ) ≤ 4 MHz, the reset input voltage must be 0.8 V or less when the power source voltage passes 4.0 V. In the case of f(φ) ≤ 2 MHz, the reset input voltage must be 0.48 V or less when the power source voltage passes 2.4 V. In the case of f(φ) ≤ 1 MHz, the reset input voltage must be 0.44 V or less when the power source voltage passes 2.2 V. Fig. 43 Example of reset circuit Fig. 44 Timing diagram at reset (Note)

0.2 VCC

Note : Reset release voltage Vcc = 2.2 V Data A d d r e s s 8 - 1 3 c l o c k c y c l e s R e s e t a d d r e s s f r o m t h e v e c t o r t a b l e 1 : A n o n - c h i p o s c i l l a t o r a p p l i e s a b o u t R I N G • 2 M H z , φ• 2 5 0 k H z f r e q u e n c y c l o c k a t a v e r a g e o f V c c V T h e m a r k m e a n s t h a t t h e a d d r e s s i s c h a n g e a b l e d e p e n d i n g o n t h e p r e v i o u s s t a t e T h e s e a r e a l l i n t e r n a l s i g n a l s e x c e p t R E S E T N o t e s ?? F F F CF F F D A D H , A D L??? C l o c k f r o m o n - c h i p o s c i l l a t o r R I N G φ R E S E T R E S E TO U T S Y N C

Rev.2.00 Jun 21, 2004 HARDWARE Fig. 45 Internal status of microcomputer at reset Prescaler 1 Timer 1 One-shot start register Timer X mode register Prescaler X Timer X Timer count source set register Serial I/O2 control register A/D control register MISRG Watchdog timer control register Interrupt edge selection register CPU mode register Interrupt request register 1 Interrupt control register 1 Processor status register Program counter (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) Contents of address FFFC16 (PCH ) (PCL) FF16 0116 0016 0016 FF16 FF16 0016 0016 1016 0016 002816 002916 002A16 002B16 002C 16 002D 16 002E16 003016 003416 003816 003916 003A16 003B16 003C 16 003E16 (PS) Note X : Undefined Contents of address FFFD16 0011 1111 0016 0016 0016 1000 0000 XXXX X1XX Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Pull-up control register (1) (2) (3) (4) (5) Register contents 0016 0016 0016 0016000116 000316 000516 000716 001616 Serial I/O1 control register UART control register (8) (9) Serial I/O1 status register(7) 001A16 001B16 0016 1110 0000 001916 1000 0000 XXX 0 0000 Address Port P1P3 control register (6) 001716 0016 Timer A mode register Timer A (low-order) Timer A (high-order) 0016 FF16 FF16 001D 16 001E16 001F16 Timer Y, Z mode register Prescaler Y Timer Y secondary 0016 FF16 FF16 002016 002116 002216 Timer Y primary Timer Y, Z waveform output control register Prescaler Z FF16 0016 FF16 002316 002416 002516 Timer Z secondary FF16002616 Timer Z primary FF16002716 (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) Serial I/O2 register 0016003116 Interrupt request register 2 003D 16 0016 Interrupt control register 2 003F16 0016 (37) (38) (39) (40)

Rev.2.00 Jun 21, 2004 Fig. 46 External circuit of ceramic resonator Fig. 47 External circuit of RC oscillation XIN C O U TC I N XO U T M 3 7 5 4 0 R d XI N XO U T C R M 3 7 5 4 0 Fig. 48 External clock input circuit XIN XO U T E x t e r n a l o s c i l l a t i o n c i r c u i t VCC VSS O p e n M37540 XI N XO U T M 3 7 5 4 0 O p e n Fig. 49 Processing of XIN and XOUT pins at on-chip oscillator operation Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator be- tween X IN and XOUT , and an RC oscillation circuit can be formed by connecting a resistor and a capacitor. Use the circuit constants in accordance with the resonator manufacturer's recommended values. (1) On-chip oscillator operation When the MCU operates by the on-chip oscillator for the main clock, connect X IN pin to VSS and leave XOUT pin open. The clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Ceramic resonator When the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins X IN and XOUT at the shortest distance. A feedback resistor is built in be- tween pins XIN and XOUT . (3) RC oscillation When the RC oscillation is used for the main clock, connect the XIN pin and XOUT pin to the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a micro- computer. So, set the constants within the range of the frequency limits. (4) External clock When the external signal clock is used for the main clock, connect the X IN pin to the clock source and leave XOUT pin open. Select “ceramic resonance” by setting “0” to the Oscillation mode selection bit of CPU mode register (address 003B 16). Externally connect a damping resistor Rd de- pending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manufacturer’s recom- mended value because constants such as ca- pacitance depend on the resonator. Note: Connect the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is af- fected by a capacitor, a resistor and a micro- computer. So, set the constants within the range of the frequency limits. Note: The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable fre- quencies and obtain the sufficient margin. Note:

Rev.2.00 Jun 21, 2004 HARDWARE G Oscillation stop detection circuit (Note) The oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or an oscillation circuit stops by discon- nection. When internal reset occurs, reset because of oscillation stop can be detected by setting “1” to the oscillation stop detection status bit. Also, when using the oscillation stop detection circuit, an on-chip oscillator is required. Figure 53 shows the state transition. Note: The oscillation stop detection circuit is not included in the emulator MCU “M37540RSS”. Fig. 50 Structure of MISRG MISRG(address 003816, initial value: 0016) b7 b0 Oscillation stabilization time set bit after release of the STP instruction 0: Set “0116” in timer1, and “FF16” in prescaler 1 automatically 1: Not set automatically Ceramic or RC oscillation stop detection function active bit 0: Detection function inactive 1: Detection function active Reserved bits (return “0” when read) (Do not write “1” to these bits) Not used (return “0” when read) Oscillation stop detection status bit 0: Oscillation stop not detected 1: Oscillation stop detected (1) Oscillation control

• Stop mode When the STP instruction is executed, the internal clock φ stops at an “H” level and the X IN oscillator stops. At this time, timer 1 is set to “0116” and prescaler 1 is set to “FF16” when the oscillation stabiliza- tion time set bit after release of the STP instruction is “0”. On the other hand, timer 1 and prescaler 1 are not set when the above bit is “1”. Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(X IN)/16 is forcibly connected to the input of prescaler 1. When an external interrupt is accepted, oscilla- tion is restarted but the internal clock φ remains at “H” until timer 1 underflows. As soon as timer 1 underflows, the internal clock φ is sup- plied. This is because when a ceramic oscillator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So apply an “L” level to the RESET pin while oscillation becomes stable. Also, the STP instruction cannot be used while CPU is operating by an on-chip oscillator.
• Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock re- starts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immedi- ately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to “1” before the STP or WIT instruction is executed. I Notes on clock generating circuit For use with the oscillation stabilization set bit after release of the STP instruction set to “1”, set values in timer 1 and prescaler 1 af- ter fully appreciating the oscillation stabilization time of the oscillator to be used.
• Switch of ceramic and RC oscillations After releasing reset the operation starts by starting an on-chip os- cillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register.
• Double-speed mode When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected.
• CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In or- der to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing re- set. After rewriting it is disable to write any data to the bit. (The emulator MCU “M37540RSS” is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are ex- ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
• Clock division ratio, X IN oscillation control, on-chip oscillator control The state transition shown in Fig. 52 can be performed by setting the clock division ratio selection bits (bits 7 and 6), X IN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 52.

Rev.2.00 Jun 21, 2004 Fig. 51 Block diagram of internal clock generating circuit (for ceramic resonator) Fig. 52 Block diagram of internal clock generating circuit (for RC oscillation) S R Q S R Q R SQ Rf 1 / 4 1/2 WIT instruction STP instruction T i m i n g φ I n t e r n a l c l o c k S T P i n s t r u c t i o n Interrupt request Reset Interrupt disable flag l High-speed mode M i d d l e - s p e e d m o d e P r e s c a l e r 1 Timer 1 Cl o c k d i v i s i o n r a t i o s e l e c t i o n b i t Double-speed mode On-chip oscillator modeO n - c h i p o s c i l l a t o r R I N G XOUTXI N Cl o c k d i v i s i o n r a t i o s e l e c t i o n b i t M i d d l e h i g h l o w s p e e d m o d e O n - c h i p o s c i l l a t o r m o d e R e s e t S R Q S R Q R SQ 1/4 1 / 2 WIT instruction STP instruction T i m i n g φ I n t e r n a l c l o c k STP instruction I n t e r r u p t r e q u e s t R e s e t I n t e r r u p t d i s a b l e f l a g l H i g h - s p e e d m o d e M i d d l e - s p e e d m o d e P r e s c a l e r 1 Timer 1 Clock division ratio selection bit D o u b l e - s p e e d m o d e O n - c h i p o s c i l l a t o r m o d eO n - c h i p o s c i l l a t o r R I N G XO U T XI N Delay Clock division ratio selection bit Middle-, high-, low-speed mode O n - c h i p o s c i l l a t o r m o d e R E S E T

Rev.2.00 Jun 21, 2004 HARDWARE Fig. 53 State transition S t o p m o d e Wait mode W I T i n s t r u c t i o n O s c i l l a t i o n s t o p d e t e c t i o n c i r c u i t v a l i d C P U M 4← 12 MISRG 1← 12 I n t e r r u p t I n t e r r u p t S T P i n s t r u c t i o n W I T i n s t r u c t i o n Interrupt MISRG 1← 02 C P U M 3← 12 C P U M 3← 02 C P U M 7 6← 1 C P U M 7 6← 0 N o t e C P U M 4← 02 M I S R G 1← 12 M I S R G 1← 02 R e s e t r e l e a s e d S t a t e 1 O p e r a t i o n c l o c k s o u r c e f (XI N ) N o t e f (XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r s t o p S t a t e 2 O p e r a t i o n c l o c k s o u r c e f (XI N ) N o t e f (XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r e n a b l e d State 3 Operation clock source: On-chip oscillator (Note 3) f(X IN) oscillation enabled On-chip oscillator enalbed S t a t e 4 O p e r a t i o n c l o c k s o u r c e O n c h i p o s c i l l a t o r N o t e f (XI N ) o s c i l l a t i o n s t o p O n c h i p o s c i l l a t o r e n a l b e d Notes on switch of clock (1) In operation clock source = f(XIN), the following can be selected for the CPU clock division ratio. G f(X IN)/2 (high-speed mode) G f(XIN)/8 (middle-speed mode) G f(XIN) (double-speed mode, only at a ceramic oscillation) (2) Execute the state transition state 3 to state 2 or state 3’ to state 2’ after stabilizing XIN oscillation. (3) In operation clock source = on-chip oscillator, the middle- speed mode is selected for the CPU clock division ratio. (4) When the state transition state 2 → state 3 → state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock.

• CPUM76 → 10 2 (State 2 → state 3)
• NOP instruction
• CPUM4 → 12 (State 3 → state 4) Double-speed mode at on-chip oscillator: NOP ✕ 3 High-speed mode at on-chip oscillator: NOP ✕ 1 Middle-speed mode at on-chip oscillator: NOP ✕ 0 Reset state C P U M 7 6← 1 C P U M 7 6← 0 N o t e S t a t e 2 ’ O p e r a t i o n c l o c k s o u r c e f (XI N ) N o t e f (XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r e n a b l e d S t a t e 3 ’ O p e r a t i o n c l o c k s o u r c e O n c h i p o s c i l l a t o r N o t e f XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r e n a l b e d

Rev.2.00 Jun 21, 2004 The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is “1”. After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations. Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction. Decimal Calculations

• For calculations in decimal notation, set the decimal mode flag D to “1”, then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD in- struction after executing one instruction before the ADC instruction or SBC instruction.
• In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid. Ports
• The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory opera- tion instruction when the T flag is “1”, addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA in- struction, etc. A/D Conversion Do not execute the STP instruction during A/D conversion. Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock φ by the number of cycles men- tioned in the machine-language instruction table. The frequency of the internal clock φ is the same as that of the X IN in double-speed mode, twice the XIN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode. CPU Mode Register The oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit. (Emulator MCU is ex- cluded.) When a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. Do not use it when an RC oscillation is selected. State transition Do not stop the clock selected as the operation clock because of setting of CM3, 4. NOTES ON HARDWARE Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic capacitor of 0.01 µF to 0.1 µF is recommended. One Time PROM Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 kΩ resistance. The mask ROM version track of CNVss pin has no operational in- terference even if it is connected via a resistor. NOTES ON PROGRAMMING/NOTES ON HARDWARE

Rev.2.00 Jun 21, 2004 HARDWARE NOTES ON PERIPHERAL FUNCTIONS I Interrupt When setting the followings, the interrupt request bit may be set to “1”.

• When switching external interrupt active edge Related register: Interrupt edge selection register (address 003A 16) Timer X mode register (address 2B16) Timer A mode register (address 1D16) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit (active edge switch bit). ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). I Timers
• When n (0 to 255) is written to a timer latch, the frequency divi- sion ratio is 1/(n+1).
• When a count source of timer X, timer Y or timer Z is switched, stop a count of timer X. I Timer A CNTR 1 interrupt active edge selection CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. When this bit is “0”, the CNTR 1 interrupt request bit is set to “1” at the falling edge of the CNTR1 pin input signal. When this bit is “1”, the CNTR 1 interrupt request bit is set to “1” at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR 1 pin input signal regardless of the setting of CNTR 1 active edge switch bit. I Timer X CNTR 0 interrupt active edge selection CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at the falling edge of CNTR0 pin input signal. When this bit is “1”, the CNTR 0 interrupt request bit is set to “1” at the rising edge of CNTR 0 pin input signal. I Timer Y: Programmable Generation Waveform Mode
• Count set value In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the set- ting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again.
• Write timing to TYP In the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function The waveform extension function by the timer Y waveform exten- sion control bit can be used only when “00 16” is set to Prescaler Y. When the value other than “0016” is set to Prescaler Y, be sure to set “0” to EXPYP and EXPYS.
• Timer Y write mode When using this mode, be sure to set “1” to the timer Y write con- trol bit to select “write to latch only”. Timer Y can stop counting by setting “1” to the timer Y count stop bit in any mode. Also, when Timer Y underflows, the timer Y interrupt request bit is set to “1”. Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) I Timer Z: Programmable Waveform Generation Mode
• Count set value In the programmable waveform generation mode, values of TZS, EXPZP, and EXPZS are valid by writing to TZP because the set- ting to them is executed all at once by writing to TZP. Even when changing TZP is not required, write the same value again.
• Write timing to TZP In the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function The waveform extension function by the timer Z waveform exten- sion control bit can be used only when “00 16” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used.
• Timer Z write mode When using this mode, be sure to set “1” to the timer Z write con- trol bit to select “write to latch only”. NOTES ON PERIPHERAL FUNCTIONS

Rev.2.00 Jun 21, 2004 I Timer Z: Programmable One-shot Generation Mode

• Count set value In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again.
• Write timing to TZP In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer un- derflow simultanesously.
• Usage of waveform extension function The waveform extension function by the timer Z waveform exten- sion control bit can be used only when “00 16” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used.
• Timer Z write mode When using this mode, be sure to set “1” to the timer Z write con- trol bit to select “write to latch only”. I Timer Z: Programmable Wait One-shot Generation Mode
• Count set value In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again.
• Write timing to TZP In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by soft- ware in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function The waveform extension function by the timer Z waveform exten- sion control bit can be used only when “00 16” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used.
• Timer Z write mode When using this mode, be sure to set “1” to the timer Z write con- trol bit to select “write to latch only”. Timer Z can stop counting by setting “1” to the timer Z count stop bit in any mode. Also, when Timer Z underflows, the timer Z interrupt request bit is set to “1”. Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) I Serial I/O
• Serial I/O interrupt When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➄ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O1 is enabled. The functions of P1 2 and P13 are switched with the setting values of a serial I/O1 mode selection bit and a serial I/O1 synchronous clock selection bit as follows. (1) Serial I/O1 mode selection bit → “1” : Clock synchronous type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0” : P1 2 pin turns into an output pin of a synchronous clock. “1” : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY) “0” : P1 3 pin can be used as a normal I/O pin. “1” : P13 pin turns into a SRDY output pin. (2) Serial I/O1 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0”: P1 2 pin can be used as a normal I/O pin. “1”: P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. I A/D Converter
• The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(X IN) is 500kHz or more during A/D conversion.
• As for AD translation accuracy, on the following operating condi- tions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensi- tive to noise when V REF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value. (2) When VREF voltage is lower than [3.0 V], the accuracy at the low temperature may become extremely low compared with that at room temperature When the system would be used at low temperature, the use at V REF =3.0 V or more is recom- mended. NOTES ON PERIPHERAL FUNCTIONS

Rev.2.00 Jun 21, 2004 HARDWARE I Notes on clock generating circuit For use with the oscillation stabilization set bit after release of the STP instruction set to “1”, set values in timer 1 and prescaler 1 af- ter fully appreciating the oscillation stabilization time of the oscillator to be used.

• Switch of ceramic and RC oscillations After releasing reset the operation starts by starting an on-chip os- cillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register.
• Double-speed mode When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected.
• CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In or- der to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing re- set. After rewriting it is disable to write any data to the bit. (The emulator MCU “M37540RSS” is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are ex- ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
• Clock division ratio, X IN oscillation control, on-chip oscillator control The state transition shown in Fig. 53 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 53.
• On-chip oscillator operation The clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. I Electric Characteristic Differences Among Mask ROM and One TIme PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM and One Time PROM version MCUs due to the differences in the manufac- turing processes. When manufacturing an application system with One Time PROM version and then switching to use of the mask ROM version, per- form sufficient evaluations for the commercial samples of the mask ROM version. NOTES ON PERIPHERAL FUNCTIONS I Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.

Rev.2.00 Jun 21, 2004 DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: 1.Mask ROM Order Confirmation Form * 2.Mark Specification Form * 3.Data to be written to ROM, in EPROM form (three identical cop- ies) or one floppy disk. DATA REQUIRED FOR ROM PROGRAMMING ORDERS The following are necessary when ordering a One Time PROM production: 1.ROM Programming Order Confirmation Form * 2.Mark Specification Form * 3.Data to be written to ROM, in EPROM form (three identical cop- ies) or one floppy disk. * For the mask ROM confirmation ROM programming order confir- mation and the mark specifications, refer to the “Renesas Technology Corp” Homepage (http://www.renesas.com/en/rom). ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To en- sure proper operation after programming, the procedure shown in Figure 54 is recommended to verify programming. Package 32P4B 32P6U-A 36P2R-A Name of Programming Adapter PCA7435SPG02 PCA7435GPG03 PCA7435FPG02 Table 7 Special programming adapter Fig. 54 Programming and testing of One Time PROM version Programming with PROM programmer Screening (Caution) (150 °C for 40 hours) Verification with PROM programmer Functional check in target device The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Caution: DATA REQUIRED FOR MASK ORDERS/DATA REQUIRED FOR ROM PROGRAMMING ORDERS/ ROM PROGRAMMING METHOD

Rev.2.00 Jun 21, 2004 HARDWARE 7540 group permits interrupts on the 14 sources for 42-pin version, 13 sources for 36-pin version and 12 sources for 32-pin version. It is vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. This priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to “Table 8.” Table 8 Interrupt sources, vector addresses and interrupt priority Vector addresses (Note 1) High-orderPriority Low-order Interrupt request generating conditions RemarksInterrupt source FFFC 16 FFFA 16 FFF8 16 FFF6 16 FFF4 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFE8 16 FFE6 16 FFE4 16 FFE2 16 FFE0 16 FFDE 16 FFDC 16 FFFD 16 FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF 16 FFDD 16 Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: It is an interrupt which can use only for 36 pin version. Non-maskable Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling) External interrupt (active edge selectable) External interrupt (active edge selectable) STP release timer underflow Non-maskable software interrupt At reset input At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or when transmit buffer is empty At detection of either rising or falling edge of INT 0 input At detection of either rising or falling edge of INT1 input At falling of conjunction of input logical level for port P0 (at input) At detection of either rising or falling edge of CNTR 0 input At detection of either rising or falling edge of CNTR 1 input At timer X underflow At timer Y underflow At timer Z underflow At timer A underflow At completion of transmit/receive shift At completion of A/D conversion At timer 1 underflow Not available At BRK instruction execution Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit INT0 INT1 (Note 3) Key-on wake-up CNTR CNTR 1 Timer X Timer Y Timer Z Timer A Serial I/O2 A/D conversion Timer 1 Reserved area BRK instruction FUNCTIONAL DESCRIPTION SUPPLEMENT

Rev.2.00 Jun 21, 2004 The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 55 shows a timing chart after an interrupt occurs, and Figure 56 shows the time up to execution of the interrupt processing routine. Fig. 55 Timing chart after an interrupt occurs Fig. 56 Time up to execution of the interrupt processing routine : CPU operation code fetch cycle : Vector address of each interrupt : Jump destination address of each interrupt : “00 16” or “0116” SYNC BL, BH AL, AH SPS Data bus Not used PC H PC L PS A L AH Address bus S, SPS S-2 , SPSS-1, SPSPC B L BH AL, AH SYNC RD WR φ Generation of interrupt request Main routine Interrupt processing routine 7 to 23 cycles (At performing 6.0 MHz, in double-speed mode, 1.75 µs to 5.75 µs) 2 cycles 5 cycles Start of interrupt processing 0 to 16 cycles Waiting time for post-processing of pipeline Stack push and Vector fetch FUNCTIONAL DESCRIPTION SUPPLEMENT

Rev.2.00 Jun 21, 2004 HARDWARE A/D conversion is started by setting AD conversion completion bit to “0.” During A/D conversion, internal operations are performed as follows. 1. After the start of A/D conversion, A/D conversion register goes to “0016.” 2. The highest-order bit of A/D conversion register is set to “1,” and the comparison voltage Vref is input to the comparator. Then, Vref is compared with analog input voltage V IN. 3. As a result of comparison, when Vref < VIN, the highest-order bit of A/D conversion register be- comes “1.” When Vref > VIN, the highest-order bit becomes “0.” By repeating the above operations up to the lowest- order bit of the A/D conversion register, an analog value converts into a digital value. A/D conversion completes at 122 clock cycles (20.34 µs at f(X IN) = 6.0 MHz) after it is started, and the result of the conversion is stored into the A/D conversion register. Concurrently with the completion of A/D conversion, A/D conversion interrupt request occurs, so that the AD conversion interrupt request bit is set to “1.” Relative formula for a reference voltage VREF of A/D converter and Vref When n = 0 Vref = 0 When n = 1 to 1023 Vref = ✕ n n : the value of A/D converter (decimal numeral) VREF 1024 ✽ 1–✽ 10: A result of the first to tenth comparison Table 9 Change of A/D conversion register during A/D conversion At start of conversion First comparison Second comparison Third comparison After completion of tenth comparison 100000 1000000 10000000 00000 00 0 V REF V REF V REF 2 84 V REF V REF V REF ± ± A result of A/D conversion ✽ 1 ✽ 1 ✽ 2 Change of A/D conversion register Value of comparison voltage (Vref) 000 ✽ 9 ✽ 10 2 10244 V REF V REF V REF

• ••
• ••
• •• FUNCTIONAL DESCRIPTION SUPPLEMENT

Rev.2.00 Jun 21, 2004 Figure 56 shows A/D conversion equivalent circuit, and Figure 57 shows A/D conversion timing chart. Fig. 57 A/D conversion equivalent circuit Fig. 58 A/D conversion timing chart ANi (i=0 to 7: 36-pin version i=0 to 5: 32-pin version) 12 pF(Typical) Notes 1: This is a parasitic diode. 2: Only the selected analog input pin is turned on. 1.5 pF(Typical) Chopper Amp. A/D control circuit Typical voltage generation circuit Switch tree, ladder resistor 1.5 kΩ (Typical) V SS VSS VCC VSS VREF R (Note 1) SW1 (Note 2) (Note 1) W r i t e s i g n a l f o r A / D c o n t r o l r e g i s t e r A D c o n v e r s i o n c o m p l e t i o n b i t S a m p l i n g c l o c k

122 XIN cycles

FUNCTIONAL DESCRIPTION SUPPLEMENT

2.1 I/O port

2.2 Timer A

2.3 Timer 1

2.4 Timer X

2.5 Timer Y and timer Z

2.6 Serial I/O1

2.7 Serial I/O2

2.8 A/D converter

2.9 Reset

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.1 I/O port This paragraph explains the registers setting method and the notes relevant to the I/O ports.

2.1.1 Memory map

Fig. 2.1.1 Memory map of registers relevant to I/O port 000016 000116 000216 000316 000416 000516 000616 000716 001616 001716 Pull-up control register (PULL) Port P1P3 control register (P1P3C) 003A16 Interrupt edge selection register (INTEDGE) 003C 16 Interrupt request register 1 (IREQ1) 003E16 Interrupt control register 1 (ICON1) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D)

Rev.2.00 Jun 21, 2004

2.1.2 Relevant registers

Fig. 2.1.2 Structure of Port Pi (i = 0, 2, 3) Port Pi b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port Pi0 Port Pi1 Port Pi2 Port Pi3 Port Pi4 Port Pi5 Port Pi6 Port Pi7 In output mode Write Read G Port latch In input mode Write : Port latch Read : Value of pins G Port Pi (Pi) (i = 0, 2, 3) [Address : 0016, 0416, 0616] Note: The 32-pin package versions have nothing to be allocated for the following:

• Bits 6 and 7 of port P2
• Bits 5 and 6 of port P3. Fig. 2.1.3 Structure of Port P1 Port P1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port P10 Port P11 Port P12 Port P13 Port P14 In output mode Write Read G Port latch In input mode Write : Port latch Read : Value of pins G Port P1 (P1) [Address : 0216] Nothing is allocated for these bits. When these bits are read out, the values are undefined.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.1 I/O port Fig. 2.1.4 Structure of Port Pi direction register (i = 0, 2, 3) Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port Pi direction register 0 Port Pi direction register (PiD) (i = 0, 2, 3) [Address : 0116, 0516, 0716] 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode Note: The 32-pin package versions have nothing to be allocated for the following:

• Bits 6 and 7 of P2D
• Bits 5 and 6 of P3D. Fig. 2.1.5 Structure of Port P1 direction register Port P1 direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port P1 direction register 0 Port P1 direction register (P1D) [Address : 0316] 0 : Port P10 input mode 1 : Port P10 output mode 0 : Port P11 input mode 1 : Port P11 output mode 0 : Port P12 input mode 1 : Port P12 output mode 0 : Port P13 input mode 1 : Port P13 output mode 0 : Port P14 input mode 1 : Port P14 output mode Nothing is allocated for these bits. When these bits are read out, the values are undefined.

Rev.2.00 Jun 21, 2004 Fig. 2.1.6 Structure of Pull-up control register P u l l u p c o n t r o l r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 B F u n c t i o n A t r e s e t RW Name P 00 p u l l - u p c o n t r o l b i t 0 P u l l - u p c o n t r o l r e g i s t e r ( P U L L ) [ A d d r e s s : 1 61 0 : P u l l - u p O f f P u l l u p O n Note: Pins set to output are disconnected from the pull-up control. P 01 p u l l - u p c o n t r o l b i t 0 : P u l l - u p O f f P u l l u p O n P 02, P 03 p u l l - u p c o n t r o l b i t 0 : P u l l - u p O f f P u l l u p O n P 04 – P 07 p u l l - u p c o n t r o l b i t 0 : P u l l - u p O f f P u l l u p O n P 30 – P 33 p u l l - u p c o n t r o l b i t 0 : P u l l - u p O f f P u l l u p O n P34 pull-up control bit 0 : P u l l - u p O f f P u l l u p O n P 35, P 36 p u l l - u p c o n t r o l b i t 0 : Pull-up Off 1 : Pull-up On P 37 p u l l - u p c o n t r o l b i t 0 : Pull-up Off 1 : Pull-up On Fig. 2.1.7 Structure of Port P1P3 control register Port P1P3 control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name P37/INT0 input level selection bit Port P1P3 control register (P1P3C) [Address : 1716] 0 : CMOS level 1 : TTL level P36/INT1 input level selection bit (Note) 0 : CMOS level 1 : TTL level P10, P12,P13 input level selection bit 0 : CMOS level 1 : TTL level Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Note: Keep setting the P36/INT1 input level selection bit to “0” (initial value) for the 32-pin package version.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.1 I/O port Fig. 2.1.8 Structure of Interrupt edge selection register Fig. 2.1.9 Structure of Interrupt request register 1 Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt edge selection register (INTEDGE) [Address : 3A16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. INT0 interrupt edge selection bit INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 1 (IREQ1) [Address : 3C16] Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued CNTR 0 interrupt request bit CNTR 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued INT0 interrupt request bit INT1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Key-on wake up interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Timer X interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued

Rev.2.00 Jun 21, 2004 Fig. 2.1.10 Structure of Interrupt control register 1 Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 1 (ICON1) [Address : 3E16] Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Timer X interrupt enable bit0 : Interrupt disabled 1 : Interrupt enabled

2.1.3 Application example of key-on wake up (1)

Outline: The built-in pull-up resistor is used. Specifications: System is returned from the wait mode when the key-on wakeup interrupt occurs by input of the falling edge to port P0i. Note: Only the falling edge is active for the key-on wakeup interrupt. Figure 2.1.11 shows an example of application circuit, and Figure 2.1.12 shows an example of control procedure. Fig. 2.1.11 Example of application circuit 7 5 4 0 G r o u p P0i(i:0 to 3) K e y O N P03 P02 P01 P00

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.1 I/O port Fig. 2.1.12 Example of control procedure (1) Key ON Key-on wakeup interrupt processing R T I S e t p u l l - u p c o n t r o l r e g i s t e r P U L L ( A d d r e s s 1 61 6)111 P 00 p u l l - u p O n P 01 p u l l - u p O n P 02, P 03 p u l l - u p O n S e t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r I N T E D G E ( A d d r e s s 3 A1 6)0 K e y - o n w a k e u p e n a b l e d Set “0” to the key-on wakeup interrupt request bit. WIT Power-down processing R E S E T 1 0 0 0 0 X 0 02C P U M ( A d d r e s s 3 B1 C L T C L D S E I W a i t u n t i l f ( XI N ) o s c i l l a t i o n i s s t a b i l i z e d (N o t e) X X 0 0 0 X 0 02C P U M( A d d r e s s 3 B1 CLI I n i t i a l i z a t i o n P r o c e s s i n g c o n t i n u e d S e t “ 1 ” t o t h e k e y - o n w a k e u p i n t e r r u p t e n a b l e b i t . k e y o n w a k e u p i n t e r r u p t e n a b l e d X: This bit is not used here. Set it to “0” or “1” arbitrary. Note: For the concrete time, ask the oscillator manufacture.

Rev.2.00 Jun 21, 2004 S e t p u l l - u p c o n t r o l r e g i s t e r , i f n e c e s s a r y PULL(Address 1616) P 00 p u l l - u p O n / O f f P p u l l u p O n O f f P 02, P p u l l u p O n O f f P 04– P p u l l u p O n O f f R T I CLI I N T E D G E ( A d d r e s s 3 A1 6)0 R E S E T S E I C L D C L T C P U M A d d r e s s B 6) ← X W a i t u n t i l f XI N ) o s c i l l a t i o n i s s t a b i l i z e d o t e C P U M A d d r e s s 6) ← X X X S e t p o r t P 0 i u s i n g k e y - o n w a k e u p i n t e r r u p t t o i n p u t m o d e . S e t p o r t n o t u s i n g k e y o n w a k e u p i n t e r r u p t t o o u t p u t m o d e S e t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r (N o t e 2) K e y - o n w a k e u p e n a b l e d Set “0” to the key-on wakeup interrupt request bit. Initialization S e t “ 1 ” t o t h e k e y - o n w a k e u p i n t e r r u p t e n a b l e b i t . k e y o n w a k e u p i n t e r r u p t e n a b l e d X: This bit is not used here. Set it to “0” or “1” arbitrary. N o t e s 1 : F o r t h e c o n c r e t e t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . I n t h i s c a s e p o r t P i s u s e d Key-on waleup interrupt processing routine P r o c e s s i n g Fig. 2.1.13 Example of control procedure (2)

2.1.4 Application example of key-on wake up (2)

Outline: The key-on wakeup interrupt is used as the normal external interrupt. Specifications: The key-on wakeup interrupt occurs by input of the falling edge to port P0i. If necessary, the built-in pull-up resistor is used. Note: Only the falling edge is active for the key-on wakeup interrupt. Figure 2.1.13 shows an example of control procedure.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.1 I/O port

2.1.5 Handling of unused pins

Table 2.1.1 Handling of unused pins Pins/Ports name P0, P1, P2, P3 V REF X IN X OUT Handling

• Set to the input mode and connect each to Vcc or Vss through a resistor of 1 kΩ to 10 kΩ .
• Set to the output mode and open at “L” or “H” level.
• Connect to Vss (GND).
• Connect to VSS (GND) when using an on-chip oscillator for main clock.
• Open when using an external clock.
• Open when using an on-chip oscillator for main clock.

Rev.2.00 Jun 21, 2004

2.1.6 Notes on input and output ports

Notes on using input and output ports are described below. (1) Notes in stand-by state In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O port “undefined”. Pull-up (connect the port to VCC ) or pull-down (connect the port to VSS ) these ports through a resistor. When determining a resistance value, note the following points:

• External circuit
• Variation of output levels during the ordinary operation When using a built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external. G Reason The output transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes “undefined” depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an I/O port are “undefined”. This may cause power source current. 1 stand-by state : the stop mode by executing the STP instruction the wait mode by executing the WIT instruction (2) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the unspecified bit may be changed. G Reason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port : The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port : The bit value of the port latch is read in the CPU, and is written to this bit after bit managing. Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. 2 bit managing instructions : SEB , and CLB instructions (3) Usage for the 32-pin version ➀ Fix the P35, P36 pull-up control bit of the pull-up control register to “1”. ➁ Keep the P36/INT1 input level selection bit of the port P1P3 control register “0” (initial state).

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.1 I/O port

2.1.7 Termination of unused pins

(1) Terminate unused pins ➀ I/O ports :

• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of 1 kΩ to 10 kΩ . Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/ O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) Termination remarks ➀ Input ports and I/O ports : Do not open in the input mode. G Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and ➂ shown on the above. ➁ I/O ports : When setting for the input mode, do not connect to V CC or VSS directly. G Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and VCC (or VSS ). ➂ I/O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. G Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins.

Rev.2.00 Jun 21, 2004 This paragraph explains the registers setting method and the notes relevant to the timer A.

2.2.1 Memory map

Port P0 direction register (P0D) Pull-up control register (PULL) Timer A mode register (TAM) Timer A (low-order) (TAL) Timer A (high-order) (TAH) 003C 16 003E16 Interrupt request register 1 (IREQ1) Interrupt control register 1 (ICON1) 003A16 Interrupt edge selection register (INTEDGE) Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2) 003D 16 003F16 Fig. 2.2.1 Memory map of registers relevant to timer A

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.2 Timer A

2.2.2 Relevant registers

Fig. 2.2.2 Structure of Port P0 direction register Port P0 direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port P0 direction register 0 Port P0 direction register (P0D) [Address : 0116] 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode Fig. 2.2.3 Structure of Pull-up control register P u l l u p c o n t r o l r e g i s t e r b7 b6 b5 b4 b3 b2 b1 b0 B F u n c t i o n At resetRW Name P00 pull-up control bit 0 Pull-up control register (PULL) [Address : 1616] 0 : P u l l - u p O f f P u l l u p O n N o t e : P i n s s e t t o o u t p u t a r e d i s c o n n e c t e d f r o m t h e p u l l - u p c o n t r o l . P 01 p u l l - u p c o n t r o l b i t 0 : P u l l - u p O f f P u l l u p O n P 02, P 03 p u l l - u p c o n t r o l b i t 0 : P u l l - u p O f f P u l l u p O n P 04 – P 07 p u l l - u p c o n t r o l b i t 0 : P u l l - u p O f f P u l l u p O n P 30 – P 33 p u l l - u p c o n t r o l b i t 0 : P u l l - u p O f f P u l l u p O n P 34 p u l l - u p c o n t r o l b i t 0 : P u l l - u p O f f P u l l u p O n P 35, P 36 p u l l - u p c o n t r o l b i t 0 : Pull-up Off 1 : Pull-up On P 37 p u l l - u p c o n t r o l b i t 0 : P u l l - u p O f f P u l l u p O n

Rev.2.00 Jun 21, 2004 Fig. 2.2.4 Structure of Timer A mode register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRWName Timer A mode register (TAM) [Address : 1D16] Timer A mode register 00 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode b5 b4 5 0 Timer A operating mode bits CNTR 1 active edge switch bitThe function depends on the operating mode. (Refer to Table 2.2.1) Timer A count stop bit 0 : Count start 1 : Count stop Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer A operating modes Timer mode Period measurement mode Event counter mode Pulse width HL continuously measurement mode CNTR 1 active edge switch bit (bit 6 of address 1D16) contents “0” CNTR 1 interrupt request occurrence: Falling edge ; No influence to timer count “1” CNTR 1 interrupt request occurrence: Rising edge ; No influence to timer count “0” Period measurement: Falling period measurement CNTR 1 interrupt request occurrence: Falling edge “1” Period measurement: Rising period measurement CNTR 1 interrupt request occurrence: Rising edge “0” Timer A: Rising edge count CNTR 1 interrupt request occurrence: Falling edge “1” Timer A: Falling edge count CNTR 1 interrupt request occurrence: Rising edge “0” CNTR1 interrupt request occurrence: Rising edge and Falling edge “1” CNTR1 interrupt request occurrence: Rising edge and Falling edge Table 2.2.1 CNTR1 active edge switch bit function

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.2 Timer A Fig. 2.2.5 Structure of Timer A register Fig. 2.2.6 Structure of Interrupt edge selection register Timer A register (low-order, high-order) b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer A register (low-order, high-order) (TAL, TAH) [Address : 1E16, 1F16]

• Set a count value of timer A.
• The value set in this register is written to both timer A and timer A latch at the same time.
• When this register is read out, the timer A’s count value is read out. Notes 1: Be sure to write to/read out both the low-order of timer A (TAL) and the high- order of timer A (TAH). 2: Read the high-order of timer A (TAH) first, and the high-order of timer A (TAL) next. 3: Write to the low-order of timer A (TAL) first, and the high-order of timer A (TAH) next. 4: Do not write to them during read, and do not read out them during write. Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt edge selection register (INTEDGE) [Address : 3A16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. INT0 interrupt edge selection bit INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled

Rev.2.00 Jun 21, 2004 Fig. 2.2.7 Structure of Interrupt request register 1 Fig. 2.2.8 Structure of Interrupt request register 2 Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 1 (IREQ1) [Address : 3C16] Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued CNTR 0 interrupt request bit CNTR 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued INT0 interrupt request bit INT1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Key-on wake up interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Timer X interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 2 (IREQ2) [Address : 3D16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer Y interrupt request bit Timer Z interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Timer 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued Timer A interrupt request bit Serial I/O2 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued AD converter interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.2 Timer A Fig. 2.2.9 Structure of Interrupt control register 1 Fig. 2.2.10 Structure of Interrupt control register 2 Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 1 (ICON1) [Address : 3E16] Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Timer X interrupt enable bit0 : Interrupt disabled 1 : Interrupt enabled Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 2 (ICON2) [Address : 3F16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer Y interrupt enable bit Timer Z interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Timer 1 interrupt enable bit Timer A interrupt enable bit Serial I/O2 interrupt enable bit AD conversion interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled

Rev.2.00 Jun 21, 2004

2.2.3 Timer mode

(1) Operation description Timer A counts the oscillation frequency divided by 16. Each time the count clock is input, the contents of Timer A is decremented by 1. When the contents of Timer A reach “000016”, an underflow occurs at the next count clock, and the timer A latch is reloaded into Timer A. The division ratio of Timer A is 1/(n+1) provided that the value of Timer A is n. Timer A can stop counting by setting “1” to the timer A count stop bit. Also, when Timer A underflows, the timer A interrupt request bit is set to “1”. (2) Timer mode setting method Figure 2.2.11 shows the setting method for timer mode of timer A.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.2 Timer A Fig. 2.2.11 Setting method for timer mode P r o c e s s 1 : D i s a b l e t i m e r A i n t e r r u p t . P r o c e s s 2 : S e t t i m e r A m o d e r e g i s t e r . b 7b 0

001 T i m e r A m o d e r e g i s t e r ( T A M ) [ A d d r e s s 1 D 1

P r o c e s s 3 : S e t t h e c o u n t v a l u e t o T i m e r A (N o t e) .

• S e t t h e c o u n t v a l u e t o t i m e r A ( l o w - o r d e r )
• S e t t h e c o u n t v a l u e t o t i m e r A ( h i g h - o r d e r ) T i m e r A ( l o w - o r d e r ) ( T A L ) ( A d d r e s s 1 E1 C o u n t v a l u e T i m e r A ( h i g h - o r d e r ) ( T A H ) ( A d d r e s s 1 F1 N o t e : W r i t e b o t h r e g i s t e r s i n o r d e r o f t i m e r X ( l o w - o r d e r ) a n d t i m e r X h i g h o r d e r f o l l o w i n g c e r t a i n l y P r o c e s s 4 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t n o r e q u e s t e d t o t h e t i m e r A i n t e r r u p t r e q u e s t b i t b 000 T i m e r m o d e T i m e r A c o u n t s t o p C o u n t v a l u e b 7b 0

0 I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1

T i m e r A i n t e r r u p t d i s a b l e d b

0 I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 3 D 1

b P r o c e s s 5 : W h e n T i m e r A i n t e r r u p t i s u s e d , s e t “ 1 ” ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r A i n t e r r u p t e n a b l e b i t N o t i m e r A i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 T i m e r A i n t e r r u p t e n a b l e d T i m e r A m o d e r e g i s t e r ( T A M ) [ A d d r e s s 1 D 1 T i m e r A c o u n t s t a r t P r o c e s s 6 : S t a r t c o u n t i n g o f T i m e r A .

Rev.2.00 Jun 21, 2004 (3) Application example of timer mode Outline: The input clock is divided by the timer so that the period processing is executed every 25 ms intervals. Specifications: •The f(XIN) = 8 MHz is divided by timer A to detect 25 ms.

• The timer A interrupt request is confirmed in the main routine. When 25 ms has elapsed, the period processing is executed in the timer A interrupt processing routine.
• Operation clock: f(XIN) = 8 MHz, high-speed mode Figure 2.2.12 shows an example of control procedure. Fig. 2.2.12 Example of control procedure S e t “ 0 ” t o t h e t i m e r A i n t e r r u p t e n a b l e b i t . T i m e r A i n t e r r u p t d i s a b l e d “ D 31 “ 3 01 T i m e r A ( l o w - o r d e r ) ( A d d r e s s 1 E1 S e t v a l u e t o t i m e r A (N o t e s 2 , 3) 0 0 S e t “ 0 ” t o t h e t i m e r A i n t e r r u p t r e q u e s t b i t . C L I

0 T A M ( A d d r e s s 1 D 1

T i m e r A c o u n t s t o p S e t t i m e r A m o d e r e g i s t e r I n i t i a l i z a t i o n R E S E T S E I C L D C L T C P U M A d d r e s s 6) ← X W a i t u n t i l f XI N ) o s c i l l a t i o n i s s t a b i l i z e d o t e C P U M A d d r e s s 6) ← X P r o c e s s i n g T i m e r A i n t e r r u p t p r o c e s s i n g r o u t i n e Periodic processing R T I T i m e r A ( h i g h - o r d e r ) ( A d d r e s s 1 F1 S e t “ 1 ” t o t h e t i m e r A i n t e r r u p t e n a b l e b i t . T i m e r A i n t e r r u p t e n a b l e d T A M ( A d d r e s s 1 D 1 T i m e r A c o u n t s t a r t S e t t i m e r A m o d e r e g i s t e r X: T h i s b i t i s n o t u s e d h e r e . S e t i t t o “ 0 ” o r “ 1 ” a r b i t r a r y . Notes 1: For the concrete time, ask the oscillator manufacture. 2: When setting the value to Timer A, set in order of low-order byte and high-order byte following. 3: 25 ms = 1/8 MHz ✕ 16 ✕ (30D316 + 1) T i m e r A d i v i s i o n r a t i o f i x e d T i m e r A s e t t i n g v a l u e

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.2 Timer A Fig. 2.2.13 Setting method for period measurement mode (1)

2.2.4 Period measurement mode

(1) Operation description In the period measurement mode, the pulse period input from the P00/CNTR 1 pin is measured. CNTR 1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in the timer A latch is reloaded in Timer A and count continues. The active edge of CNTR1 pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit. The count value when trigger input from CNTR1 pin is accepted is retained until Timer A is read once. Timer A can stop counting by setting “1” to the timer A count stop bit. Also, when Timer A underflows, the timer A interrupt request bit is set to “1”. (2) Period measurement mode setting method b b 101 b7 b0 b b P r o c e s s 1 : D i s a b l e t i m e r A i n t e r r u p t a n d C N T R 1 i n t e r r u p t . I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E1 C N T R 1 i n t e r r u p t d i s a b l e d P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D ) [ A d d r e s s 0 11 S e t t h e P 00/ C N T R 1 p i n t o t h e i n p u t m o d e P r o c e s s 2 : S e t t h e C N T R 1 p i n t o t h e i n p u t m o d e . I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 T i m e r A i n t e r r u p t d i s a b l e d Process 3: Set pull-up control register. P u l l - u p c o n t r o l r e g i s t e r ( P U L L ) [ A d d r e s s 1 61 P 00/ C N T R 1 p u l l - u p c o n t r o l b i t P u l l u p O f f P u l l u p O n P r o c e s s 4 : S e t t i m e r A m o d e r e g i s t e r . T i m e r A m o d e r e g i s t e r ( T A M ) [ A d d r e s s 1 D 1 P e r i o d m e a s u r e m e n t m o d e C N T R 1 a c t i v e e d g e s e l e c t e d F a l l i n g p e r i o d m e a s u r e d F a l l i n g e d g e a c t i v e f o r C N T R 1 i n t e r r u p t R i s i n g p e r i o d m e a s u r e d R i s i n g e d g e a c t i v e f o r C N T R 1 i n t e r r u p t T i m e r A c o u n t s t o p

Rev.2.00 Jun 21, 2004 Fig. 2.2.14 Setting method for period measurement mode (2) b b b b7 b0 b 100 b P r o c e s s 5 : S e t t h e c o u n t v a l u e t o t i m e r A (N o t e) .

• S e t t h e i n i t i a l v a l u e t o t i m e r A ( l o w - o r d e r ) T i m e r A ( l o w - o r d e r ) ( T A L ) ( A d d r e s s 1 E1 I n i t i a l v a l u e T i m e r A ( h i g h - o r d e r ) ( T A H ) ( A d d r e s s 1 F1 N o t e : W r i t e b o t h r e g i s t e r s i n o r d e r o f t i m e r X ( l o w - o r d e r ) a n d t i m e r X ( h i g h - o r d e r ) f o l l o w i n g , c e r t a i n l y . Process 7: In order not to execute the no requested interrupt processing, set “0” (no requested) to the timer A interrupt request bit and CNTR1 interrupt request bit. I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 3 C 1 P r o c e s s 8 : W h e n t h e i n t e r r u p t i s u s e d , s e t “ 1 ” ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r A i n t e r r u p t e n a b l e b i t o r C N T R 1 i n t e r r u p t e n a b l e b i t N o C N T R 1 i n t e r r u p t r e q u e s t i s s u e d Interrupt control register 2 (ICON2) [Address 3F16] Timer A interrupt enabled T i m e r A m o d e r e g i s t e r ( T A M ) [ A d d r e s s 1 D 1 T i m e r A c o u n t s t a r t P r o c e s s 9 : S t a r t c o u n t i n g o f t i m e r A . I n i t i a l v a l u e
• Set the initial value to timer A (high-order) Interrupt request register 2 (IREQ2) [Address 3D16] N o t i m e r A i n t e r r u p t r e q u e s t i s s u e d Interrupt control register 1 (ICON1) [Address 3E16] CNTR 1 interrupt enabled I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E ) [ A d d r e s s 3 A1 Key-on wakeup disabled P r o c e s s 6 : I n o r d e r t o u s e t h e C N T R 1 p i n f u n c t i o n o f t h e P 00/ C N T R 1 p i n , d i s a b l e t h e P 00 k e y - o n w a k e u p f u n c t i o n .

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.2 Timer A (3) Application example of period measurement mode Outline: The phase control signal is adjusted by using the period measurement mode. Specifications: • The phase control signal is output to a load, and that controls the phase of a load.

• The period of the pulse input to the P00/CNTR 1 pin from the load as a feedback signal is measured. The correct of the phase control signal to the load is executed using this result. The input pulse period is set to be less than the period of timer A. When timer A underflows, the period is recognized as not corrected, and error processing is executed in the timer A interrupt processing routine.
• Operation clock: f(X IN) = 8 MHz, high-speed mode Figure 2.2.15 shows an example of a peripheral circuit, and Figure 2.2.16 shows an example of control procedure. Fig. 2.2.15 Example of peripheral circuit Load

Rev.2.00 Jun 21, 2004 Fig. 2.2.16 Example of control procedure “FF16” “ F F1 Set timer A mode register

0 TAM(Address 1D16)

T i m e r A c o u n t s t a r t C L I R E S E T S E I C L D C L T C P U M A d d r e s s 6) ← X W a i t u n t i l f XI N ) o s c i l l a t i o n i s s t a b i l i z e d o t e C P U M A d d r e s s 6) ← X Processing Timer A interrupt processing routine Error processing R T I P e r i o d m e a s u r e m e n t m o d e R i s i n g p e r i o d m e a s u r e d R i s i n g e d g e a c t i v e f o r C N T R 1 i n t e r r u p t T i m e r A c o u n t s t o p Set timer A mode register 1 1 S e t p o r t P 00 t o t h e i n p u t m o d e . PULL(Address 1616) P00 pull-up control bit 0: Pull-up Off 1: Pull-up On Set pull-up control register CNTR 1 interrupt processing routine Read timer A (Note 3) R T I Error processing at incorrect period input INTEDGE(Address 3A16) K e y - o n w a k e u p d i s a b l e d CNTR 1 interrupt processing Timer A interrupt processing S e t “ 0 ” t o t h e C N T R 1 i n t e r r u p t e n a b l e b i t . C N T R 1 i n t e r r u p t d i s a b l e d S e t t o t h e t i m e r A i n t e r r u p t e n a b l e b i t T i m e r A i n t e r r u p t d i s a b l e d I n i t i a l i z a t i o n X : T h i s b i t i s n o t u s e d h e r e . S e t i t t o “ 0 ” o r “ 1 ” a r b i t r a r y . Notes 1: For the concrete time, ask the oscillator manufacture. 2: When setting the value to timer A, set in order of low-order byte and high-order byte following. 3: When reading a value of timer A, read in order of high-order byte and low-order byte following. Timer A (low-order) (Address 1E16) S e t v a l u e t o t i m e r A (N o t e 2) Timer A (high-order) (Address 1F16) Set interrupt edge selection register Set “1” to the CNTR1 interrupt enable bit. (CNTR 1 interrupt enabled) Set “1” to the timer A interrupt enable bit. (Timer A interrupt enabled) Set “0” to the CNTR1 interrupt request bit. Set “0” to the timer A interrupt request bit.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.2 Timer A Fig. 2.2.17 Setting method for event counter mode (1)

2.2.5 Event counter mode

(1) Operation description Timer A counts signals input from the P00/CNTR 1 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR1 pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit. Timer A can stop counting by setting “1” to the timer A count stop bit. Also, when Timer A underflows, the timer A interrupt request bit is set to “1”. (2) Event counter mode setting method b b b7 b b b P r o c e s s 1 : D i s a b l e t i m e r A i n t e r r u p t a n d C N T R 1 i n t e r r u p t . I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E1 CNTR 1 interrupt disabled P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D ) [ A d d r e s s 0 11 S e t t h e P 00/ C N T R 1 p i n t o t h e i n p u t m o d e P r o c e s s 2 : S e t t h e C N T R 1 p i n t o t h e i n p u t m o d e . I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 Timer A interrupt disabled P r o c e s s 3 : S e t p u l l - u p c o n t r o l r e g i s t e r . P u l l - u p c o n t r o l r e g i s t e r ( P U L L ) [ A d d r e s s 1 61 P 00/ C N T R 1 p u l l u p c o n t r o l b i t P u l l u p O f f P u l l u p O n P r o c e s s 4 : S e t t i m e r A m o d e r e g i s t e r . Timer A mode register (TAM) [Address 1D16] Event counter mode CNTR 1 active edge selected 0: Rising period measured Falling edge active for CNTR1 interrupt 1: Falling period measured Rising edge active for CNTR1 interrupt Timer A count stop P r o c e s s 5 : S e t t h e c o u n t v a l u e t o t i m e r A (N o t e) .

• S e t t h e c o u n t v a l u e t o t i m e r A ( l o w - o r d e r ) T i m e r A ( l o w - o r d e r ) ( T A L ) ( A d d r e s s 1 E1 C o u n t v a l u e T i m e r A ( h i g h - o r d e r ) ( T A H ) ( A d d r e s s 1 F1 N o t e : W r i t e b o t h r e g i s t e r s i n o r d e r o f t i m e r X ( l o w - o r d e r ) a n d t h e t i m e r X ( h i g h - o r d e r ) f o l l o w i n g , c e r t a i n l y . C o u n t v a l u e
• S e t t h e c o u n t v a l u e t o t i m e r A ( h i g h - o r d e r )

Rev.2.00 Jun 21, 2004 Fig. 2.2.18 Setting method for event counter mode (2) b 7b 0 b 7b 0 010 b 7b 0 b 7b 0 b 7b 0 b7 b0 P r o c e s s 7 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t “ 0 ” ( n o r e q u e s t e d ) t o t h e t i m e r A i n t e r r u p t r e q u e s t b i t a n d C N T R 1 i n t e r r u p t r e q u e s t b i t I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 3 C 1 Process 8: When the interrupt is used, set “1” (interrupt enabled) to the timer A interrupt enable bit or CNTR1 interrupt enable bit. N o C N T R 1 i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 Timer A interrupt enabled T i m e r A m o d e r e g i s t e r ( T A M ) [ A d d r e s s 1 D 1 T i m e r A c o u n t s t a r t Process 9: Start counting of timer A. I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 3 D 1 N o t i m e r A i n t e r r u p t r e q u e s t i s s u e d Interrupt control register 1 (ICON1) [Address 3E16] CNTR 1 interrupt enabled I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E ) [ A d d r e s s 3 A1 Key-on wakeup disabled Process 6: In order to use the CNTR1 pin function of the P00/CNTR 1 pin, disable the P00 key-on wakeup function.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.2 Timer A (3) Application example of event counter mode Outline: The frequency of the pulse which is input to the P00/CNTR 1 pin (“H” active) is measured by the number of events in a certain period. Specifications: The count source of timer A is input from the P00/CNTR 1 pin, and the timer A starts counting the count source. Clock (f(XIN) = 8 MHz) is divided by timer X to detect 1 ms. The frequency of the pulse input to the P00/CNTR 1 pin is calculated by the number of events counted within 1 ms. Operation clock: f(XIN) = 8 MHz, high-speed mode Figure 2.2.19 shows an example of measurement method of frequency, and Figure 2.2.20 shows an example of control procedure. Fig. 2.2.19 Example of measurement method of frequency N o t e s 1 : C o u n t e d a t f a l l i n g e d g e . F r e q u e n c y o f p u l s e i n p u t f r o m P 00/ C N T R 1 p i n T i m e r X i n t e r r u p t p r o c e s s i n g r o u t i n e T i m e r A T i m e r X c o u n t s t o p T i m e r A r e a d T i m e r A T i m e r X s e t a g a i n T i m e r A T i m e r X c o u n t r e s t a r t P00/CNTR 1 pin input T i m e r X i n t e r r u p t r e q u e s t b i t 1ms Counted by Timer A (Note 1) X times (Note 2)Timer A, Timer X count start kHzX times 1ms

Rev.2.00 Jun 21, 2004 Fig. 2.2.20 Example of control procedure ( T i m e r A s e t t i n g v a l u e “ F F F F1 6” ) – ( T i m e r A c o u n t v a l u e e v e n t i n m s Timer X interrupt processing routine (1ms interrupt) “FF16” “ F F1 1 0 C L I RESET S E I C L D C L T C P U M A d d r e s s 6) ← 1 X f XI N ) u n t i l f XI N ) o s c i l l a t i o n i s s t a b i l i z e d o t e C P U M A d d r e s s 6) ← 0 X Processing “FF16” “FF16” 1 01 1 S e t t i m e r X m o d e r e g i s t e r T X M ( A d d r e s s 2 B1 T i m e r m o d e T i m e r X c o u n t s t o p 10 0 “ 0 11 “ F 91 Set timer count source set register TCSS(Address 2E16) T i m e r X c o u n t s o u r c e : f XI N ) s e l e c t e d 00 0 TXM(Address 2B16)00 0 T X M ( A d d r e s s 2 B1 6)10 0 TAM(Address 1D16) TXM(Address 2B16) 0110 0 00 R T I T A M ( A d d r e s s 1 D 1 6)0111 “ 0 11 “1816” S e t t i m e r A m o d e r e g i s t e r T A M ( A d d r e s s 1 D 1 Timer A count start T A M ( A d d r e s s 1 D 1 E v e n t c o u n t m o d e C o u n t a t f a l l i n g e d g e T i m e r A c o u n t s t o p S e t t i m e r A m o d e r e g i s t e r S e t p o r t P 00 t o t h e i n p u t m o d e . P U L L ( A d d r e s s 1 61 P 00 p u l l - u p c o n t r o l b i t P u l l u p O f f P u l l u p O n S e t p u l l - u p c o n t r o l r e g i s t e r I N T E D G E ( A d d r e s s 3 A1 Key-on wakeup disabled S e t “ 0 ” t o t h e C N T R 1 i n t e r r u p t e n a b l e b i t . C N T R 1 i n t e r r u p t d i s a b l e d S e t t o t h e t i m e r A i n t e r r u p t e n a b l e b i t T i m e r A i n t e r r u p t d i s a b l e d S e t t o t h e t i m e r X i n t e r r u p t e n a b l e b i t T i m e r X i n t e r r u p t d i s a b l e d I n i t i a l i z a t i o n X : T h i s b i t i s n o t u s e d h e r e . S e t i t t o “ 0 ” o r “ 1 ” a r b i t r a r y . N o t e s 1 : F o r t h e c o n c r e t e t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . W h e n s e t t i n g t h e v a l u e t o t i m e r s e t i n o r d e r o f l o w o r d e r b y t e a n d h i g h o r d e r b y t e f o l l o w i n g m s d e t e c t i o n M H z F T i m e r A ( l o w - o r d e r ) ( A d d r e s s 1 E1 Set value to timer A (Note 2) T i m e r A ( h i g h - o r d e r ) ( A d d r e s s 1 F1 S e t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r Set “1” to the timer X interrupt enable bit. (Timer X interrupt enabled) S e t “ 0 ” t o t h e t i m e r X i n t e r r u p t r e q u e s t b i t . Prescaler X (Address 2C 16) Set value to timer X (Note 3) T i m e r X ( A d d r e s s 2 D 1 S e t t i m e r X m o d e r e g i s t e r T i m e r X c o u n t s t a r t Set timer A mode register Timer A count start Set timer X mode register T i m e r X c o u n t s t a r t Set timer A mode register T i m e r A c o u n t s t o p Set timer X mode register T i m e r X c o u n t s t o p T i m e r A ( l o w - o r d e r ) ( A d d r e s s 1 E1 Set value to timer A (Note 2) T i m e r A ( h i g h - o r d e r ) ( A d d r e s s 1 F1 P r e s c a l e r X ( A d d r e s s 2 C 1 Set value to timer X (Note 3) T i m e r X ( A d d r e s s 2 D 1 T i m e r X d i v i s i o n r a t i o T i m e r X s e t t i n g v a l u e P r e s c a l e r X s e t t i n g v a l u e

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.2 Timer A Fig. 2.2.21 Setting method for pulse width HL continuously measurement mode (1)

2.2.6 Pulse width HL continuously measurement mode

(1) Operation description In the pulse width HL continuously measurement mode, the pulse width (“H” and “L” levels) input to the P0 0/CNTR 1 pin is measured. CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. The count value when trigger input from the CNTR1 pin is accepted is retained until Timer A is read once. Timer A can stop counting by setting “1” to the timer A count stop bit. Also, when Timer A underflows, the timer A interrupt request bit is set to “1”. (2) Pulse width HL continuously measurement mode setting method Figure 2.2.21 and Figure 2.2.22 show the setting method for pulse width HL continuously measurement mode of timer A. b 7b 0 b 11 1 b b b P r o c e s s 1 : D i s a b l e t i m e r A i n t e r r u p t a n d C N T R 1 i n t e r r u p t . I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E1 C N T R 1 i n t e r r u p t d i s a b l e d Port P0 direction register (P0D) [Address 0116] S e t t h e P 00/ C N T R 1 p i n t o t h e i n p u t m o d e P r o c e s s 2 : S e t t h e C N T R 1 p i n t o t h e i n p u t m o d e . I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 T i m e r A i n t e r r u p t d i s a b l e d P r o c e s s 3 : S e t t h e p u l l - u p c o n t r o l r e g i s t e r . P u l l - u p c o n t r o l r e g i s t e r ( P U L L ) [ A d d r e s s 1 61 P 00/ C N T R 1 p u l l - u p c o n t r o l b i t P u l l u p O f f P u l l u p O n P r o c e s s 4 : S e t t i m e r A m o d e r e g i s t e r . T i m e r A m o d e r e g i s t e r ( T A M ) [ A d d r e s s 1 D 1 Pulse width HL continuously measurement mode Timer A count stop P r o c e s s 5 : S e t t h e c o u n t v a l u e t o t i m e r A (N o t e) .

• S e t t h e i n i t i a l v a l u e t o t i m e r A ( l o w - o r d e r ) Timer A (low-order) (TAL) (Address 1E16) I n i t i a l v a l u e Timer A (high-order) (TAH) (Address 1F16) Note: Write both registers in order of timer X (low-order) and the timer X (high-order) following, certainly. I n i t i a l v a l u e
• S e t t h e i n i t i a l v a l u e t o t i m e r A ( h i g h - o r d e r )

Rev.2.00 Jun 21, 2004 Fig. 2.2.22 Setting method for pulse width HL continuously measurement mode (2) b7 b0 b b b b7 b0 0 11 b7 b0 P r o c e s s 7 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t “ 0 ” ( n o r e q u e s t e d ) t o t h e t i m e r A i n t e r r u p t r e q u e s t b i t a n d C N T R 1 i n t e r r u p t r e q u e s t b i t o t I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 3 C 1 Process 8: When the interrupt is used, set “1” (interrupt enabled) to the timer A interrupt enable bit or CNTR1 interrupt enable bit. N o C N T R 1 i n t e r r u p t r e q u e s t i s s u e d Interrupt control register 2 (ICON2) [Address 3F16] Timer A interrupt enabled T i m e r A m o d e r e g i s t e r ( T A M ) [ A d d r e s s 1 D 1 Timer A count start P r o c e s s 9 : S t a r t c o u n t i n g o f t i m e r A . I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 3 D 1 N o t i m e r A i n t e r r u p t r e q u e s t i s s u e d Interrupt control register 1 (ICON1) [Address 3E16] CNTR 1 interrupt enabled I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E ) [ A d d r e s s 3 A1 K e y - o n w a k e u p d i s a b l e d P r o c e s s 6 : I n o r d e r t o u s e t h e C N T R 1 p i n f u n c t i o n o f t h e P 00/ C N T R 1 p i n , d i s a b l e t h e P 00 k e y - o n w a k e u p f u n c t i o n . N o t e : I n t h e p u l s e w i d t h H L c o n t i n u o u s l y m e a s u r e m e n t m o d e , t h e C N T R 1 i n t e r r u p t r e q u e s t o c c u r s a t t h e r i s i n g e d g e a n d f a l l i n g e d g e o f t h e P 00/ C N T R 1 p i n r e g a r d l e s s o f t h e v a l u e o f t h e P 00/ C N T R 1 a c t i v e e d g e s w i t c h b i t o f t h e t i m e r A m o d e r e g i s t e r

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.2 Timer A (3) Application example of pulse width HL continuously measurement mode Outline: A telephone ringing (calling) pulse* is detected by using the pulse width HL continuously measurement mode. * Signal which is sent by turning on/off (make/break) the telephone line. Each country has a different standard. In this case, Japanese domestic standard is adopted as an example. Specifications: Whether a telephone call exists or not is judged by measuring a pulse width output from the ringing signal detection circuit. f(XIN)/16 (f(XIN) = 6.4 MHz) is used as the count source, and “H” and “L” pulse width of the ringing pulse are measured by using the pulse width HL continuously measurement mode. When the following conditions are satisfied, it is recognized as a normal value. When the following conditions are not satisfied, it is recognized as an unusual value. 200 ms ≤ “H” pulse width of ringing pulse < 1.2 s 600 ms ≤ “L” pulse width of ringing pulse < 2.2 s 1.0 s ≤ one period (“H” pulse width + “L” pulse width) < 3.0 s Operation clock: f(X IN) = 6.4 MHz, high-speed mode Figure 2.2.23 shows an example of a peripheral circuit, and Figure 2.2.24 shows an operation timing Fig. 2.2.23 Example of peripheral circuit 7 5 4 0 G r o u p P00/CNTR 1 Ringing pulse detection circuit T e l e p h o n e l i n e Fig. 2.2.24 Operation timing when ringing pulse is input I n p u t s i g n a l t o P 00/ C N T R 1 p i n T i m e r A v a l u e T i m e r A i n t e r r u p t r e q u e s t C N T R 1 i n t e r r u p t r e q u e s t “H” width measurement end 4 to 23 interrupts occur 12 to 43 interrupts occur p e r i o d 20 to 59 interrupts occur (1.0 s to 3.0 s) R i n g i n g d u r a t i o n m s t o s N o r i n g i n g d u r a t i o n m s t o s G W h e n a n o r m a l r a n g e r i n g i n g p u l s e i s i n p u t R e l o a d R e l o a d L w i d t h m e a s u r e m e n t e n d

Rev.2.00 Jun 21, 2004 Fig. 2.2.25 Example of control procedure (1) “ 1 F1 “4E16” 1 1 C L I R E S E T Timer A division ratio (fixed) Timer A setting value S E I C L D C L T C P U M A d d r e s s 6) ← X W a i t u n t i l f XI N ) o s c i l l a t i o n i s s t a b i l i z e d o t e C P U M A d d r e s s 6) ← X 1 11 N Y CNTR 1 interrupt occurs at rising edge and falling edge of waveform which is input to P00/CNTR 1 pin Timer A interrupt occurs at timer A underflow (at every 50 ms) A ringing pulse exists ? (Ringer flag = “1”?) Processing when a ringing pulse exists Main processing M a i n p r o c e s s i n g S e t t i m e r A m o d e r e g i s t e r T A M ( A d d r e s s 1 D 1 T i m e r A c o u n t s t a r t T A M ( A d d r e s s 1 D 1 P u l s e w i d t h H L c o n t i n u o u s l y m e a s u r e m e n t m o d e T i m e r A c o u n t s t o p S e t t i m e r A m o d e r e g i s t e r S e t p o r t P 00 t o t h e i n p u t m o d e . P U L L ( A d d r e s s 1 61 P 00 p u l l - u p c o n t r o l b i t P u l l u p O f f P u l l u p O n S e t p u l l - u p c o n t r o l r e g i s t e r I N T E D G E ( A d d r e s s 3 A1 K e y - o n w a k e u p d i s a b l e d C N T R 1 i n t e r r u p t p r o c e s s i n g Timer A interrupt processing S e t “ 0 ” t o t h e t i m e r A i n t e r r u p t e n a b l e b i t . T i m e r A i n t e r r u p t d i s a b l e d S e t t o t h e C N T R 1 i n t e r r u p t e n a b l e b i t C N T R 1 i n t e r r u p t d i s a b l e d I n i t i a l i z a t i o n X: This bit is not used here. Set it to “0” or “1” arbitrary. Notes 1: For the concrete time, ask the oscillator manufacture. 2: When setting the value to timer A, set in order of low-order byte and high-order byte following. 3: 50 ms = 1/6.4 MHz ✕ 16 ✕ (4E1F16 + 1) T i m e r A ( l o w - o r d e r ) ( A d d r e s s 1 E1 Set value to timer A (Notes 2, 3) T i m e r A ( h i g h - o r d e r ) ( A d d r e s s 1 F1 S e t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r S e t “ 1 ” t o t h e C N T R 1 i n t e r r u p t e n a b l e b i t . C N T R 1 i n t e r r u p t e n a b l e d S e t t o t h e t i m e r A i n t e r r u p t e n a b l e b i t T i m e r A i n t e r r u p t e n a b l e d Set “0” to the CNTR1 interrupt request bit. Set “0” to the timer A interrupt request bit.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.2 Timer A Fig. 2.2.26 Example of control procedure (2) C N T R 1 i n t e r r u p t p r o c e s s i n g r o u t i n e T h e n u m b e r o f u n d e r f l o w i s w i t h i n t h e r a n g e ? o r m o r e a n d l e s s t h a n N N Y Y When judging that a ringing pulse exists as a result of several period measurement, set “1” to the ringing flag. N Set “0” to the “H” width decision flag and the “L” width decision flag. * Error processing W h e n P 00/ C N T R 1 = “ 0 ” , H d u r a t i o n m e a s u r i n g i s f i n i s h e d Y * Error processing Set “1” to the unusual value detection flag RTI T h e n u m b e r o f a p e r i o d ’ s u n d e r f l o w i s w i t h i n t h e r a n g e o r m o r e a n d l e s s t h a n Timer A interrupt processing routine Count the number of underflows RTI Set “1” to the “L” width decision flag.S e t “ 1 ” t o t h e “ H ” w i d t h d e c i s i o n f l a g . T h e n u m b e r o f u n d e r f l o w i s w i t h i n t h e r a n g e ? o r m o r e a n d l e s s t h a n L e v e l o f P 00/ C N T R 1 i s c h e c k e d , a n d w h i c h d u r a t i o n m e a s u r i n g i s f i n i s h e d i s j u d g e d . W h e n P 00/ C N T R 1 = “ 1 ” , L d u r a t i o n m e a s u r i n g i s f i n i s h e d

Rev.2.00 Jun 21, 2004

2.2.7 Notes on timer A

Notes on using timer A are described below. (1) Common to all modes ➀ When reading timer A (high-order) (TAH) and timer A (low-order) (TAL), the contents of timer A is read out. Read both registers in order of TAH and TAL following, certainly. TAH and TAL keep the values until they are read out. Also, do not write to them during read. In this case, unexpected operation may occur. ➁ When writing data to TAL and TAH when timer A is operating or stopped, the data are set to timer A and timer A latch simultaneously. Write both registers in order of TAL and TAH following, certainly. Also, do not read them during write. In this case, unexpected operation may occur. (2) Period measurement mode, event counter mode, and pulse width HL continuously measurement mode ➀ In order to use CNTR 1 pin, set “0” to bit 0 of the port P0 direction register (input mode). ➁ In order to use CNTR1 pin, set “1” to bit 7 of the interrupt edge selection register to disable the P0 0 key-on wakeup function. ➂ CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. When this bit is “0”, the CNTR 1 interrupt request bit is set to “1” at the falling edge of the CNTR1 pin input signal. When this bit is “1”, the CNTR1 interrupt request bit is set to “1” at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR 1 active edge switch bit.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.3 Timer 1 This paragraph explains the registers setting method and the notes relevant to the timer 1.

2.3.1 Memory map

Fig. 2.3.1 Memory map of registers relevant to timer 1 002816 002916 Prescaler 1 (PRE1) Timer 1 (T1) 003D 16 003F16 Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2)

003816 MISRG

2.3.2 Relevant registers

Fig. 2.3.2 Structure of Prescaler 1 P r e s c a l e r 1 b7 b6 b5 b4 b3 b2 b1 b0 B F u n c t i o n At resetRW Prescaler 1 (PRE1) [Address : 2816]

• S e t a c o u n t v a l u e o f p r e s c a l e r 1 . T h e v a l u e s e t i n t h i s r e g i s t e r i s w r i t t e n t o b o t h p r e s c a l e r a n d t h e p r e s c a l e r l a t c h a t t h e s a m e t i m e W h e n t h i s r e g i s t e r i s r e a d o u t t h e c o u n t v a l u e o f t h e p r e s c a l e r i s r e a d o u t

Rev.2.00 Jun 21, 2004 Fig. 2.3.3 Structure of Timer 1 Timer 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer 1 (T1) [Address : 2916]

• Set a count value of timer 1.
• The value set in this register is written to both timer 1 and timer 1 latch at the same time.
• When this register is read out, the timer 1’s count value is read out. Fig. 2.3.4 Structure of MISRG b7 b6 b5 b4 b3 b2 b1 b0 B F u n c t i o n A t r e s e t RW Name MISRG [Address : 3816] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. M I S R G O s c i l l a t i o n s t a b i l i z a t i o n t i m e s e t b i t a f t e r r e l e a s e o f t h e S T P i n s t r u c t i o n 00 : Set “0116” in timer 1, and “FF16” in prescaler 1 automatically 1 : Not set automatically These are reserved bits. Do not write “1” to these bits. (N o t e) ✕0 : Oscillation stop not detected 1 : Oscillation stop detected Ceramic or RC oscillation stop detection function active bit 0 : Detection function inactive 1 : Detection function active O s c i l l a t i o n s t o p d e t e c t i o n s t a t u s b i t Note: “0” at normal reset “1” at reset by detecting the oscillation stop

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.3 Timer 1 Fig. 2.3.5 Structure of Interrupt request register 2 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 2 (IREQ2) [Address : 3D16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer Y interrupt request bit Timer Z interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Timer 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued Timer A interrupt request bit Serial I/O2 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued AD converter interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Fig. 2.3.6 Structure of Interrupt control register 2 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 2 (ICON2) [Address : 3F16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer Y interrupt enable bit Timer Z interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Timer 1 interrupt enable bit Timer A interrupt enable bit Serial I/O2 interrupt enable bit AD conversion interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled

Rev.2.00 Jun 21, 2004

2.3.3 Timer 1 operation description

Timer 1 always operates in the timer mode. Prescaler 1 counts the selected count source. Each time the count clock is input, the contents of Prescaler 1 is decremented by 1. When the contents of Prescaler 1 reach “00 16”, an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/ (n+1) provided that the value of Prescaler 1 is n. The contents of Timer 1 is decremented by 1 each time the underflow signal of Prescaler 1 is input. When the contents of Timer 1 reach “00 16”, an underflow occurs at the next count clock, and the timer 1 latch is reloaded into Timer 1 and count continues. The division ratio of Timer 1 is 1/(m+1) provided that the value of Timer 1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is provided as follows that the value of Prescaler 1 is n and the value of Timer 1 is m. Timer 1 cannot stop counting by software. Also, when timer 1 underflows, the timer 1 interrupt request bit is set to “1”.

2.3.4 Notes on timer 1

Note on using timer 1 is described below. (1) Notes on set of the oscillation stabilizing time Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/ “not set automatically” by the oscillation stabilizing time set bit after release of the STP instruction of MISRG. When “0” is set to this bit, “0116” is set to timer 1 and “FF16” is set to prescaler 1 automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. Division ratio = 1 (n+1) ✕ (m+1)

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X This paragraph explains the registers setting method and the notes relevant to the timer X.

2.4.1 Memory map

Fig. 2.4.1 Memory map of registers relevant to timer X 000116 000316 002B16 002C 16 002D 16 002E16 Port P0 direction register (P0D) Port P1 direction register (P1D) Timer X mode register (TXM) Prescaler X (PREX) Timer X (TX) Timer count source set register (TCSS) 003C 16 003E16 Interrupt request register 1 (IREQ1) Interrupt control register 1 (ICON1)

Rev.2.00 Jun 21, 2004

2.4.2 Relevant registers

Fig. 2.4.2 Structure of Port P0 direction register Fig. 2.4.3 Structure of Port P1 direction register Port P0 direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port P0 direction register 0 Port P0 direction register (P0D) [Address : 0116] 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode Port P1 direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port P1 direction register 0 Port P1 direction register (P1D) [Address : 0316] 0 : Port P10 input mode 1 : Port P10 output mode 0 : Port P11 input mode 1 : Port P11 output mode 0 : Port P12 input mode 1 : Port P12 output mode 0 : Port P13 input mode 1 : Port P13 output mode 0 : Port P14 input mode 1 : Port P14 output mode Nothing is allocated for these bits. When these bits are read out, the values are undefined.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X Fig. 2.4.4 Structure of Timer X mode register Timer X operating modes Timer mode Pulse output mode Event counter mode Pulse width measurement mode CNTR 0 active edge switch bit (bit 2 of address 2B16) contents “0” CNTR 0 interrupt request occurrence: Falling edge ; No influence to timer count “1” CNTR 0 interrupt request occurrence: Rising edge ; No influence to timer count “0” Pulse output start: Beginning at “H” level CNTR 0 interrupt request occurrence: Falling edge “1” Pulse output start: Beginning at “L” level CNTR 0 interrupt request occurrence: Rising edge “0” Timer X: Rising edge count CNTR 0 interrupt request occurrence: Falling edge “1” Timer X: Falling edge count CNTR 0 interrupt request occurrence: Rising edge “0” Timer X: “H” level width measurement CNTR 0 interrupt request occurrence: Falling edge “1” Timer X: “L” level width measurement CNTR 0 interrupt request occurrence: Rising edge Table 2.4.1 CNTR0 active edge switch bit function b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Timer X mode register (TXM) [Address : 2B16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer X mode register 00 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode b1 b0 1 0 Timer X operating mode bits CNTR 0 active edge switch bitThe function depends on the operating mode. (Refer to Table 2.4.1) Timer X count stop bit 0 : Count start 1 : Count stop 0 : Output invalid (I/O port) 1 : Output valid (Inverted CNTR0 output) P03/TXOUT output valid bit

Rev.2.00 Jun 21, 2004 Fig. 2.4.5 Structure of Prescaler X Fig. 2.4.6 Structure of Timer X Prescaler X b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Prescaler X (PREX) [Address : 2C16]

• Set a count value of prescaler X.
• The value set in this register is written to both prescaler X and the prescaler X latch at the same time.
• When this register is read out, the count value of the prescaler X is read out. Timer X b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer X (TX) [Address : 2D16]
• Set a count value of timer X.
• The value set in this register is written to both timer X and timer X latch at the same time.
• When this register is read out, the timer X’s count value is read out.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X Fig. 2.4.7 Structure of Timer count source set register b 7b 6b 5b 4b 3b 2b 1b 0 B Function A t r e s e t RW N a m e T i m e r c o u n t s o u r c e s e t r e g i s t e r ( T C S S ) [ A d d r e s s : 2 E1 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. T i m e r c o u n t s o u r c e s e t r e g i s t e r Timer X count source selection bits 0b1 b0 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available Timer Y count source selection bits Timer Z count source selection bits Notes 1: f(XIN) can be used as timer X count source only when using a ceramic oscillator or on-chip oscillator. Do not use it at RC oscillation. 2: System operates using an on-chip oscillator as a count source by setting the on-chip oscillator to oscillation enabled by bit 3 of CPUM. F i x t h i s b i t t o “ 0 ” . b5 b4 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : Timer Y underflow 1 1 : Not available b 3 b 2 f XI N ) f XI N ) O n c h i p o s c i l l a t o r o u t p u t o t e N o t a v a i l a b l e

Rev.2.00 Jun 21, 2004 Fig. 2.4.8 Structure of Interrupt request register 1 Fig. 2.4.9 Structure of Interrupt control register 1 Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 1 (IREQ1) [Address : 3C16] Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued CNTR 0 interrupt request bit CNTR 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued INT0 interrupt request bit INT1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Key-on wake up interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Timer X interrupt request bit0 : No interrupt request issued 1 : Interrupt request issued Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 1 (ICON1) [Address : 3E16] Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Timer X interrupt enable bit0 : Interrupt disabled 1 : Interrupt enabled

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X

2.4.3 Timer mode

(1) Operation description Prescaler X counts the selected count source by the timer X count source selection bits. Each time the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of Prescaler X reach “00 16”, an underflow occurs at the next count clock, and the prescaler X latch is reloaded into Prescaler X and count continues. The division ratio of Prescaler X is 1/(n+1) provided that the value of Prescaler X is n. The contents of Timer X is decremented by 1 each time the underflow signal of Prescaler X is input. When the contents of Timer X reach “00 16”, an underflow occurs at the next count clock, and the timer X latch is reloaded into Timer X and count continues. The division ratio of Timer X is 1/(m+1) provided that the value of Timer X is m. Accordingly, the division ratio of Prescaler X and Timer X is provided as follows that the value of Prescaler X is n and the value of Timer X is m. Timer X can stop counting by setting “1” to the timer X count stop bit. Also, when Timer X underflows, the timer X interrupt request bit is set to “1”. (2) Timer mode setting method Figure 2.4.10 shows the setting method for timer mode of timer X. Division ratio = 1 (n+1) ✕ (m+1)

Rev.2.00 Jun 21, 2004 Fig. 2.4.10 Setting method for timer mode b 7b 0 01 0 b 7b 0 b 7b 0 b 7b 0 b 7b 0 b 7b 0 P r o c e s s 1 : D i s a b l e t i m e r X i n t e r r u p t . P r o c e s s 2 : S e t t i m e r X m o d e r e g i s t e r . T i m e r X m o d e r e g i s t e r ( T X M ) [ A d d r e s s 2 B1 P r o c e s s 4 : S e t t h e c o u n t v a l u e t o t i m e r X .

• S e t t h e c o u n t v a l u e t o p r e s c a l e r X a n d t i m e r X Prescaler X (PREX) (Address 2C16) C ount value Timer X (TX) (Address 2D16) Note: f(XIN) can be used only when a ceramic resonator or an on-chip oscillator is used. Do not use f(XIN) at RC oscillation. P r o c e s s 5 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t n o r e q u e s t e d t o t h e t i m e r X i n t e r r u p t r e q u e s t b i t T i m e r m o d e T i m e r X c o u n t s t o p C ount value I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E1 Timer X interrupt disabled I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 3 C 1 P r o c e s s 6 : W h e n t i m e r X i n t e r r u p t i s u s e d , s e t “ 1 ” ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r X i n t e r r u p t e n a b l e b i t N o timer X interrupt request issued Interrupt control register 1 (ICON1) [Address 3E16] Timer X interrupt enabled T i m e r X m o d e r e g i s t e r ( T X M ) [ A d d r e s s 2 B1 T i m e r X c o u n t s t a r t P r o c e s s 7 : S t a r t c o u n t i n g o f t i m e r X . P r o c e s s 3 : S e t t i m e r c o u n t s o u r c e s e t r e g i s t e r . T i m e r c o u n t s o u r c e s e t r e g i s t e r ( T C S S ) [ A d d r e s s 2 E1 T i m e r X c o u n t s o u r c e s e l e c t i o n b i t s b b f XI N ) f XI N ) f XI N ) o t N o t a v a i l a b l e

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X (3) Application example of timer mode Outline: The input clock is divided by the timer so that the clock is counted up every 250 ms intervals. Specifications: •The f(XIN) = 4.19 MHz (222 Hz) is divided by timer X.

• The clock is counted up in the timer X interrupt processing routine (timer X interrupt occurs every 250 ms).
• Operation clock: f(XIN) = 4.19 MHz, high-speed mode Figure 2.4.11 shows the connection of timer and setting of division ratio and Figure 2.4.12 shows an example of control procedure. Fig. 2.4.11 Connection of timer and setting of division ratio f(XIN) = 4.19 MHz P r e s c a l e r XT i m e r X Timer X interrupt request bit 250 ms 1/16 1/256 1/256 0 or 1 1/4 D i v i d e d b y 4 b y s o f t w a r e 0: No interrupt request 1: Interrupt request T i m e r X c o u n t s o u r c e s e l e c t i o n b i t s

Rev.2.00 Jun 21, 2004 Fig. 2.4.12 Example of control procedure “FF16” CLI 0 11 RESET Timer X interrupt processing routine RTI

0 TCSS(Address 2E16)

Timer X count source: f(XIN)/16 selected Set timer count source set register 1 00

0 TXM(Address 2B16)01 00

Setting clock is required? Processing Processing of setting clock Y N Clock is stopped? Y N Processing of clock setting Clock setting RTS 0 1 00 0 01 00 Set “0” to the timer X interrupt enable bit. (Timer X interrupt disabled) Prescaler X (Address 2C16) Set value to timer X (Note 2) Set “0” to the timer X interrupt request bit. TXM(Address 2B16) Timer mode Timer X count stop Set timer X mode register Initialization SEI CLD CLT CPUM(Address 3B 16) ← 10000X002 Wait until f(XIN) oscillation is stabilized (Note 1) CPUM(Address 3B16) ← 00000X002 Timer X (Address 2D16) Set “1” to the timer X interrupt enable bit. (Timer X interrupt enabled) Timer X count start Set timer X mode register X: This bit is not used here. Set it to “0” or “1” arbitrary. Notes 1: For the concrete time, ask the oscillator manufacture. 2: About 250 ms = 1/4.19 MHz ✕ 16 ✕ (FF16 + 1) ✕ (FF16 + 1) Timer X setting value “FF16” Clock count up (1/4 s to year) Set “0” to the timer X interrupt enable bit. (Timer X interrupt disabled) TXM(Address 2B16) Timer X count start Set timer X mode register TXM(Address 2B16) Timer X count stop Set timer X mode register “FF16” Prescaler X (Address 2C16) Set value to timer X (Note 2) Set “0” to the timer X interrupt request bit. Timer X (Address 2D16) Set “1” to the timer X interrupt enable bit. (Timer X interrupt enabled) “FF16” Timer X division ratio Prescaler X setting value

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X Fig. 2.4.13 Setting method for pulse output mode (1)

2.4.4 Pulse output mode

(1) Operation description In the pulse output mode, the waveform whose polarity is inverted each time timer X underflows is output from the P1 4/CNTR 0 pin. The output level of CNTR0 pin can be selected by the CNTR0 active edge switch bit. When the CNTR0 active edge switch bit is “0”, the output of CNTR0 pin is started at “H” level. When this bit is “1”, the output is started at “L” level. Also, the inverted waveform of pulse output from CNTR 0 pin can be output from TXOUT pin by setting “1” to the P03/TXOUT output valid bit. When using a timer in this mode, set the port P14 and P03 direction registers to output mode. Timer X can stop counting by setting “1” to the timer X count stop bit. Also, when Timer X underflows, the timer X interrupt request bit is set to “1”. (2) Pulse output mode setting method b 7b 0 01 1 b 7b 0 b b 7b 0 P r o c e s s 1 : D i s a b l e t i m e r X i n t e r r u p t . Interrupt control register 1 (ICON1) [Address 3E16] T i m e r X i n t e r r u p t d i s a b l e d P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D ) [ A d d r e s s 0 31 S e t t h e P 14/ C N T R 0 p i n t o t h e o u t p u t m o d e P r o c e s s 3 : S e t t h e C N T R 0 p i n t o t h e o u t p u t m o d e . P r o c e s s 2 : S e t t i m e r X m o d e r e g i s t e r . Timer X mode register (TXM) [Address 2B16] P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D ) [ A d d r e s s 0 11 S e t t h e P 03/ T XO U T p i n t o t h e o u t p u t m o d e P r o c e s s 4 : S e t t h e T XO U T p i n a s t h e o u t p u t m o d e w h e n T XO U T o u t p u t i s v a l i d . Pulse output mode CNTR 0 active edge switch 0: Output is started at “H” level 1: Output is started at “L” level Timer X count stop 3/TXOUT output 0: Output invalid (I/O port) 1: Output valid (inverted CNTR 0 output)

Rev.2.00 Jun 21, 2004 Fig. 2.4.14 Setting method for pulse output mode (2) b b 7b 0 00 1 b b7 b0 P r o c e s s 6 : S e t t h e c o u n t v a l u e t o t i m e r X .

• Set the count value to prescaler X and timer X P r e s c a l e r X ( P R E X ) ( A d d r e s s 2 C 1 C o u n t v a l u e Timer X (TX) (Address 2D16) P r o c e s s 7 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t “ 0 ” ( n o r e q u e s t e d ) t o t h e t i m e r X i n t e r r u p t r e q u e s t b i t I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 3 C 1 P r o c e s s 8 : W h e n t h e i n t e r r u p t i s u s e d , s e t “ 1 ” ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r X i n t e r r u p t e n a b l e b i t N o timer X interrupt request issued Timer X mode register (TXM) [Address 2B16] Timer X count start Process 9: Start counting of timer X. C o u n t v a l u e Interrupt control register 1 (ICON1) [Address 3E16] Timer X interrupt enabled N o t e : f ( XI N ) c a n b e u s e d o n l y w h e n a c e r a m i c r e s o n a t o r o r a n o n - c h i p o s c i l l a t o r i s u s e d . D o n o t u s e f XI N ) a t R C o s c i l l a t i o n P r o c e s s 5 : S e t t i m e r c o u n t s o u r c e s e t r e g i s t e r . T i m e r c o u n t s o u r c e s e t r e g i s t e r ( T C S S ) [ A d d r e s s 2 E1 T i m e r X c o u n t s o u r c e s e l e c t i o n b i t s b b f XI N ) f XI N ) f XI N ) o t e N o t a v a i l a b l e

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X (3) Application example of pulse output mode Outline: The pulse output mode of timer X is used for a piezoelectric buzzer output. Specifications: The rectangular waveform which is clock f(XIN) = 4 MHz divided up to 4 kHZ is output from the P14/CNTR 0 pin. The level of the P14/CNTR 0 pin is fixed to “H” while a piezoelectric buzzer output is stopped. Operation clock: f(X IN) = 4 MHz, double-speed mode Figure 2.4.15 shows an example of a peripheral circuit, Figure 2.4.16 shows the connection of timer and setting of the division ratio, and Figure 2.4.17 shows an example of control procedure. Fig. 2.4.15 Example of peripheral circuit 7 5 4 0 G r o u p 125 µs 125 µs S e t d i v i s i o n r a t i o s o t h a t t h e u n d e r f l o w o u t p u t p e r i o d o f t i m e r X w i l l b e c o m e µs T h e “ H ” l e v e l i s o u t p u t w h i l e a p i e z o e l e c t r i c b u z z e r o u t p u t i s s t o p p e d . C N T R 0 o u t p u t f(XIN) = 4MHz Prescaler X Timer X Timer X count source selection bit 1/2 1/125 1/2 Fixed CNTR 0 pin output 4 kHz Fig. 2.4.16 Connection of timer and setting of division ratio

Rev.2.00 Jun 21, 2004 Fig. 2.4.17 Example of control procedure “0116” “7C16”

0 TXM(Address 2B16)11

Timer X count source: f(XIN)/2 selected 1 01 0 01 00 Buzzer output is requested? Processing Y N “7C16” Timer X (Address 2D16) CLI Timer X count is stopped? Y Processing Timer X count is operating? 0 11 001 N Y N Buzzer output processing Timer X division ratio Timer X setting value SEI CLD CLT CPUM(Address 3B 16) ← 10000X002 Wait until f(XIN) oscillation is stabilized (Note 1) CPUM(Address 3B16) ← 11000X002 Set timer X mode register TXM(Address 2B16) Timer X count start Pulse output mode Output is started at “H” level Timer X count stop Set timer X mode register Set port P1 4 to the output mode. Set “0” to the CNTR0 interrupt enable bit. (CNTR 0 interrupt disabled) Set “0” to the timer X interrupt enable bit. (Timer X interrupt disabled) Initialization X: This bit is not used here. Set it to “0” or “1” arbitrary. Notes 1: For the concrete time, ask the oscillator manufacture. 2: 125 µs = 1/4 MHz ✕ 2 ✕ (0116 + 1) ✕ (7C16 + 1) Prescaler X (Address 2C16) Set value to timer X (Notes 2, 3) Timer X (Address 2D16) Set “1” to port P14. (“H” output) Set timer count source set register Set timer X mode register TXM(Address 2B16) Timer X count stop Set value to timer X (Note 3) 3: The output level of P14/CNTR 0 pin is initialized by writing to timer X. Prescaler X setting value

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X Fig. 2.4.18 Setting method for event counter mode (1)

2.4.5 Event counter mode

(1) Operation description The timer X counts signals input from the P14/CNTR 0 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR0 pin input signal can be selected from rising or falling by the CNTR0 active edge switch bit. Timer X can stop counting by setting “1” to the timer X count stop bit. Also, when Timer X underflows, the timer X interrupt request bit is set to “1”. (2) Event counter mode setting method b 7b 0 11 0 b7 b0 b 7b 0 b 7b 0 P r o c e s s 1 : D i s a b l e t i m e r X i n t e r r u p t a n d C N T R 0 i n t e r r u p t . I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E1 C N T R 0 i n t e r r u p t d i s a b l e d T i m e r X i n t e r r u p t d i s a b l e d P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D ) [ A d d r e s s 0 31 Set the P14/CNTR 0 pin to the input mode Process 2: Set the CNTR0 pin to the input mode. Process 3: Set timer X mode register. T i m e r X m o d e r e g i s t e r ( T X M ) [ A d d r e s s 2 B1 Event counter mode CNTR 0 active edge switch 0: Count at rising edge CNTR 0 interrupt request occurs at falling edge 1: Count at falling edge CNTR 0 interrupt request occurs at rising edge Timer X count stop N o t e : f ( XI N ) c a n b e u s e d o n l y w h e n a c e r a m i c o s c i l l a t o r o r a n o n - c h i p o s c i l l a t o r i s u s e d . D o n o t u s e f XI N ) a t R C o s c i l l a t i o n P r o c e s s 4 : S e t t i m e r c o u n t s o u r c e s e t r e g i s t e r . Timer count source set register (TCSS) [Address 2E16] Timer X count source selection bits b1 b0 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note) 1 1 : Not available

Rev.2.00 Jun 21, 2004 Fig. 2.4.19 Setting method for event counter mode (2) b7 b0 b 7b 0 b P r o c e s s 5 : S e t t h e c o u n t v a l u e t o t i m e r X .

• S e t t h e c o u n t v a l u e t o p r e s c a l e r X a n d t i m e r X Prescaler X (PREX) (Address 2C16) C o u n t v a l u e Timer X (TX) (Address 2D16) C o u n t v a l u e Process 6: In order not to execute the no requested interrupt processing, set “0” (no requested) to the timer X interrupt request bit and CNTR1 interrupt request bit. Interrupt request register 1 (IREQ1) [Address 3C16] P r o c e s s 7 : W h e n t h e i n t e r r u p t i s u s e d , s e t “ 1 ” ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r X i n t e r r u p t e n a b l e b i t N o C N T R 0 i n t e r r u p t r e q u e s t i s i s s u e d N o t i m e r X i n t e r r u p t r e q u e s t i s s u e d Timer X mode register (TXM) [Address 2B16] Timer X count start Process 8: Start counting of timer X. Interrupt control register 1 (ICON1) [Address 3E16] C N T R 0 i n t e r r u p t e n a b l e d T i m e r X i n t e r r u p t e n a b l e d

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X (3) Application example of event counter mode Outline: Pulses generated corresponding to the water flow rate are counted for a fixed period (100 ms), and the water flow rate during this period is calculated. Specifications: Pulses generated corresponding to the water flow rate are input to the P14/CNTR 0 pin and counted using timer X. The contents of timer X are read in the timer Y interrupt processing routine generated after 100 ms from the start of counting pulses, and the water flow rate during 100 ms is calculated. Operation clock: f(X IN) = 8 MHz, high-speed mode Figure 2.4.20 shows an example of peripheral circuit, Figure 2.4.21 shows the method of measuring water flow rate, and Figure 2.4.21 shows an example of control procedure. Fig. 2.4.20 Example of peripheral circuit G r o u p P14/CNTR 0 W a t e r f l o w r a t e s e n s o r Water flow B l a d e s r o t a t e i n p r o p o r t i o n t o w a t e r f l o w a n d g e n e r a t e p u l s e s T h e f a s t e r t h e w a t e r f l o w t h e s h o r t e r t h e p u l s e p e r i o d Fig. 2.4.21 Method of measuring water flow rate C N T R 0 p i n i n p u t T i m e r Y i n t e r r u p t r e q u e s t b i t m s Timer X counting (Note) Note: Counting rising edges.

• Flow rate during 100 ms = (FF16–read value of timer X) ✕ flow rate per pulse T i m e r Y i n t e r r u p t p r o c e s s i n g r o u t i n e T i m e r X t i m e r Y s t o p c o u n t i n g T i m e r X i s r e a d o u t Timer X, timer Y start counting.

Rev.2.00 Jun 21, 2004 Fig. 2.4.22 Example of control procedure “ F F1 “FF16” 0 11 10 01 00 0 01 10 F l o w r a t e m e a s u r i n g r o u t i n e 1 00 “ C 71 “F916” 0 00 E N D Timer Y interrupt processing routine 0 11 10 1 00 (Prescaler X setting value “FF16” Timer X setting value “FF16”) – (Prescaler X count value, Timer X count value) ← The numbeer of event within 100 ms RTI T X M ( A d d r e s s 2 B1 TCSS(Address 2E16) Timer Y count source: f(XIN)/16 selected T i m e r Y d i v i s i o n r a t i o Timer Y primary setting value E v e n t c o u n t e r m o d e C o u n t a t f a l l i n g e d g e T i m e r X c o u n t s t o p S e t t i m e r X m o d e r e g i s t e r Set port P14 to the input mode. S e t “ 0 ” t o t h e C N T R 0 i n t e r r u p t e n a b l e b i t . C N T R 0 i n t e r r u p t d i s a b l e d S e t t o t h e t i m e r X i n t e r r u p t e n a b l e b i t T i m e r X i n t e r r u p t d i s a b l e d S e t t o t h e t i m e r Y i n t e r r u p t e n a b l e b i t T i m e r Y i n t e r r u p t d i s a b l e d Note : 100 ms = 1/8 MHz ✕ 16 ✕ (C716 + 1) ✕ (F916 + 1) Prescaler X (Address 2C 16) S e t v a l u e t o t i m e r X T i m e r X ( A d d r e s s 2 D 1 Set timer count source set register Prescaler Y setting value T Y Z M ( A d d r e s s 2 01 S e t t i m e r Y , Z m o d e r e g i s t e r T i m e r m o d e W r i t i n g t o l a t c h a n d t i m e r s i m u l t a n e o u s l y T i m e r Y c o u n t s t o p S e t v a l u e t o t i m e r Y (N o t e) P r e s c a l e r Y ( A d d r e s s 2 11 T i m e r Y p r i m a r y ( A d d r e s s 2 31 Set “1” to the timer Y interrupt enable bit. (Timer Y interrupt enabled) S e t “ 0 ” t o t h e t i m e r Y i n t e r r u p t r e q u e s t b i t . T X M ( A d d r e s s 2 B1 Timer X count start S e t t i m e r X m o d e r e g i s t e r T Y Z M ( A d d r e s s 2 01 S e t t i m e r Y , Z m o d e r e g i s t e r T i m e r Y c o u n t s t a r t TXM(Address 2B16) T i m e r X c o u n t s t o p Set timer X mode register TYZM(Address 2016) Set timer Y, Z mode register T i m e r Y c o u n t s t o p

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X

2.4.6 Pulse width measurement mode

(1) Operation description In the pulse width measurement mode, the pulse width of the signal input to P14/CNTR 0 p i n i s measured. The operation of Timer X can be controlled by the level of the signal input from the CNTR 0 pin. When the CNTR 0 active edge switch bit is “0”, the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is “H”. The count is stopped while the pin is “L”. Also, when the CNTR 0 active edge switch bit is “1”, the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is “L”. The count is stopped while the pin is “H”. Timer X can stop counting by setting “1” to the timer X count stop bit. Also, when Timer X underflows, the timer X interrupt request bit is set to “1”. (2) Pulse width HL continuously measurement mode setting method Fig. 2.4.23 Setting method for pulse width measurement mode (1) b b 7b 0 11 1 b 7b 0 b 7b 0 P r o c e s s 1 : D i s a b l e t i m e r X i n t e r r u p t a n d C N T R 0 i n t e r r u p t . Interrupt control register 1 (ICON1) [Address 3E16] CNTR 0 interrupt disabled Timer X interrupt disabled P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D ) [ A d d r e s s 0 31 Set the P14/CNTR 0 pin to the input mode Process 2: Set the CNTR0 pin to the input mode. P r o c e s s 3 : S e t t i m e r X m o d e r e g i s t e r . Timer X mode register (TXM) [Address 2B16] P u l s e w i d t h m e a s u r e m e n t m o d e C N T R 0 a c t i v e e d g e s w i t c h H l e v e l w i d t h m e a s u r e m e n t L l e v e l w i d t h m e a s u r e m e n t T i m e r X c o u n t s t o p N o t e : f ( XI N ) c a n b e u s e d o n l y w h e n a c e r a m i c r e s o n a t o r o r a n o n - c h i p o s c i l l a t o r i s u s e d . D o n o t u s e f XI N ) a t R C o s c i l l a t i o n Process 4: Set timer X count source. T i m e r c o u n t s o u r c e s e t r e g i s t e r ( T C S S ) [ A d d r e s s 2 E1 T i m e r X c o u n t s o u r c e s e l e c t i o n b i t s b b f XI N ) f XI N ) f XI N ) o t N o t a v a i l a b l e

Rev.2.00 Jun 21, 2004 Fig. 2.4.24 Setting method for pulse width measurement mode (2) b7 b0 b7 b0 b7 b0 P r o c e s s 5 : S e t t h e c o u n t v a l u e t o t i m e r X .

• S e t t h e i n i t i a l v a l u e t o p r e s c a l e r X a n d t i m e r X Prescaler X (PREX) (Address 2C16) I n i t i a l v a l u e Timer X (TX) (Address 2D16) I n i t i a l v a l u e P r o c e s s 6 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t “ 0 ” ( n o r e q u e s t e d ) t o t h e t i m e r X i n t e r r u p t r e q u e s t b i t a n d C N T R 0 i n t e r r u p t r e q u e s t b i t Interrupt request register 1 (IREQ1) [Address 3C16] Process 7: When the interrupt is used, set “1” (interrupt enabled) to the timer X interrupt enable bit. N o C N T R 0 i n t e r r u p t r e q u e s t i s i s s u e d N o t i m e r X i n t e r r u p t r e q u e s t i s s u e d T i m e r X m o d e r e g i s t e r ( T X M ) [ A d d r e s s 2 B1 T i m e r X c o u n t s t a r t Process 8: Start counting of timer X. Interrupt control register 1 (ICON1) [Address 3E16] CNTR 0 interrupt enabled Timer X interrupt enabled

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X (3) Application example of pulse width measurement mode Outline: “H” level width of pulse input to P14/CNTR 0 pin is counted. Specifications: The “H” level width of a FG pulse input to the P14/CNTR 0 pin is counted. An underflow is detected by the timer X interrupt. The completion of “H” level of input pulse is detected by the CNTR0 interrupt. Operation clock: f(XIN) = 4.19 MHz, high-speed mode Example: When f(XIN) = 4.19 MHz, the count source becomes 3.8 µs divided by 16. Measurement can be made up to 250 ms in the range of “FFFF16” to “000016”. an example of control procedure. Fig. 2.4.25 Connection of timer and setting of division ratio f(XIN) = 4.19MHz Prescaler X Timer X Timer X interrupt request bit 2 5 0 m s 1 / 1 61 / 2 5 6 1/256 0 or 1 0: No interrupt request 1: Interrupt request T i m e r X c o u n t s o u r c e s e l e c t i o n b i t

Rev.2.00 Jun 21, 2004 Fig. 2.4.26 Example of control procedure “FF16” “FF16” 0 11 11 01 00 0 01 11 END RESET CLI Processing Timer X interrupt processing CNTR 0 interrupt processing Timer X interrupt processing routine Error processing RTI CNTR 0 interrupt processing routine Timer X is read out. RTI TXM(Address 2B16) TCSS(Address 2E16) Timer Y count source: f(XIN)/16 selected Timer X division ratio Timer X setting value SEI CLD CLT CPUM(Address 3B 16) ← 10000X002 Wait until f(XIN) oscillation is stabilized (Note 1) CPUM(Address 3B16) ← 00000X002 Pulse width measurement mode Falling edge Timer X count stop Set timer X mode register Set port P1 4 to the input mode. Set “0” to the CNTR0 interrupt enable bit. (CNTR 0 interrupt disabled) Set “0” to the timer X interrupt enable bit. (Timer X interrupt disabled) Initialization X: This bit is not used here. Set it to “0” or “1” arbitrary. Notes 1: For the concrete time, ask the oscillator manufacture. 2: About 250 ms = 1/4.19 MHz ✕ 16 ✕ (FF16+ 1) ✕ (FF16 + 1) Prescaler X (Address 2C16) Set value to timer X (Note 2) Timer X (Address 2D16) Set timer count source set register Prescaler X setting value Set “1” to the CNTR0 interrupt enable bit. (CNTR 0 interrupt enabled) Set “1” to the timer X interrupt enable bit. (Timer X interrupt enabled) Set “0” to the CNTR0 interrupt request bit. Set “0” to the timer X interrupt request bit. TXM(Address 2B16) Timer X count start Set timer X mode register Error processing at incorrect period input

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.4 Timer X

2.4.7 Notes on timer X

Notes on using each mode of timer X are described below. (1) Count source ➀ f(XIN) can be used only when a ceramic oscillator or an on-chip oscillator is used. Do not use f(XIN) at RC oscillation. (2) Pulse output mode ➀ In order to use CNTR0 pin, set “1” to bit 4 of the port P1 direction register (output mode). ➁ In order to use TXOUT pin, set “1” to bit 3 of the port P0 direction register (output mode). ➂ CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is “0”, the CNTR 0 interrupt request bit is set to “1” at the falling edge of CNTR0 pin input signal. When this bit is “1”, the CNTR0 interrupt request bit is set to “1” at the rising edge of CNTR0 pin input signal. (3) Pulse width measurement mode ➀ In order to use CNTR0 pin, set “1” to bit 4 of the port P1 direction register (output mode). ➁ CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is “0”, the CNTR 0 interrupt request bit is set to “1” at the falling edge of CNTR0 pin input signal. When this bit is “1”, the CNTR0 interrupt request bit is set to “1” at the rising edge of CNTR0 pin input signal.

Rev.2.00 Jun 21, 2004 This paragraph explains the registers setting method and the notes relevant to the timer Y and timer Z.

2.5.1 Memory map

Fig. 2.5.1 Memory map of registers relevant to timer Y and timer Z 002516 002616 002716 002A16 002E16 Prescaler Z (PREZ) Timer Z secondary (TZS) Timer Z primary (TZP) One-shot start register (ONS) Timer count source set register (TCSS) 003C 16 003E16 Interrupt request register 1 (IREQ1) Interrupt control register 1 (ICON1) 003A16 Interrupt edge selection register (INTEDGE) 003D 16 003F16 Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2) 003B16 CPU mode register (CPUM) 002216 002316 002416 Timer Y secondary (TYS) Timer Y primary (TYP) Timer Y, Z waveform output control register (PUM) 002016 002116 Timer Y, Z mode register (TYZM) Prescaler Y (PREY) 001616 001716 Pull-up control register (PULL) Port P1P3 control register (P1P3C)

000716 Port P3 direction register (P3D)

000116 Port P0 direction register (P0D)

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z

2.5.2 Relevant registers

Fig. 2.5.2 Structure of Port P0 direction register Fig. 2.5.3 Structure of Port P3 direction register Port P0 direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port P0 direction register 0 Port P0 direction register (P0D) [Address : 0116] 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode Port P3 direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port P3 direction register 0 Port P3 direction register (P3D) [Address : 0716] 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode Note: The 32-pin package versions have nothing to be allocated for the following:

• Bits 5 and 6 of P3D.

Rev.2.00 Jun 21, 2004 Fig. 2.5.4 Structure of Pull-up control register Pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name P00 pull-up control bit 0 Pull-up control register (PULL) [Address : 1616] 0 : Pull-up Off 1 : Pull-up On Notes 1: Pins set to output are disconnected from the pull-up control. 2: Keep setting the P35, P36 pull-up control bit to “1” (initial value: 0) for the 32-pin package versions. P01 pull-up control bit 0 : Pull-up Off 1 : Pull-up On P02, P03 pull-up control bit0 : Pull-up Off 1 : Pull-up On P04 – P07 pull-up control bit0 : Pull-up Off 1 : Pull-up On P30 – P33 pull-up control bit0 : Pull-up Off 1 : Pull-up On P34 pull-up control bit 0 : Pull-up Off 1 : Pull-up On P35, P36 pull-up control bit0 : Pull-up Off 1 : Pull-up On P37 pull-up control bit 0 : Pull-up Off 1 : Pull-up On Fig. 2.5.5 Structure of Port P1P3 control register Port P1P3 control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name P37/INT0 input level selection bit Port P1P3 control register (P1P3C) [Address : 1716] 0 : CMOS level 1 : TTL level P36/INT1 input level selection bit (Note) 0 : CMOS level 1 : TTL level P10, P12,P13 input level selection bit 0 : CMOS level 1 : TTL level Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Note: Keep setting the P36/INT1 input level selection bit to “0” (initial value) for the 32-pin package version.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.6 Structure of Timer Y, Z mode register Fig. 2.5.7 Structure of Prescaler Y, Prescaler Z P r e s c a l e r Y , P r e s c a l e r Z b 7b 6b 5b 4b 3b 2b 1b 0 B F u n c t i o n A t r e s e t RW Prescaler Y (PREY) [Address : 2116] Prescaler Z (PREZ) [Address : 2516]

• S e t a c o u n t v a l u e o f e a c h p r e s c a l e r . h i l e t h e c o r r e s p o n d i n g t i m e r i s s t o p p e d t h e v a l u e s e t i n t h i s r e g i s t e r i s w r i t t e n t o b o t h p r e s c a l e r a n d t h e c o r r e s p o n d i n g p r e s c a l e r l a t c h a t t h e s a m e t i m e h i l e t h e c o r r e s p o n d i n g t i m e r i s o p e r a t i n g t h e v a l u e s e t i n t h i s r e g i s t e r i s w r i t t e n t o a s f o l l o w s W h e n t h e t i m e r w r i t e c o n t r o l b i t i s t h e v a l u e i s w r i t t e n t o p r e s c a l e r l a t c h a n d p r e s c a l e r a t t h e s a m e t i m e W h e n t h e t i m e r w r i t e c o n t r o l b i t i s t h e v a l u e i s w r i t t e n t o p r e s c a l e r l a t c h o n l y h e n t h i s r e g i s t e r i s r e a d o u t t h e c o u n t v a l u e o f t h e c o r r e s p o n d i n g p r e s c a l e r i s r e a d o u t Timer Y, Z mode register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is “0”. Timer Y, Z mode register (TYZM) [Address : 2016) Timer Y operating mode bit 0 : Timer mode 1 : Programmable waveform generation mode Timer Y write control bit (Note) 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Y count stop bit 0 : Count start 1 : Count stop Timer Z operating mode bitsb5 b4 0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode Timer Z write control bit (Note) 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Z count stop bit 0 : Count start 1 : Count stop Note: When modes other than the timer mode, set these bits to “1”.

Rev.2.00 Jun 21, 2004 Fig. 2.5.8 Structure of Timer Y secondary, Timer Z secondary Timer Y secondary, Timer Z secondary b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer Y secondary, Timer Z secondary (TYS, TZS) [Address : 2216, 2616]

• Set a count value of the corresponding timer.
• The value set in this register is written to the corresponding secondary latch at the same time.
• These are read disabled bits. When these bits are read out, the values are undefined. Fig. 2.5.9 Structure of Timer Y primary, Timer Z primary b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer Y primary, Timer Z primary Timer Y primary, Timer Z primary (TYP, TZP) [Address : 2316, 2716]
• Set a count value of the corresponding timer.
• When the corresponding timer is stopped, the value set in this register is written to both the corresponding primary latch and the corresponding timer at the same time.
• When the corresponding timer is operating, the value set in this register is written as follows; timer write control bit = 0: the value is written to both the corresponding primary latch and the corresponding timer at the same time. timer write control bit = 1: the value is written to the corresponding primary latch.
• When these bits are read out, the count value of the corres- ponding timer is read out (Note). Note: The primary count value is read out at the primary interval, the secondary count value is read out at the secondary interval.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.10 Structure of Timer Y, Z waveform output control register Fig. 2.5.11 Structure of One-shot start register Timer Y, Z waveform output control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Timer Y primary waveform extension control bit Timer Y secondary waveform extension control bit Timer Z output level latch Timer Z primary waveform extension control bit Timer Z secondary waveform extension control bit Timer Y output level latch 0 : Falling edge trigger 1 : Rising edge trigger Timer Y, Z waveform output control register (PUM) [Address : 2416] INT0 pin one-shot trigger control bit (Note) INT0 pin one-shot trigger active edge selection bit (Note) 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : “L” output 1 : “H” output 0 : “L” output 1 : “H” output 0 : INT0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid Note: Stop timer Z to change the values of these bits. One-shot start register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name One-shot start register (ONS) [Address : 2A16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer Z one-shot start bit 0 : One-shot stop 1 : One-shot start

Rev.2.00 Jun 21, 2004 Fig. 2.5.12 Structure of Timer count source set register Fig. 2.5.13 Structure of Interrupt edge selection register b 7b 6b 5b 4b 3b 2b 1b 0 B F u n c t i o n At resetRW N a m e T i m e r c o u n t s o u r c e s e t r e g i s t e r ( T C S S ) [ A d d r e s s : 2 E1 N o t h i n g i s a l l o c a t e d f o r t h i s b i t . T h i s i s a w r i t e d i s a b l e d b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s T i m e r c o u n t s o u r c e s e t r e g i s t e r Timer X count source selection bits 0b 1 b 0 f XI N ) f XI N ) f XI N ) o t e N o t a v a i l a b l e T i m e r Y c o u n t s o u r c e s e l e c t i o n b i t s T i m e r Z c o u n t s o u r c e s e l e c t i o n b i t s N o t e s 1 : f ( XI N ) c a n b e u s e d a s t i m e r X c o u n t s o u r c e o n l y w h e n u s i n g a c e r a m i c o s c i l l a t o r o r o n c h i p o s c i l l a t o r D o n o t u s e i t a t R C o s c i l l a t i o n S y s t e m o p e r a t e s u s i n g a n o n c h i p o s c i l l a t o r a s a c o u n t s o u r c e b y s e t t i n g t h e o n c h i p o s c i l l a t o r t o o s c i l l a t i o n e n a b l e d b y b i t o f C P U M F i x t h i s b i t t o “ 0 ” . b 5 b 4 f XI N ) f XI N ) T i m e r Y u n d e r f l o w N o t a v a i l a b l e b 3 b 2 f XI N ) f XI N ) O n c h i p o s c i l l a t o r o u t p u t o t e N o t a v a i l a b l e Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt edge selection register (INTEDGE) [Address : 3A16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. INT0 interrupt edge selection bit INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.14 Structure of CPU mode register b 7b 6b 5b 4b 3b 2b 1b 0 B F u n c t i o n A t r e s e t RW Name CPU mode register (CPUM) [Address : 3B16] C P U m o d e r e g i s t e r 00 0 : Single-chip mode 0 1 : Not available 1 0 : Not available 1 1 : Not available b1 b0 1 0 Processor mode bits (Note 1) 0 : Ceramic oscillation 1 : RC oscillation 0 : 0 p a g e p a g e S t a c k p a g e s e l e c t i o n b i t Oscillation mode selection bit (Note 1) C l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s 0 0 : φ = f ( XI N ) / 2 h i g h s p e e d m o d e φ f XI N ) m i d d l e s p e e d m o d e A p p l i e d f r o m o n c h i p o s c i l l a t o r φ f XI N ) d o u b l e s p e e d m o d e o t e b7 b6 0 : C e r a m i c o r R C o s c i l l a t i o n e n a b l e d C e r a m i c o r R C o s c i l l a t i o n s t o p Notes 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU “M37540RSS”.) 2: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected. O n - c h i p o s c i l l a t o r o s c i l l a t i o n c o n t r o l b i t 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop XIN oscillation control bit

Rev.2.00 Jun 21, 2004 Fig. 2.5.15 Structure of Interrupt request register 1 Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 1 (IREQ1) [Address : 3C16] Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued CNTR 0 interrupt request bit CNTR 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued INT0 interrupt request bit INT1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Key-on wake up interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Timer X interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Fig. 2.5.16 Structure of Interrupt request register 2 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 2 (IREQ2) [Address : 3D16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer Y interrupt request bit Timer Z interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Timer 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued Timer A interrupt request bit Serial I/O2 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued AD converter interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.17 Structure of Interrupt control register 1 Fig. 2.5.18 Structure of Interrupt control register 2 Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 1 (ICON1) [Address : 3E16] Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Timer X interrupt enable bit0 : Interrupt disabled 1 : Interrupt enabled Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 2 (ICON2) [Address : 3F16] Timer Y interrupt enable bit Timer Z interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Timer 1 interrupt enable bit Timer A interrupt enable bit Serial I/O2 interrupt enable bit AD conversion interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled ✕Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”.

Rev.2.00 Jun 21, 2004

2.5.3 Timer mode (timer Y and timer Z)

The basic operation of Timer Y and Timer Z are the same. In this section, Timer Y is explained. (1) Operation description Prescaler Y counts the count source selected by the timer Y count source selection bits. Each time the count clock is input, the contents of Prescaler Y is decremented by 1. When the contents of Prescaler Y reach “0016”, an underflow occurs at the next count clock, and the prescaler Y latch is reloaded into Prescaler Y and count continues. The division ratio of Prescaler Y is 1/(n+1) provided that the value of Prescaler Y is n. The contents of Timer Y is decremented by 1 each time the underflow signal of Prescaler Y is input. When the contents of Timer Y reach “0016”, an underflow occurs at the next count clock, and the timer Y primary latch is reloaded into Timer Y and count continues. (In the timer mode, the contents of timer Y primary latch is counted. Timer Y secondary latch is not used in this mode.) The division ratio of Timer Y is 1/(m+1) provided that the value of Timer Y is m. Accordingly, the division ratio of Prescaler Y and Timer Y is provided as follows that the value of Prescaler Y is n and the value of Timer Y is m. In the timer mode, writing to “latch only” or “latches and Prescaler Y and timer Y primary” can be selected by the setting value of the timer Y write control bit. Timer Y can stop counting by setting “1” to the timer Y count stop bit. Also, when timer Y underflows, the timer Y interrupt request bit is set to “1”. Timer Y reloads the value of latch when counting is stopped by the timer count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) (2) Timer mode setting method Figure 2.5.19 shows the setting method for timer mode of Timer Y. When Timer Z is used, registers are set by the same method. Division ratio = (n+1) ✕ (m+1)

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.19 Setting method for timer mode b 1 0 b b7 b 0 Notes 1: For timer Z, f(XIN), f(XIN)/2, or timer Y underflow can be selected. 2: Set the on-chip oscillator oscillation to be enabled by bit 3 (on-chip oscillator oscillation control bit) of CPU mode register. b N o t e : I n t h e t i m e r m o d e , t h e t i m e r Y s e c o n d a r y i s n o t u s e d . b7 b0 b 7b 0 P r o c e s s 1 : D i s a b l e t i m e r Y i n t e r r u p t . P r o c e s s 2 : S e t t i m e r Y , Z m o d e r e g i s t e r . T i m e r Y , Z m o d e r e g i s t e r ( T Y Z M ) [ A d d r e s s 2 01 Process 4: Set the count value to timer Y.

• Set the count value to prescaler Y and timer Y primary C ount value Timer Y primary (TYP) (Address 2316) Process 5: In order not to execute the no requested interrupt processing, set “0” (no requested) to the timer Y interrupt request bit. T i m e r m o d e T i m e r Y w r i t e c o n t r o l b i t W r i t e t o l a t c h a n d t i m e r s i m u l t a n e o u s l y W r i t e t o o n l y l a t c h T i m e r Y c o u n t s t o p C ount value I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 T i m e r Y i n t e r r u p t d i s a b l e d Interrupt request register 2 (IREQ2) [Address 3D16] P r o c e s s 6 : W h e n t i m e r Y i n t e r r u p t i s u s e d , s e t “ 1 ” ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r Y i n t e r r u p t e n a b l e b i t N o t i m e r Y i n t e r r u p t r e q u e s t i s s u e d Interrupt control register 2 (ICON2) [Address 3F16] T i m e r Y i n t e r r u p t e n a b l e d Timer Y, Z mode register (TYZM) [Address 2016] T i m e r Y c o u n t s t a r t P r o c e s s 7 : S t a r t c o u n t i n g o f t i m e r Y . P r o c e s s 3 : S e t t i m e r Y c o u n t s o u r c e (N o t e 1) T i m e r c o u n t s o u r c e s e t r e g i s t e r ( T C S S ) [ A d d r e s s 2 E1 T i m e r Y c o u n t s o u r c e s e l e c t i o n b i t s b b f XI N ) f XI N ) O n c h i p o s c i l l a t o r o u t p u t o t e N o t a v a i l a b l e P r e s c a l e r Y ( P R E Y ) ( A d d r e s s 2 11

Rev.2.00 Jun 21, 2004 (3) Application example of timer mode Outline: Pulses generated corresponding to the water flow rate are counted for a fixed period (100 ms), and the water flow rate during this period is calculated. Specifications: Pulses generated corresponding to the water flow rate are input to the P14/CNTR 1 pin and counted using timer X. The contents of timer X are read in the timer Y interrupt processing routine generated after 100 ms from the start of counting pulses, and the water flow rate during 100 ms is calculated. Operation clock: f(X IN) = 8 MHz, high-speed mode Figure 2.5.20 shows an example of peripheral circuit, Figure 2.5.21 shows the method of measuring water flow rate, and Figure 2.5.21 shows an example of control procedure. Fig. 2.5.20 Example of peripheral circuit Fig. 2.5.21 Method of measuring water flow rate G r o u p P 14/ C N T R 0 W a t e r f l o w r a t e s e n s o r Water flow B l a d e s r o t a t e i n p r o p o r t i o n t o w a t e r f l o w a n d g e n e r a t e p u l s e s T h e f a s t e r t h e w a t e r f l o w t h e s h o r t e r t h e p u l s e p e r i o d CNTR 0 pin input T i m e r Y i n t e r r u p t r e q u e s t b i t m s Timer X counting (Note) N o t e C o u n t i n g r i s i n g e d g e s

• Flow rate during 100 ms = (FF16–read value of timer Y) ✕ flow rate per pulse Timer Y interrupt processing routine
• Timer X, timer Y stop counting.
• Timer X is read out. Timer X, timer Y start counting.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.22 Example of control procedure “FF16” “FF16” 0 11 10 01 00 0 01 10 1 00 “ C 71 “ F 91 0 00 END 0 11 10 1 00 RTI F l o w r a t e m e a s u r i n g r o u t i n e Timer Y interrupt processing routine ( P r e s c a l e r X s e t t i n g v a l u e “ F F1 6” t i m e r X s e t t i n g v a l u e F P r e s c a l e r X c o u n t v a l u e t i m e r X c o u n t v a l u e T h e n u m b e e r o f e v e n t w i t h i n m s T X M ( A d d r e s s 2 B1 T C S S ( A d d r e s s 2 E1 T i m e r Y c o u n t s o u r c e : f XI N ) s e l e c t e d T i m e r Y d i v i s i o n r a t i o T i m e r Y p r i m a r y s e t t i n g v a l u e E v e n t c o u n t e r m o d e C o u n t a t f a l l i n g e d g e T i m e r X c o u n t s t o p S e t t i m e r X m o d e r e g i s t e r S e t “ 0 ” t o t h e C N T R 0 i n t e r r u p t e n a b l e b i t . C N T R 0 i n t e r r u p t d i s a b l e d S e t t o t h e t i m e r X i n t e r r u p t e n a b l e b i t T i m e r X i n t e r r u p t d i s a b l e d S e t t o t h e t i m e r Y i n t e r r u p t e n a b l e b i t T i m e r Y i n t e r r u p t d i s a b l e d N o t e : 1 0 0 m s = 1 / 8 M H z ✕ 1 6 ✕ ( C 71 + 1 ) ✕ ( F 91 6 + 1 ) Prescaler X (Address 2C 16) S e t v a l u e t o t i m e r X T i m e r X ( A d d r e s s 2 D 1 Set timer count source set register P r e s c a l e r Y s e t t i n g v a l u e T Y Z M ( A d d r e s s 2 01 Set timer Y, Z mode register T i m e r m o d e W r i t i n g t o l a t c h a n d t i m e r s i m u l t a n e o u s l y T i m e r Y c o u n t s t o p S e t v a l u e t o t i m e r Y (N o t e) P r e s c a l e r Y ( A d d r e s s 2 11 Timer Y primary (Address 2316) Set “1” to the timer Y interrupt enable bit. (Timer Y interrupt enabled) S e t “ 0 ” t o t h e t i m e r Y i n t e r r u p t r e q u e s t b i t . T X M ( A d d r e s s 2 B1 T i m e r X c o u n t s t a r t Set timer X mode register T Y Z M ( A d d r e s s 2 01 Set timer Y, Z mode register T i m e r Y c o u n t s t a r t TXM(Address 2B16) T i m e r X c o u n t s t o p S e t t i m e r X m o d e r e g i s t e r TYZM(Address 2016) S e t t i m e r Y , Z m o d e r e g i s t e r T i m e r Y c o u n t s t o p S e t p o r t P 14 t o t h e i n p u t m o d e .

Rev.2.00 Jun 21, 2004

2.5.4 Programmable waveform generation mode (timer Y and timer Z)

The basic operation of Timer Y and Timer Z are the same. In this section, Timer Y is explained. (1) Operation description In the programmable waveform generation mode, timer counts the setting value of timer Y primary (TYP) and the setting value of timer Y secondary (TYS) alternately, the waveform whose polarity is inverted each time Timer Y underflows is output from P0 1/TYOUT pin. When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch only”. Also, set the port P01 direction registers to output mode. The active edge of output waveform is set by the timer Y output level latch. When “0” is set to the timer Y output level latch, “H” interval by the setting value of TYP or “L” interval by the setting value of TYS is output alternately. When “1” is set to the timer Y output level latch, “L” interval by the setting value of TYP or “H” interval by the setting value of TYS is output alternately. Also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer Y primary waveform extension control bit (b2) and the timer Y secondary waveform extension control bit (b3) of PUM to “1”. As a result, the waveforms of more accurate resolution can be output. When b2 and b3 of PUM are used, the frequency and duty of the output waveform are as follows; Waveform frequency: FYOUT= Duty: DYOUT= TMYCL: Timer Y count source (frequency) TYP: Timer Y primary TYS: Timer Y secondary EXPYP (1 bit): Timer Y primary waveform extension control bit EXPYS (1 bit): Timer Y secondary waveform extension control bit In the programmable waveform generation mode, when values of the TYP, TYS, EXPYP and EXPYS are changed, the output waveform is changed at the beginning (timer Y primary waveform interval) of waveform period. When the count values are changed, set values to the TYS, EXPYP and EXPYS first. After then, set the value to TYP. The values are set all at once at the beginning of the next waveform period when the value is set to TYP. (When writing at timer stop is executed, writing to TYP at last is required.) Timer Y can stop counting by setting “1” to the timer Y count stop bit. Also, when timer Y underflows, the timer Y interrupt request bit is set to “1”. Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) 2 ✕ (TMYCL) (2 ✕ (TYP+1)+EXPYP)+(2 ✕ (TYS+1)+EXPYS)) 2 ✕ (TYP+1)+EXPYP (2 ✕ (TYP+1)+EXPYP)+(2 ✕ (TYS+1)+EXPYS))

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Notes 1: In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again. 2: In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultaneously. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Y interrupt. Writing is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary and a secondary setting values, and primary write timing, it may be impossible.) 3: The waveform extension function by the timer Y waveform extension control bits can be used only when “00 16” is set to Prescaler Y. When the value other than “0016” is set to Prescaler Y, be sure to set “0” to EXPYP and EXPYS. The waveform extension function by the timer Z waveform extension control bits can be used only when “00 16” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. 4: When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch only”. 5: When TYS is read out, the undefined value is read out. However, while timer Y counts the setting value of TYS, the count value during the secondary interval can be obtained by reading the timer Y primary. 6: In order to use TY OUT pin, set “1” to bit 1 of the port P0 direction register (output mode). Figure 2.5.23 shows the timing diagram of the programmable waveform generation mode.

Rev.2.00 Jun 21, 2004 Fig. 2.5.23 Timing diagram of programmable waveform generation mode T i m e r Y p r i m a r y r e l o a d C o n t e n t s o f t i m e r Y TY OUT pin output Timer Y count clock T i m e r Y c o u n t s t o p b i t T i m e r Y i n t e r r u p t r e q u e s t b i t T i m e r Y o u t p u t l e v e l l a t c h i s w r i t t e n Count start 6 0 6 0016 0216 0 6 0 6 0316 0 6 0 6 0 6 0216 0 G W h e n i s s e t t o T Y P a n d i s s e t t o T Y S Underflow U n d e r f l o w U n d e r f l o w T i m e r Y s e c o n d a r y r e l o a d S e c o n d a r y w a v e f o r m e x t e n s i o n o t e 2) (N o t e 2)( N o t e Initialized to “L” Waveform output start Notes 1: In this case, timer Y primary waveform is not extended, timer Y secondary waveform is extended. 2: In this time, “0” is written to the timer Y interrupt request bit or the timer Y interrupt request bit is cleared to “0” by accepting the timer Y interrupt request. T i m e r Y s e c o n d a r y r e l o a d (Note 1) i s w r i t t e n Waveform output invertedWaveform output inverted Waveform output inverted

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z (2) Programmable waveform generation mode setting method Figure 2.5.24 and Figure 2.5.25 show the setting method for programmable waveform generation mode of timer Y. When timer Z is used, registers are set by the same method. Fig. 2.5.24 Setting method for programmable waveform generation mode (1) b 7b 0 1 11 b 7b 0 T i m e r Y p r i m a r y w a v e f o r m e x t e n s i o n c o n t r o l b i t (N o t e) W a v e f o r m n o t e x t e n d e d W a v e f o r m e x t e n d e d T i m e r Y s e c o n d a r y w a v e f o r m e x t e n s i o n c o n t r o l b i t o t W a v e f o r m n o t e x t e n d e d W a v e f o r m e x t e n d e d T i m e r Y o u t p u t l e v e l l a t c h I n i t i a l s t a t e a t s t o p L H i n t e r v a l b y T Y P s e t t i n g v a l u e L i n t e r v a l b y T Y S s e t t i n g v a l u e I n i t i a l s t a t e a t s t o p H L i n t e r v a l b y T Y P s e t t i n g v a l u e H i n t e r v a l b y T Y S s e t t i n g v a l u e P r o c e s s 4 : S e t T YO U T p i n t o t h e o u t p u t (N o t e) . P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D ) [ A d d r e s s 0 11 Set P01/TYOUT pin as the output mode b 7b 0 Note: For timer Z, set TZOUT pin as the output by bit 2 of P0D. b7 b0 N o t e : W h e n u s i n g t h i s m o d e , b e s u r e t o s e t “ 1 ” t o t h e t i m e r Y w r i t e c o n t r o l b i t t o s e l e c t w r i t e t o l a t c h o n l y P r o c e s s 1 : D i s a b l e t i m e r Y i n t e r r u p t . P r o c e s s 2 : S e t t i m e r Y , Z m o d e r e g i s t e r . T i m e r Y , Z m o d e r e g i s t e r ( T Y Z M ) [ A d d r e s s 2 01 P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e W r i t e t o o n l y l a t c h o t T i m e r Y c o u n t s t o p I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 T i m e r Y i n t e r r u p t d i s a b l e d Process 3: Set timer Y, Z waveform output control register. T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r ( P U M ) [ A d d r e s s 2 41 N o t e : T h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r Y w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n i s s e t t o p r e s c a l e r Y W h e n t h e v a l u e o t h e r t h a n i s s e t t o p r e s c a l e r Y b e s u r e t o s e t t o E X P Y P a n d E X P Y S T h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r Z w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n i s s e t t o p r e s c a l e r Z W h e n t h e v a l u e o t h e r t h a n i s s e t t o p r e s c a l e r Z b e s u r e t o s e t t o E X P Z P a n d E X P Z S A l s o w h e n t h e t i m e r Y u n d e r f l o w i s s e l e c t e d a s t h e t i m e r Z c o u n t s o u r c e t h e w a v e f o r m e x t e n s i o n f u n c t i o n c a n n o t b e u s e d

Rev.2.00 Jun 21, 2004 Fig. 2.5.25 Setting method for programmable waveform generation mode (2) b7 b 0 0 11 b7 b 0 b 7b 0 P r o c e s s 7 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t n o r e q u e s t e d t o t h e t i m e r Y i n t e r r u p t r e q u e s t b i t I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 3 D 1 P r o c e s s 8 : W h e n T i m e r Y i n t e r r u p t i s u s e d , s e t “ 1 ” ( i n t e r r u p t e n a b l e d ) t o t h e t i m e r Y i n t e r r u p t e n a b l e b i t N o t i m e r Y i n t e r r u p t r e q u e s t i s s u e d Interrupt control register 2 (ICON2) [Address 3F16] Timer Y interrupt enabled T i m e r Y , Z m o d e r e g i s t e r ( T Y Z M ) [ A d d r e s s 2 01 Timer Y count start P r o c e s s 9 : S t a r t c o u n t i n g o f t i m e r Y . b 7b 0 N o t e s 1 : F o r T i m e r Z , f ( XI N ) / 1 6 , f ( XI N ) / 2 , o r t i m e r Y u n d e r f l o w c a n b e s e l e c t e d . H o w e v e r w h e n t h e t i m e r Z w a v e f o r m e x p a n s i o n f u n c t i o n i s u s e d d o n o t s e l e c t t h e t i m e r Y u n d e r f l o w f o r t h e t i m e r Z c o u n t s o u r c e S e t t h e o n c h i p o s c i l l a t o r o s c i l l a t i o n t o b e e n a b l e d b y b i t o n c h i p o s c i l l a t o r o s c i l l a t i o n c o n t r o l b i t o f C P U m o d e r e g i s t e r P r o c e s s 6 : S e t t h e c o u n t v a l u e t o t i m e r Y (N o t e 1) .

• S e t t h e c o u n t v a l u e t o p r e s c a l e r Y , t i m e r Y s e c o n d a r y a n d t i m e r Y p r i m a r y C ount value Timer Y secondary (TYS) (Address 2216) C ount value P r o c e s s 5 : S e t t i m e r Y c o u n t s o u r c e (N o t e 1) . T i m e r c o u n t s o u r c e s e t r e g i s t e r ( T C S S ) [ A d d r e s s 2 E1 Timer Y count source selection bits b3 b2 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : On-chip oscillator output (Note 2) 1 1 : Not available P r e s c a l e r Y ( P R E Y ) ( A d d r e s s 2 11 6) (N o t e 2) T i m e r Y p r i m a r y ( T Y P ) ( A d d r e s s 2 31 6) (N o t e s 3 , 4) C o u n t v a l u e N o t e s 1 : I n t h e p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e , v a l u e s o f T Y S , E X P Y P a n d E X P Y S a r e v a l i d b y w r i t i n g t o T Y P E v e n w h e n c h a n g i n g T Y P i s n o t r e q u i r e d w r i t e t h e s a m e v a l u e a g a i n W h e n t h e t i m e r Y w a v e f o r m e x t e n s i o n f u n c t i o n i s u s e d b e s u r e t o s e t t o p r e s c a l e r Y I n t h e p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e w h e n t h e s e t t i n g v a l u e i s c h a n g e d w h i l e t h e w a v e f o r m i s o u t p u t s e t b y s o f t w a r e i n o r d e r n o t t o e x e c u t e t h e w r i t i n g t o T Y P a n d t h e t i m i n g o f t i m e r Y u n d e r f l o w d u r i n g t h e s e c o n d a r y i n t e r v a l s i m u l t a n e s o u s l y C o u n t v a l u e s o f t h e p r i m a r y i n t e r v a l a n d s e c o n d a r y i n t e r v a l c a n b e c h e c k e d b y r e a d i n g t h e T Y P T Y S i s u n d e f i n e d a t r e a d

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z (3) Application example of programmable waveform generation mode Outline: The waveform extension function is used and the waveform output is executed. Specifications: The “H” width generated by TYP and the “L” width generated by TYS are output. Set each waveform extension function to be valid, and set the duty ratio to be 2:1. The frequency is 40 kHz. Operation clock: f(XIN) = 8 MHz, high-speed mode Figure 2.5.26 shows an example of waveform output and Figure 2.5.27 shows an example of control procedure. Fig. 2.5.26 Example of waveform output G 4 0 k H z p u l s e i s o u t p u t T YO U T p i n o u t p u t 16.7 µs8 . 3 µs Duty ratio W a v e f o r m e x t e n d e d 21 : Waveform extended

Rev.2.00 Jun 21, 2004 Fig. 2.5.27 Example of control procedure “ 0 01 “ 2 01 R E S E T 01 01 P r o c e s s i n g 1 11 C L I 0 11 Timer Y primary waveform generation extended (Note 3) Timer Y secondary waveform generation extended (Note 3) Initial state: “L”, TYP: “H” interval, TYS: “L” interval PUM(Address 2416) “4116” 0 11 T C S S ( A d d r e s s 2 E1 T i m e r Y c o u n t s o u r c e : f XI N ) s e l e c t e d Set port P01 to the output mode. S e t “ 0 ” t o t h e t i m e r Y i n t e r r u p t e n a b l e b i t . T i m e r Y i n t e r r u p t d i s a b l e d Prescaler Y (Address 2116) S e t v a l u e t o t i m e r Y (N o t e s 3 , 4 , 5 , 6) S e t t i m e r c o u n t s o u r c e s e t r e g i s t e r T Y Z M ( A d d r e s s 2 01 S e t t i m e r Y , Z m o d e r e g i s t e r P r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e W r i t i n g t o o n l y l a t c h o t e T i m e r Y c o u n t s t o p T i m e r Y p r i m a r y ( A d d r e s s 2 31 S e t “ 1 ” t o t h e t i m e r Y i n t e r r u p t e n a b l e b i t . T i m e r Y i n t e r r u p t e n a b l e d S e t “ 0 ” t o t h e t i m e r Y i n t e r r u p t r e q u e s t b i t . T Y Z M ( A d d r e s s 2 01 Set timer Y, Z mode register T i m e r Y c o u n t s t a r t I n i t i a l i z a t i o n SEI CLD CLT CPUM(Address 3B 16) ← 10000X002 Wait until f(XIN) oscillation is stabilized (Note 1) CPUM(Address 3B16) ← 00000X002 X: This bit is not used here. Set it to “0” or “1” arbitrary. Timer Y secondary (Address 2216) Set timer Y, Z waveform output control register N o t e s 1 : F o r t h e c o n c r e t e t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . W h e n u s i n g t h i s m o d e b e s u r e t o s e l e c t w r i t e t o l a t c h o n l y T h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r Y w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n i s s e t t o p r e s c a l e r Y W h e n t h e v a l u e o t h e r t h a n i s s e t t o p r e s c a l e r Y b e s u r e t o s e t t o E X P Y P a n d E X P Y S I n t h e p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e v a l u e s o f T Y S E X P Y P a n d E X P Y S a r e v a l i d b y w r i t i n g t o T Y P E v e n w h e n c h a n g i n g T Y P i s n o t r e q u i r e d w r i t e t h e s a m e v a l u e a g a i n I n t h e p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e w h e n t h e s e t t i n g v a l u e i s c h a n g e d w h i l e t h e w a v e f o r m i s o u t p u t s e t b y s o f t w a r e i n o r d e r n o t t o e x e c u t e t h e w r i t i n g t o T Y P a n d t h e t i m i n g o f t i m e r Y u n d e r f l o w d u r i n g t h e s e c o n d a r y i n t e r v a l s i m u l t a n e s o u s l y C o u n t v a l u e s o f t h e p r i m a r y i n t e r v a l a n d s e c o n d a r y i n t e r v a l c a n b e c h e c k e d b y r e a d i n g T Y P T Y S i s u n d e f i n e d a t r e a d

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z

2.5.5 Programmable one-shot generation mode (timer Z)

(1) Operation description In the programmable one-shot generation mode, the one-shot pulse by the setting value of timer Z primary can be output from P0 2/TZOUT pin by software or external trigger to the P37/INT0 pin. When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. Also, set the port P0 2 direction registers to output mode. In this mode, the timer Z secondary (TZS) is not used. The active edge of output waveform is set by the timer Z output level latch. When “0” is set to the timer Z output level latch, “H” pulse during the interval of the timer Z primary (TZP) setting value is output. When “1” is set to the timer Z output level latch, “L” pulse during the interval of the TZP setting value is output. Also, in this mode, the interval of the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (EXPZP) to “1”. As a result, the waveforms of more accurate resolution can be output. During the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing “0” to the timer Z one-shot start bit. In the programmable one-shot generation mode, when the count values are changed, set value to the EXPZP first. After then, set the value to TZP. The values are set all at once at the beginning of the next one-shot pulse when the value is set to TZP. (Even when writing at timer stop is executed, writing to TZP at last is required.) Timer Z can stop counting by setting “1” to the timer Z count stop bit. Also, when timer Z underflows, the timer Z interrupt request bit is set to “1”. Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) Notes 1: In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again. 2: In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow simultaneously. An example of a measurement is shown below. ex.) The underflow of timer is stored by polling etc. using timer Z interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT 0 pin, it may be impossible.) 3: The waveform extension function by the timer Z waveform extension control bits can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. 4: When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. 5: In order to use TZOUT pin, set “1” to bit 2 of the port P0 direction register (output mode). 6: Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit. Figure 2.5.28 shows the timing diagram of the programmable one-shot generation mode.

Rev.2.00 Jun 21, 2004 Fig. 2.5.28 Timing diagram of programmable one-shot generation mode 6 0116 0016 0 60316 0 6 0 6 0 (Note 3) O n e s h o t s t a r t b i t I N p i n i n p u t o t e S e t t o b y I N p i n i n p u t t r i g g e r C o n t e n t s o f t i m e r Z T ZO U T p i n o u t p u t T i m e r Z c o u n t c l o c k T i m e r Z c o u n t s t o p b i t T i m e r Z i n t e r r u p t r e q u e s t b i t Timer Z output level latch i s w r i t t e n Count start G W h e n i s s e t t o T Z P Underflow Timer Z primary reload Waveform extension I n i t i a l i z e d t o L Waveform output start Notes 1: In this case, INT0 pin one-shot trigger valid. 2: In this case, timer Z primary waveform is extended. 3: In this time, “0” is written to the timer Z interrupt request bit or the timer Z interrupt request bit is cleared to “0” by accepting the timer Z interrupt request. (Note 2) “0” is written i s w r i t t e n U n d e r f l o w Timer Z primary reload C o u n t s t a r t W a v e f o r m e x t e n s i o n W a v e f o r m o u t p u t s t a r tW a v e f o r m o u t p u t e n d Waveform output end

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.29 Setting method for programmable one-shot generation mode (1) (2) Event counter mode setting method Figure 2.5.29 to Figure 2.5.31 show the setting method for programmable one-shot generation mode of timer Z. b 7b 0 b7 b0 1 011 b7 b0 b 7b 0 b 7b 0 T i m e r Z p r i m a r y w a v e f o r m e x t e n s i o n c o n t r o l b i t (N o t e 1) W a v e f o r m n o t e x t e n d e d W a v e f o r m e x t e n d e d T i m e r Z o u t p u t l e v e l l a t c h I n i t i a l s t a t e a t s t o p L H i n t e r v a l b y T Z P s e t t i n g v a l u e L i n t e r v a l b y T Z S s e t t i n g v a l u e I n i t i a l s t a t e a t s t o p H L i n t e r v a l b y T Z P s e t t i n g v a l u e H i n t e r v a l b y T Z S s e t t i n g v a l u e I N p i n o n e s h o t t r i g g e r c o n t r o l b i t o t e I N p i n o n e s h o t t r i g g e r i n v a l i d I N p i n o n e s h o t t r i g g e r v a l i d I N p i n o n e s h o t t r i g g e r a c t i v e e d g e s e l e c t i o n b i t o t e F a l l i n g e d g e t r i g g e r R i s i n g e d g e t r i g g e r P r o c e s s 4 : S e t T ZO U T p i n t o t h e o u t p u t (N o t e) . Port P0 direction register (P0D) [Address 0116] S e t P 02/ T ZO U T p i n a s t h e o u t p u t m o d e Note: When using this mode, be sure to select “write to latch only”. P r o c e s s 1 : D i s a b l e t h e i n t e r r u p t . Process 2: Set timer Y, Z mode register. T i m e r Y , Z m o d e r e g i s t e r ( T Y Z M ) [ A d d r e s s 2 01 P r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e W r i t e t o o n l y l a t c h o t T i m e r Y c o u n t s t o p I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E1 INT0 interrupt disabled Process 3: Set timer Y, Z waveform output control register. Timer Y, Z waveform output control register (PUM) [Address 2416] N o t e s 1 : T h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r Z w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n i s s e t t o p r e s c a l e r Z W h e n t h e v a l u e o t h e r t h a n i s s e t t o p r e s c a l e r Z b e s u r e t o s e t t o E X P Z P A l s o w h e n t h e t i m e r Y u n d e r f l o w i s s e l e c t e d a s t h e t i m e r Z c o u n t s o u r c e t h e w a v e f o r m e x t e n s i o n f u n c t i o n c a n n o t b e u s e d S t o p t i m e r Z t o c h a n g e t h e s e b i t s I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 T i m e r Z i n t e r r u p t d i s a b l e d

Rev.2.00 Jun 21, 2004 Fig. 2.5.30 Setting method for programmable one-shot generation mode (2) Prescaler Z (PREZ) [Address 2516] (Note 2) P r o c e s s 8 : S e t t h e s t a n d b y s t a t e t o a c c e p t t h e o n e - s h o t s t a r t t r i g g e r (N o t e) . b 7b 0

0 Timer Y, Z mode register (TYZM) [Address 2016]

T i m e r Z c o u n t s t a r t 011 Process 7: Set the one-shot pulse width (Note 1).

• S e t t h e c o u n t v a l u e t o p r e s c a l e r Z a n d t i m e r Z p r i m a r y C o u n t v a l u e C o u n t v a l u e Timer Z primary (TZP) [Address 2716] (Note 3) N o t e : W h e n t h e I N T0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t o f P U M i s s e t t o “ v a l i d ” , t i m e r Z c o u n t i n g i s s t a r t e d b y t h e i n p u t o f t r i g g e r t o I N p i n a f t e r t h i s s e t t i n g Notes 1: In the programmable one-shot generation mode, TZS is not used. When the count setting value is changed, value of EXPZP is valid by writing to TZP. Even when changing TZP is not required, write the same value again. 2: When the timer Z waveform extension function is used, be sure to set “00 16” to prescaler Z. 3: In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer Z underflow simultanesously. P r o c e s s 6 : S e t t h e t i m e r Z c o u n t s o u r c e . b7 b0 T i m e r c o u n t s o u r c e s e t r e g i s t e r ( T C S S ) [ A d d r e s s 2 E1 T i m e r Z c o u n t s o u r c e s e l e c t i o n b i t s b b f XI N ) f XI N ) T i m e r Y u n d e r f l o w o t e N o t a v a i l a b l e Process 5: When the trigger by INT0 pin input is selected: Set port P3 direction register, pull-up control register and port P1P3 control register P u l l - u p c o n t r o l r e g i s t e r ( P U L L ) [ A d d r e s s 1 61 P 37 p u l l - u p c o n t r o l b i t P u l l u p O f f P u l l u p O n b 7b 0 P o r t P 1 P 3 c o n t r o l r e g i s t e r ( P 1 P 3 C ) [ A d d r e s s 1 71 P 37/ I N T0 i n p u t l e v e l s e l e c t i o n b i t C M O S l e v e l T T L l e v e l b 7b 0 P o r t P 3 d i r e c t i o n r e g i s t e r ( P 3 D ) [ A d d r e s s 0 71 S e t P 37/ I N T0 p i n a s t h e i n p u t m o d e b 7b 0 Note: When the timer Z waveform extension function is used, do not select the timer Y underflow as the timer Z count source.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.31 Setting method for programmable one-shot generation mode (3) b N o t e : P u l s e i s o u t p u t f r o m T ZO U T p i n . A f t e r o u t p u t , t h i s b i t i s i n i t i a l i z e d t o “ 0 ” . b 7b 0 b b 7b 0 N o t e : W h e n t h e I N T0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t i s s e t t o “ v a l i d ” , t h e I N i n t e r r u p t c a n b e a c c e p t e d a f t e r t h i s s e t t i n g b b G W h e n t h e I N p i n o n e s h o t t r i g g e r c o n t r o l b i t o f P U M i s s e t t o v a l i d t h e t i m e r Z c o u n t i s s t a r t e d b y i n p u t o f t r i g g e r t o t h e I N p i n P r o c e s s 9 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t n o r e q u e s t e d t o t h e t i m e r Z i n t e r r u p t r e q u e s t b i t I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 3 D 1 P r o c e s s 1 0 : W h e n t h e i n t e r r u p t i s u s e d , s e t “ 1 ” ( i n t e r r u p t e n a b l e d ) t o t h e c o r r e s p o n d i n g i n t e r r u p t e n a b l e b i t N o T i m e r Z i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E1 I N T0 i n t e r r u p t e n a b l e d (N o t e) O n e - s h o t s t a r t r e g i s t e r ( O N S ) [ A d d r e s s 2 A1 T i m e r Z o n e - s h o t s t a r t (N o t e) P r o c e s s 1 1 : S t a r t c o u n t i n g o f t i m e r Z . I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E ) [ A d d r e s s 3 A1 I N T0 i n t e r r u p t e d g e s e l e c t i o n b i t F a l l i n g e d g e a c t i v e R i s i n g e d g e a c t i v e I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 3 C 1 N o I N T0 i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 T i m e r Y i n t e r r u p t e n a b l e d G W h e n t h e I N p i n o n e s h o t t r i g g e r c o n t r o l b i t o f P U M i s s e t t o v a l i d a n d t h e I N i n t e r r u p t i s u s e d s e t t h e f o l l o w i n g

Rev.2.00 Jun 21, 2004 (3) Application example of programmable one-shot generation mode Outline: The phase control signal to the load is output by using the programmable one-shot generation mode of Timer Z. Specifications: The phase control signal to the load is output from the P02/TZOUT pin using the programmable one-shot generation mode of timer Z.

• Count source: f(XIN)/16
• Rising edges of the signal input to the P37/INT0 pin from the trigger detection circuit are detected.
• A triac is turned on at the “H” level. The period of the feedback signal input from the load is measured, analyzed, and used to adjust the phase control signal. Operation clock: f(XIN) = 8 MHz, high-speed mode For the measurement of the period of the feedback signal, refer to the period measurement mode of the using timer. Figure 2.5.32 shows an example of peripheral circuit, Figure 2.5.33 shows an example of an operation timing, and Figure 2.5.34 shows an example of a control procedure. Fig. 2.5.32 Example of peripheral circuit Fig. 2.5.33 Example of operation timing 7 5 4 0 G r o u p P37/INT0 P02/TZOUT VA C T r i g g e r d e t e c t i o n c i r c u i t Port F e e d b a c k s i g n a l Phase control signal Load INT0 pin input VAC power source C o n t e n t s o f t i m e r Z TZOUT pin output RL R L R L RL R L U F UF UF U F U F UF W riting to latch in INT0 interrupt processing routine 0 0 0 01 RL

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.34 Example of control procedure Timer Z primary (Address 2716) Prescaler Z (Address 2516) 01 00 CLI R E S E T 1 11 011 S e t p u l l - u p c o n t r o l r e g i s t e r S e t p o r t P P c o n t r o l r e g i s t e r

1 T Y Z M ( A d d r e s s 2 01

Timer Z count start (Note 7) S e t t h e s t a n d b y s t a t e t o a c c e p t o n e - s h o t s t a r t t r i g g e r 0 10 I N T E D G E ( A d d r e s s 3 A1 I N T0 r i s i n g e d g e a c t i v e S e t t h e i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r P h a s e c o n t r o l p r o c e s s i n g G P e r i o d m e a s u r e m e n t o f f e e d b a c k s i g n a l G A n a l y z e o f m e a s u r e d v a l u e d e t e r m i n a t i o n o f t i m e r Z s e t t i n g v a l u e INT0 interrupt processing routine C h a n g e o f t i m e r Z R T I T i m e r Z p r i m a r y w a v e f o r m g e n e r a t i o n e x t e n d e d o t e I n i t i a l s t a t e L T Z P H i n t e r v a l T Z S L i n t e r v a l s t o p a t L a f t e r u n d e r f l o w I N p i n o n e s h o t t r i g g e r v a l i d o t e I N p i n r i s i n g e d g e t r i g g e r o t e P U M ( A d d r e s s 2 41 TCSS(Address 2E16) T i m e r Z c o u n t s o u r c e : f XI N ) s e l e c t e d S e t p o r t P 02 t o t h e o u t p u t m o d e . Set “0” to the timer Z interrupt enable bit. (Timer Z interrupt disabled) Set value to timer Z (Notes 3, 5, 6) Set timer count source set register (Note 3) T Y Z M ( A d d r e s s 2 01 S e t t i m e r Y , Z m o d e r e g i s t e r P r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e W r i t i n g t o o n l y l a t c h o t e T i m e r Z c o u n t s t o p S e t “ 1 ” t o t h e I N T0 i n t e r r u p t e n a b l e b i t . I N i n t e r r u p t e n a b l e d S e t “ 0 ” t o t h e I N T0 i n t e r r u p t r e q u e s t b i t . I n i t i a l i z a t i o n S E I C L D C L T C P U M A d d r e s s 6) ← X W a i t u n t i l f XI N ) o s c i l l a t i o n i s s t a b i l i z e d o t e C P U M A d d r e s s 6) ← X S e t t i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r X : T h i s b i t i s n o t u s e d h e r e . S e t i t t o “ 0 ” o r “ 1 ” a r b i t r a r y . Set port P37 to the input mode. N o t e s 1 : F o r t h e c o n c r e t e t i m e , a s k t h e o s c i l l a t o r m a n u f a c t u r e . W h e n u s i n g t h i s m o d e b e s u r e t o s e l e c t w r i t e t o l a t c h o n l y T h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r Z w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n i s s e t t o p r e s c a l e r Z W h e n t h e v a l u e o t h e r t h a n i s s e t t o p r e s c a l e r Z b e s u r e t o s e t t o E X P Z P A l s o w h e n t h e t i m e r Y u n d e r f l o w i s s e l e c t e d a s t h e t i m e r Z c o u n t s o u r c e t h e w a v e f o r m e x t e n s i o n f u n c t i o n c a n n o t b e u s e d S t o p t i m e r Z t o c h a n g e t h e I N p i n o n e s h o t t r i g g e r c o n t r o l b i t a n d I N o n e s h o t t r i g g e r a c t i v e e d g e s e l e c t i o n b i t I n t h e p r o g r a m m a b l e o n e s h o t g e n e r a t i o n m o d e t h e v a l u e o f E X P Z P i s v a l i d b y w r i t i n g t o T Z P E v e n w h e n c h a n g i n g T Z P i s n o t r e q u i r e d w r i t e t h e s a m e v a l u e a g a i n I n t h e p r o g r a m m a b l e o n e s h o t g e n e r a t i o n m o d e w h e n t h e s e t t i n g v a l u e i s c h a n g e d w h i l e t h e w a v e f o r m i s o u t p u t s e t b y s o f t w a r e i n o r d e r n o t t o e x e c u t e t h e w r i t i n g t o T Z P a n d t h e t i m i n g o f t i m e r Z u n d e r f l o w s i m u l t a n e s o u s l y I n t h i s s t a t e t i m e r c o u n t i s n o t s t a r t e d

Rev.2.00 Jun 21, 2004

2.5.6 Programmable wait one-shot generation mode (timer Z)

(1) Operation description In the programmable wait one-shot generation mode, the one-shot pulse by the setting value of timer Z secondary (TZS) can be output from P02/TZOUT pin by software or external trigger to P37/INT0 pin after the wait by the setting value of the timer Z primary (TZP). When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. Also, set the port P0 2 direction registers to output mode. The active edge of output waveform is set by the timer Z output level latch. When “0” is set to the timer Z output level latch, after the wait during the interval of the TZP setting value, “H” pulse during the interval of the TZS setting value is output. When “1” is set to the timer Z output level latch, after the wait during the interval of the TZP setting value, “L” pulse during the interval of the TZS setting value is output. Also, in this mode, the intervals of the wait and the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (EXPZP) and the timer Z secondary waveform extension control bit (EXPZS) to “1”. As a result, the waveforms of more accurate resolution can be output. In the programmable wait one-shot generation mode, the trigger by software or the external INT 0 pin can be accepted by writing “0” to the timer Z count stop bit after the count value is set. (At the time when “0” is written to the timer Z count stop bit, Timer Z stops.) By writing “1” to the timer Z one-shot start bit, or by inputting the valid trigger to the INT 0 pin after the trigger to the INT0 pin becomes valid by writing “1” to the INT0 pin one-shot trigger control bit, Timer Z starts counting. While Timer Z counts the TZP, the initial value of the TZOUT pin output is retained. When Timer Z underflows, the value of TZS is reloaded, at the same time, the output of TZOUT pin is inverted. When Timer Z underflows, the output of TZOUT pin is inverted again and Timer Z stops. When also the trigger of INT0 pin is accepted, the contents of the one-shot start bit is changed to “1” by hardware. The falling or rising can be selected as the edge of the valid trigger of INT0 pin by the INT0 pin one- shot trigger edge selection bit. During the wait interval and the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing “0” to the timer Z one-shot start bit. In the programmable wait one-shot generation mode, when the count values are changed, set values to the TZS, EXPZP and EXPZS first. After then, set the value to TZP. The values are set all at once at the beginning of the next wait interval when the value is set to TZP. (When writing at timer stop is executed, writing to TZP at last is required.) Timer Z can stop counting by setting “1” to the timer Z count stop bit. Also, when timer Z underflows, the timer Z interrupt request bit is set to “1”. Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.)

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Notes 1: In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. 2: In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultaneously. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Z interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT 0 pin, it may be impossible.) 3: The waveform extension function by the timer Z waveform extension control bits can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. 4: When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. 5: When TZS is read out, the undefined value is read out. However, while Timer Z counts the setting value of TZS (during one-shot output), the count value during the secondary interval can be obtained by reading TZP. 6: In order to use TZOUT pin, set “1” to bit 2 of the port P0 direction register (output mode). 7: Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit. Figure 2.5.35 shows the timing diagram of the programmable wait one-shot generation mode.

Rev.2.00 Jun 21, 2004 Fig. 2.5.35 Timing diagram of programmable wait one-shot generation mode 6 0116 0 6 0 6 0116 0 W a i t s t a r t 03160 (Note 3)(Note 3) O n e s h o t s t a r t b i t I N p i n i n p u t o t e S e t t o b y I N p i n i n p u t t r i g g e r C o n t e n t s o f t i m e r Z T ZO U T p i n o u t p u t Timer Z count clock T i m e r Z c o u n t s t o p b i t T i m e r Z i n t e r r u p t r e q u e s t b i t T i m e r Z o u t p u t l e v e l l a t c h i s w r i t t e n C o u n t s t a r t G W h e n i s s e t t o T Z P a n d i s s e t t o T Z S Underflow Timer Z secondary reload Initialized to “L” N o t e s I n t h i s c a s e I N p i n o n e s h o t t r i g g e r v a l i d r i s i n g e d g e t r i g g e r s e l e c t e d I n t h i s c a s e t i m e r Z p r i m a r y w a v e f o r m i s e x t e n d e d t i m e r Z s e c o n d a r y w a v e f o r m i s n o t e x t e n d e d I n t h i s t i m e i s w r i t t e n t o t h e t i m e r Z i n t e r r u p t r e q u e s t b i t o r t h e t i m e r Z i n t e r r u p t r e q u e s t b i t i s c l e a r e d t o b y a c c e p t i n g t h e t i m e r Z i n t e r r u p t r e q u e s t o t e “0” is written i s w r i t t e n U n d e r f l o w Timer Z primary reload C o u n t s t a r t W a v e f o r m e x t e n s i o n W a v e f o r m o u t p u t e n dWaveform output start

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.36 Setting method for programmable wait one-shot generation mode (1) b7 b0 b 1 11 1 b7 b0 b b Timer Z primary waveform extension control bit (N ote 1) 0: Waveform not extended 1: Waveform extended Timer Z secondary waveform extension control bit (Note 1) 0: Waveform not extended 1: Waveform extended Timer Z output level latch 0: “L” level is output at timer stop. When count is started, “L” level is output during the TZP interval (wait), and them, “H” level is output during the TZS interval (one-shot) and timer Z output is stopped at “L” level by underflow. 1: “H” level is output at timer stop. When count is started, “H” level is output during the TZP interval (wait), and them, “L” level is output during the TZS interval (one-shot) and timer Z output is stopped at “H” level by underflow. INT 0 pin one-shot trigger control bit (Note 2) 0: INT0 pin one-shot trigger invalid 1: INT0 pin one-shot trigger valid INT0 pin one-shot trigger active edge selection bit (Note 2) 0: Falling edge trigger 1: Rising edge trigger P r o c e s s 4 : S e t T ZO U T p i n t o t h e o u t p u t . Port P0 direction register (P0D) [Address 0116] S e t P 02/ T ZO U T p i n a s t h e o u t p u t m o d e Note: When using this mode, be sure to select “write to latch only”. P r o c e s s 1 : D i s a b l e i n t e r r u p t . P r o c e s s 2 : S e t t i m e r Y , Z m o d e r e g i s t e r . T i m e r Y , Z m o d e r e g i s t e r ( T Y Z M ) [ A d d r e s s 2 01 P r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n m o d e W r i t e t o o n l y l a t c h o t T i m e r Y c o u n t s t o p I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E1 I N T 0 i n t e r r u p t d i s a b l e d Process 3: Set timer Y, Z waveform output control register. T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r ( P U M ) [ A d d r e s s 2 41 N o t e s 1 : T h e w a v e f o r m e x t e n s i o n f u n c t i o n b y t h e t i m e r Z w a v e f o r m e x t e n s i o n c o n t r o l b i t s c a n b e u s e d o n l y w h e n i s s e t t o p r e s c a l e r Z W h e n t h e v a l u e o t h e r t h a n i s s e t t o p r e s c a l e r Z b e s u r e t o s e t t o E X P Z P a n d E X P Z S A l s o w h e n t h e t i m e r Y u n d e r f l o w i s s e l e c t e d a s t h e t i m e r Z c o u n t s o u r c e t h e w a v e f o r m e x t e n s i o n f u n c t i o n c a n n o t b e u s e d S t o p T i m e r Z t o c h a n g e t h e s e b i t s Interrupt control register 2 (ICON2) [Address 3F16] T i m e r Z i n t e r r u p t d i s a b l e d (2) Programmable wait one-shot generation mode setting method Figure 2.5.36 to Figure 2.5.38 show the setting method for programmable wait one-shot generation mode of Timer Z.

Rev.2.00 Jun 21, 2004 Fig. 2.5.37 Setting method for programmable wait one-shot generation mode (2) b7 b b7 b 0 b7 b 0 b7 b 0 Prescaler Z (PREZ) [Address 2516] (Note 2) Process 7: Set the wait interval, one-shot pulse width (Note 1).

• Set the wait interval to the timer Z primary, and one-shot pulse width to the timer Z secondary. C ount value C o u n t v a l u e T i m e r Z s e c o n d a r y ( T Z S ) [ A d d r e s s 2 61 Notes 1: In the programmable wait one-shot generation mode, values of TZS, EXPZP, and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. 2: When the timer Z waveform extension function is used, be sure to set “00 16” to prescaler Z. 3: In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer Z underflow during the secondary interval simultanesously. 4: Count values of the primary interval (during wait) and secondary interval (during one-shot output) can be checked by reading TZP (TZS is undefined at read). P r o c e s s 6 : S e t t h e t i m e r Z c o u n t s o u r c e . T i m e r c o u n t s o u r c e s e t r e g i s t e r ( T C S S ) [ A d d r e s s 2 E1 T i m e r Z c o u n t s o u r c e s e l e c t i o n b i t s b b f XI N ) f XI N ) T i m e r Y u n d e r f l o w o t N o t a v a i l a b l e P r o c e s s 5 : W h e n t h e t r i g g e r b y I N T0 p i n i n p u t i s s e l e c t e d : S e t p o r t P d i r e c t i o n r e g i s t e r p u l l u p c o n t r o l r e g i s t e r a n d p o r t P P c o n t r o l r e g i s t e r Pull-up control register (PULL) [Address 1616] P 37/ I N T0 p u l l - u p c o n t r o l b i t P u l l u p O f f P u l l u p O n Port P1P3 control register (P1P3C) [Address 1716] P 37/ I N T0 i n p u t l e v e l s e l e c t i o n b i t C M O S l e v e l T T L l e v e l P o r t P 3 d i r e c t i o n r e g i s t e r ( P 3 D ) [ A d d r e s s 0 71 S e t P 37/ I N T0 p i n t o t h e i n p u t m o d e Note: When the timer Z waveform extension function is used, do not select the timer Y underflow for the timer Z count source. C o u n t v a l u e T i m e r Z p r i m a r y ( T Z P ) [ A d d r e s s 2 71

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.38 Setting method for programmable wait one-shot generation mode (3) b 7b 0 0111 b 7b 0 b 7b 0 b 7b 0 b 7b 0 b7 b0 b 7b 0 P r o c e s s 8 : S e t t h e s t a n d b y s t a t e t o a c c e p t t h e o n e - s h o t s t a r t t r i g g e r (N o t e) . Timer Y, Z mode register (TYZM) [Address 2016] T i m e r Z c o u n t s t a r t N o t e : W h e n t h e I N T0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t o f P U M i s s e t t o “ v a l i d ” , t i m e r Z c o u n t i n g i s s t a r t e d b y t h e i n p u t o f t r i g g e r t o I N p i n a f t e r t h i s s e t t i n g N o t e : P u l s e i s o u t p u t f r o m T ZO U T p i n . A f t e r o u t p u t , t h i s b i t i s i n i t i a l i z e d t o “ 0 ” . Note: When the INT0 pin one-shot trigger control bit is set to “valid”, the INT0 interrupt can be accepted after this setting. G When the INT0 pin one-shot trigger control bit of PUM is set to “valid”, the timer Z count is started by input of trigger to the INT0 pin. Process 9: In order not to execute the no requested interrupt processing, set “0” (no requested) to the timer Z interrupt request bit. Interrupt request register 2 (IREQ2) [Address 3D16] Process 10: When the interrupt is used, set “1” (interrupt enabled) to the corresponding interrupt enable bit. N o timer Z interrupt request issued Interrupt control register 1 (ICON1) [Address 3E16] INT0 interrupt enabled (N ote) O n e - s h o t s t a r t r e g i s t e r ( O N S ) [ A d d r e s s 2 A1 T i m e r Z o n e - s h o t s t a r t (N o t e) P r o c e s s 1 1 : S t a r t c o u n t i n g o f t i m e r Z . I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E ) [ A d d r e s s 3 A1 INT0 interrupt edge selection bit 0: Falling edge active 1: Rising edge active Interrupt request register 1 (IREQ1) [Address 3C16] N o I N T0 i n t e r r u p t r e q u e s t i s s u e d Interrupt control register 2 (ICON2) [Address 3F16] T i m e r Z i n t e r r u p t e n a b l e d G When the INT0 pin one-shot trigger control bit is set to “valid” and the INT0 interrupt is used, set the following;

Rev.2.00 Jun 21, 2004 (3) Application example of programmable wait one-shot generation mode Outline: The wait one-shot pulse synchronized with the PWM waveform output from the P01/TYOUT pin is generated from Timer Z by using the programmable waveform generation mode of Timer Y. Specifications:T YOUT pin is connected to the P37/INT0 pin. The wait one-shot pulse is output by the INT0 pin input as trigger. Operation clock: f(XIN) = 8 MHz, high-speed mode As for the usage of Timer Y, refer to the above mentioned programmable waveform generation mode. an example of control procedure. Fig. 2.5.39 Example of waveform generation and peripheral circuit Timer Z active Timer Z active Timer Z active

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z Fig. 2.5.40 Example of control procedure W a i t o n e - s h o t g e n e r a t i o n r o u t i n e 1 11 111 10 11 INT0 rising edge active Timer Z interrupt processing routine R T I R T S Timer Z primary (Address 2716) Prescaler Z (Address 2516) Set pull-up control register Set port P1P3 control register TYZM(Address 2016) Timer Z count start (Note 7) S e t t h e s t a n d b y s t a t e t o a c c e p t o n e s h o t s t a r t t r i g g e r INTEDGE(Address 3A16) Set interrupt edge selection register C h a n g e o f t i m e r Z T i m e r Z p r i m a r y w a v e f o r m g e n e r a t i o n n o t e x t e n d e d o t e T i m e r Z s e c o n d a r y w a v e f o r m g e n e r a t i o n n o t e x t e n d e d o t e I n i t i a l s t a t e T Z P H i n t e r v a l T Z S L i n t e r v a l a f t e r u n d e r f l o w S t o p a t H a f t e r u n d e r f l o w I N p i n o n e s h o t t r i g g e r v a l i d o t e I N p i n r i s i n g e d g e t r i g g e r o t e P U M ( A d d r e s s 2 41 TCSS(Address 2E16) Timer Z count source selected Set port P02 to the output mode. S e t “ 0 ” t o t h e t i m e r Z i n t e r r u p t e n a b l e b i t . T i m e r Z i n t e r r u p t d i s a b l e d Set value to timer Z (Notes 2, 4, 5, 6) S e t t i m e r c o u n t s o u r c e s e t r e g i s t e r (N o t e 3) T Y Z M ( A d d r e s s 2 01 S e t t i m e r Y , Z m o d e r e g i s t e r P r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n m o d e W r i t i n g t o o n l y l a t c h o t e T i m e r Z c o u n t s t o p S e t “ 1 ” t o t h e t i m e r Z i n t e r r u p t e n a b l e b i t . T i m e r Z i n t e r r u p t e n a b l e d S e t “ 0 ” t o t h e i m e r Z i n t e r r u p t r e q u e s t b i t . Set timer Y, Z waveform output control register Set port P37 to the input mode. Notes 1: When using this mode, be sure to select “write to latch only”. 2: The waveform extension function by the timer Z waveform extension control bits can be used only when “0016” is set to prescaler Z. When the value other than “00 16” is set to prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. 3: Stop timer Z to change the INT 0 pin one-shot trigger control bit and INT0 one-shot trigger active edge selection bit. 4: In the programmable wait one-shot generation mode, values of TZS, EXPZP, and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. 5: In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer Z underflow simultanesously. 6: Count values of the primary interval (during wait) and secondary interval (during one-shot output) can be checked by reading TZP (TZS is undefined at read). 7: In this state, timer count is not started. Timer Z secondary ( A d d r e s s 2 61

Rev.2.00 Jun 21, 2004

2.5.7 Notes on timer Y and timer Z

Notes on using each mode of Timer Y and Timer Z are described below. (1) Timer mode (timer Y and timer Z) ➀ In the timer mode, TYP and TYS is not used. (2) Programmable waveform generation mode (timer Y and timer Z) ➀ In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again. ➁ In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultaneously. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Y interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary and a secondary setting values, and primary write timing, it may be impossible.) ➂ The waveform extension function by the timer Y waveform extension control bits can be used only when “00 16” is set to Prescaler Y. When the value other than “0016” is set to Prescaler Y, be sure to set “0” to EXPYP and EXPYS. The waveform extension function by the timer Z waveform extension control bits can be used only when “00 16” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. ➃ When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch only”. ➄ When TYS is read out, the undefined value is read out. However, while timer Y counts the setting value of TYS, the count value during the secondary interval can be obtained by reading the timer Y primary. ➅ In order to use TY OUT pin, set “1” to bit 1 of the port P0 direction register (output mode). (3) Programmable one-shot generation mode (timer Z) ➀ In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again. ➁ In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow simultaneously.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.5 Timer Y and timer Z ➂ The waveform extension function by the timer Z waveform extension control bits can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. An example of a measurement is shown below. ex.) The underflow of timer is stored by polling etc. using timer Z interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT 0 pin, it may be impossible.) ➃ When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. ➄ In order to use TZOUT pin, set “1” to bit 2 of the port P0 direction register (output mode). ➅ Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit. (4) Programmable wait one-shot generation mode (timer Z) ➀ In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Z interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT 0 pin, it may be impossible.) ➁ In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultaneously. ➂ The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. ➃ When using this mode, be sure to set “1” to the timer Z write control bits to select “write to latch only”. ➄ When TZS is read out, the undefined value is read out. However, while Timer Z counts the setting value of TZS (during one-shot output), the count value during the secondary interval can be obtained by reading TZP. ➅ In order to use TZ OUT pin, set “1” to bit 2 of the port P0 direction register (output mode). ➆ Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit.

Rev.2.00 Jun 21, 2004 This paragraph explains the registers setting method and the notes relevant to the serial I/O.

2.6.1 Memory map

Fig. 2.6.1 Memory map of registers relevant to serial I/O

2.6.2 Relevant registers

Fig. 2.6.2 Structure of Transmit/Receive buffer register 001816 001916 001A16 001B16 001C 16 003C 16 Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Interrupt request register 1 (IREQ1) 003E16 Interrupt control register 1 (ICON1) Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Transmit/Receive buffer register (TB/RB) [Address : 1816] The transmission data is written to or the receive data is read out from this buffer register.

• At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read out. Note: The contents of transmit buffer register cannot be read out. The data cannot be written to the receive buffer register.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.6 Serial I/O1 Fig. 2.6.3 Structure of Serial I/O1 status register Fig. 2.6.4 Structure of Serial I/O1 control register Serial I/O1 status register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Serial I/O1 status register (SIO1STS) [Address : 1916] Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is “1”. Transmit buffer empty flag (TBE) Overrun error flag (OE) 0 : Buffer full 1 : Buffer empty Receive buffer full flag (RBF) Transmit shift register shift completion flag (TSC) Parity error flag (PE) Framing error flag (FE) Summing error flag (SE) 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error Serial I/O1 control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Serial I/O1 control register (SIO1CON) [Address : 1A16] 0 : f(XIN) 1 : f(XIN)/4 BRG count source selection bit (CSS) 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled Transmit interrupt source selection bit (TIC) Transmit enable bit (TE) Receive enable bit (RE) Serial I/O1 enable bit (SIOE) 0 : Interrupt when transmit buffer has emptied 1 : Interrupt when transmit shift operation is completed 0: Serial I/O1 disabled 1: Serial I/O1 enabled Serial I/O1 synchronous clock selection bit (SCS) When clock synchronous serial I/O is selected; 0: BRG output divided by 4 1: External clock input When UART is selected; 0: BRG output divided by 16 External clock input divided by 16 0SRDY1 output enable bit (SRDY) 0: P13 pin 1: SRDY1 output pin Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O

Rev.2.00 Jun 21, 2004 Fig. 2.6.5 Structure of UART control register Fig. 2.6.6 Structure of Baud rate generator b 7b 6b 5b 4b 3b 2b 1b 0 B Function A t r e s e t RW N a m e U A R T c o n t r o l r e g i s t e r ( U A R T C O N ) [ A d d r e s s : 1 B1 N o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . T h e s e a r e w r i t e d i s a b l e d b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e U A R T c o n t r o l r e g i s t e r C h a r a c t e r l e n g t h s e l e c t i o n b i t C H A S P a r i t y e n a b l e b i t P A R E S t o p b i t l e n g t h s e l e c t i o n b i t S T P S P a r i t y s e l e c t i o n b i t P A R S I n o u t p u t m o d e C M O S o u t p u t N c h a n n e l o p e n d r a i n o u t p u t 0 : 8 bits 1 : 7 bits 0 : Parity checking disabled 1 : Parity checking enabled 0 : 1 stop bit 1 : 2 stop bits 0 : Even parity 1 : Odd parity P 11/ T x D P - c h a n n e l o u t p u t d i s a b l e b i t P O F F Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Baud rate generator (BRG) [Address : 1C16] Set a count value of baud rate generator.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.6 Serial I/O1 Fig. 2.6.7 Structure of Interrupt request register 1 Fig. 2.6.8 Structure of Interrupt control register 1 Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 1 (IREQ1) [Address : 3C16] Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued CNTR 0 interrupt request bit CNTR 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued INT0 interrupt request bit INT1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Key-on wake up interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Timer X interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 1 (ICON1) [Address : 3E16] Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Timer X interrupt enable bit0 : Interrupt disabled 1 : Interrupt enabled

Rev.2.00 Jun 21, 2004

2.6.3 Serial I/O1 transfer data format

Figure 2.6.9 shows the serial I/O1 transfer data format. Fig. 2.6.9 Serial I/O1 transfer data format 1ST-8DATA-1SP S T L S B S e r i a l I / O 1 UART Clock synchronous serial I/O

1 S T - 7 D A T A - 1 S P

1 S T - 7 D A T A - 1 P A R - 1 S P

1 S T - 8 D A T A - 2 S P

1 S T - 8 D A T A - 1 P A R - 2 S P

1 S T - 7 D A T A - 1 P A R - 2 S P

S T : S t a r t b i t S P S t o p b i t P A R P a r i t y b i t

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.6 Serial I/O1

2.6.4 Application example of clock synchronous serial I/O1

For clock synchronous serial I/O1, the transmitter and the receiver use the same clock. Synchronizing with this clock, the transmit operation of the transmitter and the receive operation of the receiver are executed at the same time. If an internal clock is used as the operation clock, transfer is started by a write signal to the TB/RB. (1) Data transfer rate The synchronous clock frequency is calculated by the following formula; G When the internal clock is selected (when baud rate generator is used) Synchronous clock frequency [Hz] = Division ratio*1 : “1” or “4” is selected (set by bit 0 of serial I/O1 control register) BRG setting value*2 : 0 to 255 (0016 to FF16) is set G When the external clock is selected Synchronous clock frequency [Hz] = Clock input to SCLK1 pin f(XIN) Division ratio *1 ✕ (BRG setting value *2 + 1) ✕ 4

Rev.2.00 Jun 21, 2004 Fig. 2.6.10 Setting method for clock synchronous serial I/O1 (1) Interrupt control register 1 (ICON1) [Address 3E16] b 7b 0 S e r i a l I / O 1 r e c e i v e i n t e r r u p t d i s a b l e d S e r i a l I O t r a n s m i t i n t e r r u p t d i s a b l e d Baud rate generator (BRG) [Address 1C16] Set baud rate value b 7b 0 0 0 P r o c e s s 1 : S t o p a n d i n i t i a l i z e s e r i a l I / O . S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O 1 C O N ) [ A d d r e s s 1 A1 T r a n s m i t o p e r a t i o n s t o p a n d i n i t i a l i z e d R e c e i v e o p e r a t i o n s t o p a n d i n i t i a l i z e d BRG count source selected (set in internal clock selected) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selected 0: BRG output/4 (Note 1) 1: External clock input S RDY1 output enable selected 0: P13 pin operates as normal I/O pin 1: P13 pin operates as SRDY1 output pin (Note 2) Transmit interrupt source selected 0: When transmit buffer has emptied 1: When transmit shift operation is completed Transmit enable selected 0: Transmit disabled (at half-duplex communication receive) 1: Transmit enabled (at full-duplex communication) (Note 3) Receive enable selected 0: Receive disabled (at half-duplex communication transmit) 1: Receive enabled (at full-duplex communication) (Note 3) Clock synchronous serial I/O Serial I/O1 enabled (P1 0–P13 pins operate as serial I/O1 pins) S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O 1 C O N ) [ A d d r e s s 1 A1 P r o c e s s 3 : S e t s e r i a l I / O 1 c o n t r o l r e g i s t e r . b7 b 0 1 1 Notes 1: Setting of serial I/O1 synchronous selection bit is as follows: “0”: P12 pin is set to be an output pin of the synchronous clock. “1”: P12 pin is set to be an input pin of the synchronous clock. 2: When an external clock input is selected as the synchronous clock, and the receiver performs the SRDY1 output, set “1” to the transmit enable bit in addition to the receive enable bit and SRDY1 output enable bit. 3: When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set “1” to the transmit enable bit while the SCLK1 is “H” state. P r o c e s s 2 : D i s a b l e s e r i a l I / O 1 t r a n s m i t / r e c e i v e i n t e r r u p t . Process 4: When BRG output/4 is selected as synchronous clock, set value to baud rate generator. (2) Clock synchronous serial I/O setting method

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.6 Serial I/O1 Fig. 2.6.11 Setting method for clock synchronous serial I/O1 (2) P r o c e s s 7 : T r a n s m i t / R e c e i v e o f s e r i a l d a t a (N o t e s 1 , 2) . Transmit/Receive buffer register (TB/RB) [Address 1816] b b Set transmit data (in full-duplex commun ication) Set dummy data (in half-duplex communication) P r o c e s s 5 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t “ 0 ” ( n o r e q u e s t e d ) t o t h e s e r i a l I O t r a n s m i t r e c e i v e i n t e r r u p t r e q u e s t b i t I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 3 C 1 N o s e r i a l I / O 1 r e c e i v e i n t e r r u p t r e q u e s t i s s u e d N o s e r i a l I O t r a n s m i t i n t e r r u p t r e q u e s t i s s u e d S e r i a l I / O 1 r e c e i v e i n t e r r u p t e n a b l e d S e r i a l I O t r a n s m i t i n t e r r u p t e n a b l e d I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E1 P r o c e s s 6 : W h e n t h e i n t e r r u p t i s u s e d , s e t “ 1 ” ( i n t e r r u p t e n a b l e d ) t o t h e s e r i a l I / O t r a n s m i t / r e c e i v e i n t e r r u p t e n a b l e b i t Notes 1: When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set the transmit data while the SCLK is “H” state. 2: When inputting the SRDY1 signal, set used pins to to the input mode before transmitting data.

Rev.2.00 Jun 21, 2004 (3) Communication using clock synchronous serial I/O1 (transmit/receive) Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O1. SRDY1 signal is used for communication control. Specifications : •The serial I/O1 (clock synchronous serial I/O selected ) is used.

• Synchronous clock frequency : 125 kHz; f(XIN) = 4 MHz divided by 32
• The receiver outputs the SRDY1 signal at 2 ms intervals which the timer generates, and 2-byte data is transferred from the transmitter to the receiver. the control procedure of transmitter, and Figure 2.6.15 shows an example of control procedure of receiver. Fig. 2.6.12 Connection diagram Fig. 2.6.13 Timing chart SR D Y SC L K TXD D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 2ms T r a n s m i t t e r P37/INT0 SCLK1 TXD 1 7 5 4 0 G r o u p SRDY1 SCLK1 R XD 1 Receiver

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.6 Serial I/O1 Fig. 2.6.14 Control procedure of transmitter S I O 1 C O N ( A d d r e s s 1 A1 B R G c o u n t s o u r c e : f ( XI N ) S y n c h r o n o u s c l o c k B R G o u t p u t P p i n N o r m a l I O p i n T r a n s m i t i n t e r r u p t s o u r c e W h e n t r a n s m i t b u f f e r h a s e m p t i e d T r a n s m i t e n a b l e d R e c e i v e d i s a b l e d C l o c k s y n c h r o n o u s s e r i a l I O S e r i a l I O e n a b l e d S e t s e r i a l I / O 1 c o n t r o l r e g i s t e r 0 00 B R G ( A d d r e s s 1 C 1 Set baud rate generator I N T0 f a l l i n g e d g e i n p u t ? Y N I n i t i a l i z a t i o n RESET S E I C L D C L T 11 00 “0716” INTEDGE(Address 3A16) I N T0 f a l l i n g e d g e a c t i v e Set INT0 interrupt active edge T B / R B ( A d d r e s s 1 81 Write the first-byte transmission data to the transmit/receive buffer register Transmit buffer has emptied? (checked by b0 of SIO1STS (address 1916)) Y N TB/RB(Address 1816) Y N N Y Write the second-byte transmission data to the transmit/receive buffer register Transmit buffer has emptied? (checked by b0 of SIO1STS (address 1916)) Transmit shift has completed? (checked by b2 of SIO1STS (address 1916))

Rev.2.00 Jun 21, 2004 Fig. 2.6.15 Control procedure of receiver 1 11 2 ms elapsed ? (generated by timer) Y N R E S E T S E I C L D C L T 11 1 Set dummy data to the transmit/receive buffer Y N Y N SIO1CON(Address 1A16) Synchronous clock: External clock input S RDY1 output pin Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O enabled Set serial I/O1 control register I n i t i a l i z a t i o n TB/RB(Address 1816) Read the first-byte reception data from the transmit/receive buffer register R e c e i v e b u f f e r i s f u l l ? c h e c k e d b y b o f S I O S T S a d d r e s s T B / R B ( A d d r e s s 1 81 R e a d t h e s e c o n d - b y t e r e c e p t i o n d a t a f r o m t h e t r a n s m i t r e c e i v e b u f f e r r e g i s t e r R e c e i v e b u f f e r i s f u l l ? c h e c k e d b y b o f S I O S T S a d d r e s s TB/RB(Address 1816)

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.6 Serial I/O1 BRG count source f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) f(XIN) f(XIN) BRG set value 255 (FF16) 127 (7F16) 63 (3F16) 31 (1F16) 15 (0F16) 7 (0716) 3 (0316) 1 (0116) 3 (0316) 1 (0116) 0 (0016) Transfer bit rate (bps) At f(XIN) = 4.9152 MHz 300 600 1200 2400 4800 9600 19200 38400 76800 153600 307200 At f(X IN) = 8 MHz 488.28125 976.5625 1953.125 3906.25 7812.5 15625 31250 62500 125000 250000 500000

2.6.5 Application example of clock asynchronous serial I/O1

For clock asynchronous serial I/O1 (UART), the transfer formats used by a transmitter and receiver must be identical. In the 7540 Group, eight serial data transfer formats can be selected. (1) Data transfer rate The transfer bit rate is calculated by the following formula; G When the internal clock is selected (when baud rate generator is used) Transfer bit rate [bps] = Division ratio*1 : “1” or “4” is selected (set by bit 0 of serial I/O1 control register) BRG setting value*2 : 0 to 255 (0016 to FF16) is set G When the external clock is selected Transfer bit rate [bps] = Clock input to SCLK1 pin/16 Table 2.6.1 shows the setting example of baud rate generator and transfer bit rate values. Table 2.6.1 Setting example of baud rate generator (BRG) and transfer bit rate values f(XIN) Division ratio *1 ✕ (BRG setting value *2 + 1) ✕ 16

Rev.2.00 Jun 21, 2004 Fig. 2.6.16 Setting method for UART of serial I/O1 (1) (2) UART setting method b 7b 0 b 7b 0 1 0 b 7b 0 0 0 I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E1 S e r i a l I / O 1 r e c e i v e i n t e r r u p t d i s a b l e d S e r i a l I O t r a n s m i t i n t e r r u p t d i s a b l e d P r o c e s s 1 : S t o p a n d i n i t i a l i z e s e r i a l I / O . S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O 1 C O N ) [ A d d r e s s 1 A1 T r a n s m i t o p e r a t i o n s t o p a n d i n i t i a l i z a t i o n R e c e i v e o p e r a t i o n s t o p a n d i n i t i a l i z a t i o n BRG count source selected (set in internal clock selected) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selected (Note 1) 0: BRG output/16 1: External clock input/16 Transmit interrupt source selected 0: When transmit buffer has emptied 1: When transmit shift operation is completed Transmit enable selected 0: Transmit disabled (at half-duplex communication receive) 1: Transmit enabled (at full-duplex communication) (Note 2) Receive enable selected 0: Receive disabled (at half-duplex communication transmit) 1: Receive enabled (at full-duplex communication) (Note 2) Clock asynchronous serial I/O Serial I/O1 enabled (P1 0–P12 pins operate as serial I/O1 pins)(Note 3) Serial I/O1 control register (SIO1CON) [Address 1A16] P r o c e s s 3 : S e t s e r i a l I / O 1 c o n t r o l r e g i s t e r . N o t e 1 : S e t t i n g o f s e r i a l I / O 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t i s a s f o l l o w s ; P p i n c a n b e u s e d a s a n o r m a l I O p i n P p i n i s u s e d a s a n i n p u t p i n f o r a n e x t e r n a l c l o c k W h e n d a t a t r a n s m i s s i o n i s e x e c u t e d a t t h e s t a t e t h a t a n e x t e r n a l c l o c k i n p u t i s s e l e c t e d a s t h e s y n c h r o n o u s c l o c k s e t t o t h e t r a n s m i t e n a b l e b i t w h i l e t h e SC L K i s H s t a t e W h e n c l o c k a s y n c h r o n o u s U A R T s e r i a l I O i s s e l e c t e d P p i n c a n b e u s e d a s a n o r m a l I O p i n P r o c e s s 2 : D i s a b l e s e r i a l I / O 1 t r a n s m i t / r e c e i v e i n t e r r u p t .

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.6 Serial I/O1 Fig. 2.6.17 Setting method for UART of serial I/O1 (2) b b7 b0 P r o c e s s 5 : W h e n B R G o u t p u t / 1 6 i s s e l e c t e d a s s y n c h r o n o u s c l o c k , s e t v a l u e t o b a u d r a t e g e n e r a t o r . Baud rate generator (BRG) [Address 1C16] S e t b a u d r a t e v a l u e P r o c e s s 4 : S e t U A R T c o n t r o l r e g i s t e r . S e l e c t c h a r a c t e r l e n g t h b i t s b i t s S e l e c t p a r i t y e n a b l e P a r i t y d i s a b l e d P a r i t y e n a b l e d S e l e c t p a r i t y v a l i d o n l y w h e n p a r i t y i s e n a b l e d E v e n p a r i t y O d d p a r i t y S e l e c t s t o p b i t l e n g t h s t o p b i t s t o p b i t s S e l e c t P 11/ T x D P c h a n n e l o u t p u t d i s a b l e i n o u t p u t m o d e C M O S o u t p u t N c h a n n e l o p e n d r a i n o u t p u t U A R T c o n t r o l r e g i s t e r ( U A R T C O N ) [ A d d r e s s 1 B1 b 7b 0 P r o c e s s 8 : W h e n t r a n s m i t t i n g , s t a r t s e r i a l d a t a t r a n s m i s s i o n (N o t e) . T r a n s m i t / R e c e i v e b u f f e r r e g i s t e r ( T B / R B ) [ A d d r e s s 1 81 Set transmit data P r o c e s s 6 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t “ 0 ” ( n o r e q u e s t e d ) t o t h e s e r i a l I O t r a n s m i t r e c e i v e i n t e r r u p t r e q u e s t b i t Interrupt request register 1 (IREQ1) [Address 3C16] N o s e r i a l I / O 1 r e c e i v e i n t e r r u p t r e q u e s t i s s u e d N o s e r i a l I O t r a n s m i t i n t e r r u p t r e q u e s t i s s u e d S e r i a l I / O 1 r e c e i v e i n t e r r u p t e n a b l e d S e r i a l I O t r a n s m i t i n t e r r u p t e n a b l e d I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E1 P r o c e s s 7 : W h e n t h e i n t e r r u p t i s u s e d , s e t “ 1 ” ( i n t e r r u p t e n a b l e d ) t o t h e s e r i a l I / O 1 t r a n s m i t r e c e i v e i n t e r r u p t e n a b l e b i t Note: When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set the transmit data while the SCLK1 is “H” state.

Rev.2.00 Jun 21, 2004 (3) Communication using UART of serial I/O (transmit/receive) Outline : 2-byte data is transmitted and received, using UART. Port P00 is used for communication control. Specifications : •The Serial I/O1 (UART selected ) is used.

• Transfer bit rate : 9600 bps (f(XIN) = 4.9152 MHz divided by 512)
• Communication control using port P00 (output level of port P00 is controlled by software) 2-byte data is transferred from the transmitter to the receiver at 10 ms intervals which the timer generates. the control procedure of transmitter, and Figure 2.6.21 shows an example of control procedure of receiver. Fig. 2.6.18 Connection diagram Fig. 2.6.19 Timing chart P00 TXD 1 0 m s D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST S P ( 2 ) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST S P ( 2 ) D 0ST T r a n s m i t t e r P 00 T x D 7 5 4 0 G r o u p P00 R XD

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.6 Serial I/O1 Fig. 2.6.20 Control procedure of transmitter 10 ms elapsed ? (generated by timer) Y N R E S E T S E I C L D C L T 100 Y N UARTCON(Address 1B 16) Character length: 8 bits Parity disabled Stop bit length: 2 bits T XD: CMOS output S e t U A R T c o n t r o l r e g i s t e r 00 1 0 “ 0 71 Y N N S e t “ 0 ” t o t h e c o m m u n i c a t i o n c o n t r o l p o r t P 00. Y SIO1CON(Address 1A16) B R G c o u n t s o u r c e : f ( XI N ) / 4 S y n c h r o n o u s c l o c k B R G o u t p u t T r a n s m i t i n t e r r u p t s o u r c e W h e n t r a n s m i t b u f f e r h a s e m p t i e d T r a n s m i t e n a b l e d R e c e i v e d i s a b l e d U A R T S e r i a l I O e n a b l e d Set serial I/O1 control register B R G ( A d d r e s s 1 C 1 S e t b a u d r a t e g e n e r a t o r I n i t i a l i z a t i o n T B / R B ( A d d r e s s 1 81 Write the first-byte transmission data to the transmit/receive buffer register TB/RB(Address 1816) Write the second-byte transmission data to the transmit/receive buffer register T r a n s m i t b u f f e r h a s e m p t i e d ? c h e c k e d b y b o f S I O S T S a d d r e s s T r a n s m i t s h i f t h a s c o m p l e t e d ? c h e c k e d b y b o f S I O S T S a d d r e s s T r a n s m i t b u f f e r h a s e m p t i e d ? c h e c k e d b y b o f S I O S T S a d d r e s s S e t “ 1 ” t o t h e c o m m u n i c a t i o n c o n t r o l p o r t P 00. S e t t h e c o m m u n i c a t i o n c o n t r o l p o r t P 00 t o t h e o u t p u t m o d e

Rev.2.00 Jun 21, 2004 Fig. 2.6.21 Control procedure of receiver Y 101 1 U A R T C O N ( A d d r e s s 1 B1 6)01 0 B R G ( A d d r e s s 1 C 1 6)“ 0 71 N N Y N N Y Y N Y Error processing S E I C L D C L T SIO1CON(Address 1A16) BRG count source: f(XIN)/4 Synchronous clock: BRG output/16 Transmit disabled Receive enabled UART Serial I/O1 enabled S e t s e r i a l I / O 1 c o n t r o l r e g i s t e r I n i t i a l i z a t i o n C h a r a c t e r l e n g t h : 8 b i t s P a r i t y d i s a b l e d S t o p b i t l e n g t h b i t s S e t U A R T c o n t r o l r e g i s t e r B R G ( A d d r e s s 1 C 1 S e t b a u d r a t e g e n e r a t o r TB/RB(Address 1816) Read the first-byte transmission data from the transmit/receive buffer register R e c e i v e b u f f e r i s f u l l ? c h e c k e d b y b o f S I O S T S a d d r e s s C o m m u n i c a t i o n c o n t r o l p o r t P 00 = “ 0 ” ? S e t t h e c o m m u n i c a t i o n c o n t r o l p o r t P 00 t o t h e i n p u t m o d e TB/RB(Address 1816) R e a d t h e s e c o n d - b y t e t r a n s m i s s i o n d a t a f r o m t h e t r a n s m i t r e c e i v e b u f f e r r e g i s t e r E r r o r o c c u r s ? c h e c k e d b y b o f S I O S T S a d d r e s s E r r o r o c c u r s ? c h e c k e d b y b o f S I O S T S a d d r e s s R e c e i v e b u f f e r i s f u l l ? c h e c k e d b y b o f S I O S T S a d d r e s s

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.6 Serial I/O1

2.6.6 Notes on Serial I/O1

Notes on using serial I/O1 are described below. (1) Notes when selecting clock synchronous serial I/O ➀ When the clock synchronous serial I/O1 is used, serial I/O2 cannot be used. ➁ When the transmit operation is stopped, clear the serial I/O1 enable bit and the transmit enable bit to “0” (serial I/O1 and transmit disabled). G Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD 1, RxD1, SCLK1 , and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD 1 pin and an operation failure occurs. ➂ When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0” (serial I/O1 disabled). ➃ When the transmit/receive operation is stopped, clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) simultaneously. (any one of data transmission and reception cannot be stopped.) G Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit cannot be initialized even if the serial I/O1 enable bit is cleared to “0” (serial I/O1 disabled) (same as ➁ ). ➄ When signals are output from the S RDY1 pin on the reception side by using an external clock, set all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to “1”. ➅ When the SRDY1 signal input is used, set the using pin to the input mode before data is written to the transmit/receive buffer register. ➆ Setup of a serial I/O1 synchronous clock selection bit when a clock synchronous serial I/O is selected; “0” : P12 pin turns into an output pin of a synchronous clock. “1” : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY1 ) when a clock synchronous serial I/O1 is selected; “0” : P13 pin can be used as a normal I/O pin. “1” : P13 pin turns into a SRDY1 output pin.

Rev.2.00 Jun 21, 2004 (2) Notes when selecting UART ➀ When the clock asynchronous serial I/O1 (UART) is used, serial I/O2 can be used only when BRG output divided by 16 is selected as the synchronous clock. ➁ When the transmit operation is stopped, clear the transmit enable bit to “0” (transmit disabled). G Reason Same as (1) ➁ . ➂ When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled). ➃ When the transmit/receive operation is stopped, clear the transmit enable bit to “0” (transmit disabled) and receive enable bit to “0” (receive disabled). ➄ Setup of a serial I/O1 synchronous clock selection bit when a clock asynchronous (UART) serial I/O is selected; “0”: P12 pin can be used as a normal I/O pin. “1”: P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. (3) Notes common to clock synchronous serial I/O and UART ➂ When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set “1” to the transmit enable bit while the SCLK1 is “H” state. Also, write to the transmit buffer register while the SCLK1 is “H” state. ➃ When the transmit interrupt is used, set as the following sequence. ❶ Serial I/O1 transmit interrupt enable bit is set to “0” (disabled). ❷ Serial I/O1 transmit enable bit is set to “1”. ❸ Serial I/O1 transmit interrupt request bit is set to “0”. ❹ Serial I/O1 transmit interrupt enable bit is set to “1” (enabled). G Reason When the transmit enable bit is set to “1”, the transmit buffer empty flag and transmit shift completion flag are set to “1”. Accordingly, even if the timing when any of the above flags is set to “1” is selected for the transmit interrupt source, interrupt request occurs and the transmit interrupt request bit is set. ➄ Write to the baud rate generator (BRG) while the transmit/receive operation is stopped. Fig. 2.6.22 Sequence of setting serial I/O1 control register again ➀ Set the serial I/O control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0.” ➁ The transmit shift completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. Can be set with the LDM instruction at the same time Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1”

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.7 Serial I/O2 This paragraph explains the registers setting method and the notes relevant to the serial I/O.

2.7.1 Memory map

Fig. 2.7.1 Memory map of registers relevant to serial I/O2

2.7.2 Relevant registers

Fig. 2.7.2 Structure of Port P1 direction register 000316 003D 16 Port P1 direction register (P1D) Interrupt request register 2 (IREQ2) 003F16 Interrupt control register 2 (ICON2)

003016 Serial I/O2 control register (SIO2CON)

003116 Serial I/O2 register (SIO2)

Port P1 direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port P1 direction register 0 Port P1 direction register (P1D) [Address : 0316] 0 : Port P10 input mode 1 : Port P10 output mode 0 : Port P11 input mode 1 : Port P11 output mode 0 : Port P12 input mode 1 : Port P12 output mode 0 : Port P13 input mode 1 : Port P13 output mode 0 : Port P14 input mode 1 : Port P14 output mode Nothing is allocated for these bits. When these bits are read out, the values are undefined.

Rev.2.00 Jun 21, 2004 Fig. 2.7.3 Structure of Serial I/O2 control register Fig. 2.7.4 Structure of Serial I/O2 register b 7b 6b 5b 4b 3b 2b 1b 0 B Function A t r e s e t RW Name S e r i a l I / O 2 c o n t r o l r e g i s t e r ( S I O 2 C O N ) [ A d d r e s s : 3 01 N o t h i n g i s a l l o c a t e d f o r t h i s b i t . T h i s i s a w r i t e d i s a b l e d b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s S e r i a l I / O 2 c o n t r o l r e g i s t e r N o t e : W h e n u s i n g i t a s a SD A T A i n p u t , s e t t h e p o r t P 13 d i r e c t i o n r e g i s t e r b i t t o “ 0 ” . 0 : L S B f i r s t M S B f i r s t 0 0 0 : f(XIN)/8 0 0 1 : f(XIN)/16 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 1 0 : f(XIN)/128 1 1 1 : f(XIN)/256 I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s T r a n s f e r d i r e c t i o n s e l e c t i o n b i t b2 b1 b0 SD A T A 2 p i n s e l e c t i o n b i t o t 0 : I / O p o r t / SD A T A 2 i n p u t SD A T A o u t p u t SC L K 2 p i n s e l e c t i o n b i t 0 : External clock (SCLK2 is input) 1 : Internal clock (SCLK2 is output) Transmit / receive shift completion flag 0 : shift in progress 1 : shift completed Serial I/O2 register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Serial I/O2 register (SIO2) [Address : 3116] A shift register for serial transmission and reception.

• At transmitting : Set a transmission data.
• At receiving : A reception data is stored.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.7 Serial I/O2 Fig. 2.7.5 Structure of Interrupt request register 2 Fig. 2.7.6 Structure of Interrupt control register 2 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 2 (IREQ2) [Address : 3D16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer Y interrupt request bit Timer Z interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Timer 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued Timer A interrupt request bit Serial I/O2 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued AD converter interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 2 (ICON2) [Address : 3F16] Timer Y interrupt enable bit Timer Z interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Timer 1 interrupt enable bit Timer A interrupt enable bit Serial I/O2 interrupt enable bit AD conversion interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled ✕Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”.

Rev.2.00 Jun 21, 2004 Fig. 2.7.7 Setting method for serial I/O2

2.7.3 Application example of serial I/O2

(1) Serial I/O2 setting method b b7 b0 b 7b 0 P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D ) [ A d d r e s s 0 31 b P 12/ SC L K 2 p i n (N o t e 1) P 13/ SD A T A p i n o t e s I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 Serial I/O2 interrupt disabled Internal synchronous clock selected (set in internal clock selected) b2b1b0 0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 1 0: f(XIN)/128 1 1 1: f(XIN)/256 SDATA2 pin selected 0: I/O port/SDATA2 input (at receive) 1: SDATA2 output (at transmit) Transfer direction selected 0: LSB first 1: MSB first S CLK2 pin selected 0: External clock (SCLK2 is input) 1: Internal clock (SCLK2 is outpu) Serial I/O2 control register (SIO2CON) [Address 3016] Process 3: Set serial I/O2 control register. Process 1: Disable serial I/O2 transmit/receive interrupt. Process 4: In order not to execute the no requested interrupt processing, set “0” (no requested) to the serial I/O2 interrupt request bit. I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 3 D 1 N o s e r i a l I / O 2 i n t e r r u p t r e q u e s t i s s u e d N o t e s 1 : W h e n a n e x t e r n a l c l o c k i n p u t i s s e l e c t e d , s e t P 12/ SC L K 2 p i n t o t h e i n p u t m o d e . W h e n P 13/ SD A T A p i n i s u s e d a s t h e P p i n s e t t h i s b i t t o W h e n t h i s b i t i s s e t t o a t t r a n s m i t a n d t h e i n t e r n a l c l o c k i s s e l e c t e d f o r SC L K t h e SD A T A p i n i s i n a h i g h i m p e d a n c e s t a t e a f t e r t h e d a t a t r a n s f e r i s c o m p l e t e d Process 2: Set port P1 according to the usage condition.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.7 Serial I/O2 Fig. 2.7.8 Setting method for serial I/O2 b7 b0 Serial I/O2 register (SIO2) [Address 3116] S e t t r a n s m i t d a t a Serial I/O2 interrupt enabled Interrupt control register 2 (ICON2) [Address 3F16] Process 5: When the interrupt is used, set “1” (interrupt enabled) to the serial I/O2 interrupt. enable bit. Process 6: When transmitting, start serial data transmission.

Rev.2.00 Jun 21, 2004 (2) Communication using serial I/O2 (transmit/receive) Outline: 2-byte data is transmitted and received, using the serial I/O2. Port P00 is used for communication control and outputs the quasi-SRDY signal. Specifications: • The serial I/O2, clock synchronous serial I/O, is used.

• Synchronous clock frequency : 125 kHz; f(XIN) = 8 MHz divided by 64
• Transfer direction : LSB first
• The receiver outputs the quasi-S RDY signal at 2 ms intervals which the timer generates, and 2-byte data is transferred from the transmitter to the receiver. the control procedure of transmitter, and Figure 2.7.12 shows an example of control procedure of receiver. Fig. 2.7.9 Connection diagram Fig. 2.7.10 Timing chart T r a n s m i t t e r P37/INT0 SCLK SDATA 7 5 4 0 G r o u p P 00 SC L K SD A T A

R e c e i v e r Q u a s i -SR D Y SC L K SD A T A D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 2 ms

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.7 Serial I/O2 Fig. 2.7.11 Control procedure of transmission side 0 11 Y N R E S E T 10 1 I N T0 f a l l i n g e d g e a c t i v e S I O 2 ( A d d r e s s 3 11 Y N Y N S e t p o r t P 12 t o t h e o u t p u t m o d e . S e t “ 0 ” t o t h e s e r i a l I / O 2 i n t e r r u p t r e q u e s t b i t . SIO2CON(Address 3016) S y n c h r o n o u s c l o c k : f ( XI N ) / 6 4 SD A T A p i n SD A T A o u t p u t L S B f i r s t SC L K p i n I n t e r n a l c l o c k S e t s e r i a l I / O 2 c o n t r o l r e g i s t e r I N T0 f a l l i n g e d g e i n p u t ? I n i t i a l i z a t i o n SEI CLD CLT I N T E D G E ( A d d r e s s 3 A Set INT0 interrupt active edge W r i t e t h e f i r s t - b y t e t r a n s m i s s i o n d a t a t o t h e s e r i a l I O r e g i s t e r Transmit shift has completed? (checked by serial I/O2 interrupt request bit) S e t p o r t P 13 t o t h e o u t p u t m o d e . (N o t e) S I O 2 ( A d d r e s s 3 11 S e t “ 0 ” t o t h e s e r i a l I / O 2 i n t e r r u p t r e q u e s t b i t . W r i t e t h e s e c o n d - b y t e t r a n s m i s s i o n d a t a t o t h e s e r i a l I O r e g i s t e r Transmit shift has completed? (checked by serial I/O2 interrupt request bit) N o t e : W h e n d i r e c t i o n r e g i s t e r o f P 13/ SD A T A 2 p i n i s s e t t o t h e i n p u t m o d e a n d t h e i n t e r n a l c l o c k i s s e l e c t e d t h e SD A T A p i n i s i n a h i g h i m p e d a n c e s t a t e a f t e r t h e d a t a t r a n s f e r i s c o m p l e t e d

Rev.2.00 Jun 21, 2004 Fig. 2.7.12 Control procedure of reception side 0 11 Y N R E S E T 0 00 Y N SIO2(Address 3116) SIO2(Address 3116) S e t d u m m y d a t a t o s e r i a l I / O 2 r e g i s t e r o t e Y N W a i t f o r h a l f c y c l e o f c l o c k (N o t e 2) SIO2(Address 3116) R e a d r e c e i v e d a t a f r o m s e r i a l I / O 2 r e g i s t e r SIO2(Address 3116) Set quasi-SRDY signal port P00 to the output mode. SIO2CON(Address 3016) S y n c h r o n o u s c l o c k : f ( XI N ) / 6 4 SD A T A p i n SD A T A i n p u t L S B f i r s t SC L K p i n E x t e r n a l c l o c k S e t s e r i a l I / O 2 c o n t r o l r e g i s t e r 2 m s e l a p s e d ? g e n e r a t e d b y t i m e r I n i t i a l i z a t i o n SEI CLD CLT S e t d u m m y d a t a t o t h e s e r i a l I / O 2 r e g i s t e r o t e Receive has completed? (checked by b7 of SIO2CON (address 30 16)) S e t p o r t P 12 t o t h e i n p u t m o d e . N o t e s 1 : T h e t r a n s m i t / r e c e i v e s h i f t c o m p l e t i o n f l a g o f t h e s e r i a l I / O 2 c o n t r o l r e g i s t e r i s “ 1 ” a f t e r t r a n s m i t r e c e i v e s h i f t i s c o m p l e t e d I n o r d e r t o s e t t o t h i s f l a g s e t d a t a d u m m y d a t a a t r e c e i v e t o t h e s e r i a l I O r e g i s t e r b y p r o g r a m B i t t r a n s m i t r e c e i v e s h i f t c o m p l e t i o n f l a g o f t h e s e r i a l I O c o n t r o l r e g i s t e r i s s e t e a r l i e r t h a n t h e c o m p l e t i o n o f t h e a c t u a l s h i f t o p e r a t i o n f o r a h a l f c y c l e o f s h i f t c l o c k A c c o r d i n g l y w h e n t h e s h i f t c o m p l e t i o n i s c h e c k e d b y u s i n g t h i s b i t r e a d w r i t e t h e s e r i a l I O r e g i s t e r a f t e r a h a l f o r m o r e c y c l e o f c l o c k f r o m t h e s e t t i n g t o t h i s b i t i s c h e c k e d O u t p u t “ 1 ” f r o m q u a s i - SR D Y s i g n a l p o r t P 00. S e t p o r t P 13 t o t h e i n p u t m o d e . Receive has completed? (checked by b7 of SIO2CON (address 3016)) Wait for half cycle of clock (Note 2) Read receive data from serial I/O2 register Output “0” from quasi-SRDY signal port P00. Output “1” from quasi-SRDY signal port P00.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.7 Serial I/O2

2.7.4 Notes on serial I/O2

Notes on using serial I/O2 are described below. (1) Note on serial I/O1 Serial I/O2 can be used only when serial I/O1 is not used or serial I/O1 is used as UART and the BRG output divided by 16 is selected as the synchronous clock. (2) Note on SCLK2 pin When an external clock is selected, set “0” to bit 2 of the port P1 direction register (input mode). (3) Note on SDATA2 pin When P1 3/SRDY1 /SDATA2 pin is used as the SDATA input, set “0” to bit 3 of the port P1 direction register (input mode). When the internal clock is selected as the transfer and P13/SDATA2 pin is set to the input mode, the S DATA2 pin is in a high-impedance state after the data transfer is completed. (4) Notes on serial I/O2 transmit/receive shift completion flag ➀ The transmit/receive shift completion flag of the serial I/O2 control register is “1” after transmit/ receive shift is completed. In order to set “0” to this flag, set data (dummy data at receive) to the serial I/O2 register by program. ➁ Bit 7 (transmit/receive shift completion flag) of the serial I/O2 control register is set earlier than the completion of the actual shift operation for a half cycle of shift clock. Accordingly, when the shift completion is checked by using this bit, read/write the serial I/O2 register after a half or more cycle of clock from the setting “1” to this bit is checked.

Rev.2.00 Jun 21, 2004 This paragraph explains the registers setting method and the notes relevant to the A/D converter.

2.8.1 Memory map

Fig. 2.8.1 Memory map of registers relevant to A/D converter

2.8.2 Relevant registers

Fig. 2.8.2 Structure of A/D control register 0 0 3 41 0 0 3 51 0 0 3 61 0 0 3 D 1 A / D c o n t r o l r e g i s t e r ( A D C O N ) A / D c o n v e r s i o n r e g i s t e r ( l o w - o r d e r ) ( A D L ) A / D c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) ( A D H ) I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) 0 0 3 F1

6 I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 )

B F u n c t i o n A t r e s e t RW Name A/D control register (ADCON) [Address : 3416] Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is “0”. A / D c o n t r o l r e g i s t e r N o t e : T h e s e c a n b e u s e d o n l y f o r t h e 3 6 - p i n p a c k a g e v e r s i o n s . 0 0 0 : P 20/ A N 0 P 21/ A N 1 P 22/ A N 2 P 23/ A N 3 P 24/ A N 4 P 25/ A N 5 P 26/ A N 6 (N o t P 27/ A N 7 (N o t Analog input pin selection bitsb2 b1 b0 AD conversion completion bit0 : Conversion in progress 1 : Conversion completed Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. ✽: T h i s b i t c a n b e c l e a r e d t o “ 0 ” b y p r o g r a m , b u t c a n n o t b e s e t t o “ 1 ” .

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.8 A/D converter Fig. 2.8.3 Structure of A/D conversion register (low-order) Fig. 2.8.4 Structure of A/D conversion register (high-order) A/D conversion register (low-order) b 7b 6b 5b 4b 3b 2b 1b 0 B Function At resetRW A/D conversion register (low-order) (ADL) [Address : 3516] The read-only register in which the A/D conversion’s results are stored. < 8-bit read> b 7 b 8b 7b 6b 5b 4b 3 b2b 9 < 10-bit read> b 7 b6 b5 b4 b3 b2 b1 b0b7 A / D c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) b 7b 6b 5b 4b 3b 2b 1b 0 B F u n c t i o n At resetRW A / D c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) ( A D H ) [ A d d r e s s : 3 61 T h e r e a d - o n l y r e g i s t e r i n w h i c h t h e A / D c o n v e r s i o n ’ s r e s u l t s a r e s t o r e d < 10-bit read> b 8 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”.

Rev.2.00 Jun 21, 2004 Fig. 2.8.5 Structure of Interrupt request register 2 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 2 (IREQ2) [Address : 3D16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer Y interrupt request bit Timer Z interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Timer 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued Timer A interrupt request bit Serial I/O2 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued AD converter interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 2 (ICON2) [Address : 3F16] Timer Y interrupt enable bit Timer Z interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Timer 1 interrupt enable bit Timer A interrupt enable bit Serial I/O2 interrupt enable bit AD conversion interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled ✕Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Fig. 2.8.6 Structure of Interrupt control register 2

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.8 A/D converter

2.8.3 A/D converter application examples

(1) Setting of A/D converter Figure 2.8.7 shows the relevant registers setting. Fig. 2.8.7 Relevant registers setting P r o c e s s 2 : S e t A / D c o n t r o l r e g i s t e r . b 7b 0 A / D c o n t r o l r e g i s t e r ( A D C O N ) [ A d d r e s s 3 41 A n a l o g i n p u t p i n s s e l e c t e d b b b P 20/ A N 0 P 21/ A N 1 P 22/ A N 2 P 23/ A N 3 P 24/ A N 4 P 25/ A N 5 P 26/ A N 6 o t P 27/ A N 7 o t b 7b 0 b 7b 0 I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 6]0 Note: These can be used only for 36-pin version. b 7b 0 b 7b 0 A / D c o n v e r s i o n i n t e r r u p t d i s a b l e d P r o c e s s 1 : D i s a b l e A / D c o n v e r s i o n i n t e r r u p t . Process 3: In order not to execute the no requested interrupt processing, set “0” (no requested) to the A/D conversion interrupt request bit. I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 3 D 1 N o A/D conversion interrupt request issued A/D control register (ADCON) [Address 3416] Start A/D conversion A/D conversion interrupt enabled I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F1 P r o c e s s 4 : W h e n t h e i n t e r r u p t i s u s e d , s e t “ 1 ” ( i n t e r r u p t e n a b l e d ) t o t h e A D c o n v e r s i o n i n t e r r u p t e n a b l e b i t P r o c e s s 5 : S t a r t A / D c o n v e r s i o n .

Rev.2.00 Jun 21, 2004 Fig. 2.8.8 Connection diagram (2) Control procedure Outline : The analog input voltage input from a sensor is converted to digital values. Specifications : •The analog input voltage input from a sensor is converted to digital values.

• P20/AN0 pin is used as an analog input pin. Fig. 2.8.9 Control procedure P20/AN0 7 5 4 0 G r o u p S e n s o r A / D c o n v e r s i o n p r o c e s s i n g ADCON(Address 3416) A n a l o g i n p u t p i n s : P 20/ A N 0 S e t a n a l o g i n p u t p i n s 0 00 ADCON(Address 3416) S t a r t A / D c o n v e r s i o n 0 000 A/D conversion completed ? (Note 2) R e a d A D H ( a d d r e s s 3 61 6) (N o t e 3) R T S N o t e s 1 : I n t h i s c a s e , t h e A / D c o n v e r s i o n i n t e r r u p t i s u s e d . T h e c o m p l e t i o n o f t h e A D c o n v e r s i o n i s c h e c k e d b y t h e f o l l o w i n g T h e A D c o n v e r s i o n c o m p l e t i o n b i t o f t h e A D c o n t r o l r e g i s t e r i s T h e A D c o n v e r s i o n i n t e r r u p t r e q u e s t b i t o f t h e i n t e r r u p t r e q u e s t r e g i s t e r i s B r a n c h t o t h e A D c o n v e r s i o n i n t e r r u p t p r o c e s s i n g r o u t i n e i s e x e c u t e d I n t h i s t i m e t h e A D c o n v e r s i o n i n t e r r u p t i s e n a b l e d A t b i t r e a d t h e c o n v e r s i o n r e s u l t o f t h e h i g h o r d e r b i t s b b c a n b e r e a d A t b i t r e a d N o t u s e d A t b i t r e a d t h e c o n v e r s i o n r e s u l t o f t h e l o w o r d e r b i t s b t o b c a n b e r e a d A t b i t r e a d t h e c o n v e r s i o n r e s u l t o f b t o b c a n b e r e a d Y N Set “0” to the A/D conversion interrupt request bit. Set “1” to the A/D conversion interrupt enable bit. (A/D conversion interrupt enabled) (Note 1) Start A/D conversion S e t “ 0 ” t o t h e A / D c o n v e r s i o n i n t e r r u p t e n a b l e b i t . A D c o n v e r s i o n i n t e r r u p t d i s a b l e d R e a d A D L ( a d d r e s s 3 51 6) (N o t e 4)

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.8 A/D converter

2.8.4 Notes on A/D converter

Notes on A/D converter are described below. (1) Analog input pin Figure 2.8.10 shows the internal equivalent circuit of an analog input. In order to execute the A/D conversion correctly, to complete the charge to an internal capacitor within the specified time is required. The maximum output impedance of the analog input source required to complete the charge to a capacitor within the specified time is as follows; About 35 kΩ (at f(XIN) = 8 MHz) When the maximum output impedance exceeds the above value, equip an analog input pin with an external capacitor of 0.01µF to 1µF between an analog input pin and VSS . Further, be sure to verify the operation of application products on the user side. G Reason An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion/comparison precision to be worse. (2) Clock frequency during A/D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A/D conversion.

• f(X IN) is 500 kHz or more
• Do not execute the STP instruction (3) Note on A/D converter As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value. (2) When VREF voltage is lower than [3.0 V], the accuracy at the low temperature may become extremely low compared with that at room temperature When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. Fig. 2.8.10 Connection diagram ANi (i=0 to 7: 36-pin version i=0 to 5: 32-pin version) 12 pF(Typical) Notes 1: This is a parasitic diode. 2: Only the selected analog input pin is turned on. 1.5 pF(Typical) Chopper Amp. A/D control circuit Typical voltage generation circuit Switch tree, ladder resistor 1.5 kΩ (Typical) V SS VSS VCC VSS VREF R (Note 1) SW1 (Note 2) (Note 1)

Rev.2.00 Jun 21, 2004

2.9 Oscillation control

This paragraph explains the registers setting method and the notes relevant to the oscillation control.

2.9.1 Memory map

Fig. 2.9.1 Memory map of registers relevant to oscillation control

2.9.2 Relevant registers

Watchdog timer control register (WDTCON) CPU mode register (CPUM) Fig. 2.9.2 Structure of MISRG b7 b6 b5 b4 b3 b2 b1 b0 B Function A t r e s e t RW Name MISRG [Address : 3816] N o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . T h e s e a r e w r i t e d i s a b l e d b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e M I S R G O s c i l l a t i o n s t a b i l i z a t i o n t i m e s e t b i t a f t e r r e l e a s e o f t h e S T P i n s t r u c t i o n 00 : S e t “ 0 11 6” i n t i m e r 1 , a n d F i n p r e s c a l e r a u t o m a t i c a l l y N o t s e t a u t o m a t i c a l l y T h e s e a r e r e s e r v e d b i t s . D o n o t w r i t e t o t h e s e b i t s (Note) ✕0 : O s c i l l a t i o n s t o p n o t d e t e c t e d O s c i l l a t i o n s t o p d e t e c t e d C e r a m i c o r R C o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n a c t i v e b i t 0 : D e t e c t i o n f u n c t i o n i n a c t i v e D e t e c t i o n f u n c t i o n a c t i v e Oscillation stop detection status bit N o t e : “ 0 ” a t n o r m a l r e s e t a t r e s e t b y d e t e c t i n g t h e o s c i l l a t i o n s t o p

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.9 Reset Fig. 2.9.3 Structure of Watchdog timer control register Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Watchdog timer control register (WDTCON) [Address : 3916] Watchdog timer H (The high-order 6 bits are read-only bits.) STP instruction disable bit0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(XIN)/16 Fig. 2.9.4 Structure of CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW N a m e CPU mode register (CPUM) [Address : 3B16] C P U m o d e r e g i s t e r 00 0 : Single-chip mode 0 1 : Not available 1 0 : Not available 1 1 : Not available b1 b0 1 0 Processor mode bits (Note 1) 0 : Ceramic oscillation 1 : RC oscillation 0 : 0 p a g e p a g e Stack page selection bit O s c i l l a t i o n m o d e s e l e c t i o n b i t o t e C l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s 0 0 : φ = f(XIN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : Applied from on-chip oscillator 1 1 : φ = f(X IN) (double-speed mode) (Note 2) b7 b6 0 : C e r a m i c o r R C o s c i l l a t i o n e n a b l e d C e r a m i c o r R C o s c i l l a t i o n s t o p N o t e s 1 : T h e b i t c a n b e r e w r i t t e n o n l y o n c e a f t e r r e l e a s i n g r e s e t . A f t e r r e w r i t i n g i t i s d i s a b l e t o w r i t e a n y d a t a t o t h e b i t H o w e v e r b y r e s e t t h e b i t i s i n i t i a l i z e d a n d c a n b e r e w r i t t e n a g a i n I t i s n o t d i s a b l e t o w r i t e a n y d a t a t o t h e b i t f o r e m u l a t o r M C U M R S S T h e s e b i t s a r e u s e d o n l y w h e n a c e r a m i c o s c i l l a t i o n i s s e l e c t e d D o n o t u s e t h e s e w h e n a n R C o s c i l l a t i o n i s s e l e c t e d On-chip oscillator oscillation control bit 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop XIN oscillation control bit

Rev.2.00 Jun 21, 2004

2.9.3 Application example of on-chip oscillator

The on-chip oscillator is the oscillation circuit which is equipped with the 7540 Group. External circuits can be eliminated by using this oscillator as the operation clock or by using this oscillator with a ceramic or RC oscillation circuit. When this oscillator is used as the operation clock, all peripheral functions can be used. In this section, the setting method and application example are explained. Note: The 7540 Group starts operation by the on-chip oscillator. (1) Setting method Figure 2.9.5 shows the setting method when the on-chip oscillator is used as the operation clock. Fig. 2.9.5 Setting method when the on-chip oscillator is used as the operation clock P r o c e s s 1 : E n a b l e o n - c h i p o s c i l l a t o r o s c i l l a t i o n . b 7b 0 C P U m o d e r e g i s t e r ( C P U M ) [ A d d r e s s 3 B1 o n - c h i p o s c i l l a t i o r o s c i l l a t i o n e n a b l e d 000 P r o c e s s 2 : S e t t h e o p e r a t i o n c l o c k t o o n - c h i p o s c i l l a t o r . b 7b 0 A p p l i e d f r o m o n - c h i p o s c i l l a t o r 00001 P r o c e s s 3 : W h e n f ( XI N ) i s n o t u s e d , s t o p f ( XI N ) . b 7b 0 C e r a m i c o r R C o s c i l l a t i o n s t o p 00001 1 CPU mode register (CPUM) [Address 3B16] CPU mode register (CPUM) [Address 3B16] (2) Example of control procedure Outline: The frequency of the on-chip oscillator is measured, and an error by the power source voltage or temperature is confirmed. Specifications: • The f(XIN) = 4 MHz is divided by timer Z and 10 ms is detected. The on-chip oscillator is divided by timer Y.

• The count value of timer Y is read out in the timer Z interrupt processing routine which occurs every 10 ms, and an error from f(XIN) is confirmed. Figure 2.9.6 shows an example of control procedure.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.9 Reset Fig. 2.9.6 Control procedure “ F 91 “ 4 F1 I n i t i a l i z a t i o n R E S E T S E I C L D C L T S e t C P U m o d e r e g i s t e r C P U M ( A d d r e s s 3 B1 6)10 0 S i n g l e - c h i p m o d e O n c h i p o s c i l l a t o r o s c i l l a t i o n e n a b l e d f XI N ) o s c i l l a t i o n c e r a m i c R C e n a b l e d C e r a m i c o s c i l l a t i o n A p p l i e d f r o m o n c h i p o s c i l l a t o r 00 00 00000 0 0 : φ= f ( XI N ) / 2 ( H i g h - s p e e d m o d e ) f XI N ) M i d d l e s p e e d m o d e A p p l i e d f r o m o n c h i p o s c i l l a t o r o t e f XI N ) D o u b l e s p e e d m o d e 00001 “ F F1 “FF16” 100 10 P r o c e s s i n g 00000 C L I R e a d p r e s c a l e r Y a n d t i m e r Y a n d c o m p a r e t h e i r c o m p l e m e n t w i t h t h e s e t t i n g v a l u e s o f p r e s c a l e r Z a n d t i m e r Z T i m e r Z i n t e r r u p t p r o c e s s i n g r o u t i n e P r o c e s s i n g RTI S e t C P U m o d e r e g i s t e r C P U M ( A d d r e s s 3 B1 T Y Z M ( A d d r e s s 2 01 T C S S ( A d d r e s s 2 E1 T i m e r Y c o u n t s o u r c e : O n c h i p o s c i l l a t o r s e l e c t e d T i m e r Z f XI N ) s e l e c t e d Timer Y: Timer mode selected Timer Y count stop Timer Z: Timer mode selected Timer Z count stop Set timer Y, Z mode register S e t “ 0 ” t o t h e t i m e r Y i n t e r r u p t e n a b l e b i t . T i m e r Y i n t e r r u p t d i s a b l e d S e t t o t h e t i m e r Z i n t e r r u p t e n a b l e b i t T i m e r Z i n t e r r u p t d i s a b l e d Prescaler Y (Address 2116) S e t v a l u e t o p r e s c a l e r Y , t i m e r Y Timer Y (Address 2316) S e t t i m e r c o u n t s o u r c e s e t r e g i s t e r Set value to prescaler Z, timer Z (Note 3) Prescaler Z (Address 2516) T i m e r Z p r i m a r y ( A d d r e s s 2 71 S e t “ 1 ” t o t h e t i m e r Z i n t e r r u p t e n a b l e b i t . T i m e r Z i n t e r r u p t e n a b l e d Set “0” to the timer Y interrupt request bit. Set “0” to the timer Z interrupt request bit. T Y Z M ( A d d r e s s 2 01 Timer Y count start Timer Z count start Set timer Y, Z mode register T i m e r Z d i v i s i o n r a t i o Timer Z primary Notes 1: For the concrete time, ask the oscillator manufacture. 2: In this example, this setting cannot be selected. 3: 10 ms = 1/4 MHz ✕ 2 ✕ (F916 + 1) ✕ (4F16 + 1) Prescaler Z W a i t u n t i l f ( XI N ) o s c i l l a t i o n i s s t a b i l i z e d (N o t e 1)

Rev.2.00 Jun 21, 2004

2.9.4 Oscillation stop detection circuit

The oscillation stop detection circuit can be used to detect the stop by some failure or disconnection of an external ceramic oscillation circuit. In this section, the setting method and application example. (1) Operation description When the stop of an external oscillation circuit is detected by the oscillation stop detection circuit, the oscillation stop detection status bit of MISRG is set to “1” and the internal reset occurs. The 7540 Group starts operation by the on-chip oscillator after system is released from reset. Accordingly, error of the external oscillation circuit can be detected by checking the oscillation stop detection status bit after system starts operation. Notes 1: When the stop mode is used, set the oscillation stop detection function to “invalid”. 2: When f(X IN) oscillation is stopped, set the oscillation stop detection function to “invalid”.

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.9 Reset (2) Setting method Figure 2.9.7 shows the initial setting method oscillation stop detection circuit. Figure 2.9.8 shows the setting method for the oscillation stop detection circuit in the main processing. Fig. 2.9.7 Initial setting method for the oscillation stop detection circuit Process 1: Check that reset by oscillation stop detection is executed by referring the oscillation stop detection status bit. Process 2: Select oscillation mode. b7 b0 M I S R G ( M I S R G ) [ A d d r e s s 3 81 O s c i l l a t i o n s t o p d e t e c t i o n s t a t u s b i t O s c i l l a t i o n s t o p n o t d e t e c t e d O s c i l l a t i o n s t o p d e t e c t e d * E x e c u t e t h e f o l l o w i n g s e t a t t h e b e g i n n i n g o f p r o g r a m a f t e r s y s t e m i s r e l e a s e d f r o m r e s e t .

• Oscillation stop is detected Some error occus in the oscillation circuit. Do not switch the operation clock and execute the processing when some error occurs.
• Oscillation stop is not detected Execute the Process 2. b C P U m o d e r e g i s t e r ( C P U M ) [ A d d r e s s 3 B1 O s c i l l a t i o n m o d e s e l e c t i o n b i t (N o t e) C e r a m i c o s c i l l a t i o n R C o s c i l l a t i o n Process 3: Wait oscillation stabilizing (Note). N o t e : T h i s p r o c e s s c a n b e e l i m i n a t e d w h e n t h e R C o s c i l l a t i o n i s s e l e c t e d . F o r t h e o s c i l l a t i o n s t a b i l i z i n g t i m e a s k t h e o s c i l l a t o r m a n u f a c t u r e Process 4: Set the ceramic or RC oscillation stop detection function active bit. b7 b D e t e c t i o n f u n c t i o n a c t i v e (N o t e)

001 M I S R G ( M I S R G ) [ A d d r e s s 3 81

N o t e : T h e b i t c a n b e r e w r i t t e n o n l y o n c e a f t e r r e l e a s i n g r e s e t . A f t e r r e w r i t i n g i t i s d i s a b l e t o w r i t e a n y d a t a t o t h e b i t H o w e v e r b y r e s e t t h e b i t i s i n i t i a l i z e d a n d c a n b e r e w r i t t e n a g a i n I t i s n o t d i s a b l e t o w r i t e a n y d a t a t o t h e b i t f o r e m u l a t o r M C U M R S S 000 000001 000 N o t e : W h e n s o m e e r r o r o c c u r s i n t h e o s c i l l a t i o n c i r c u i t , s y s t e m i s r e l e a s e d f r o m r e s e t a f t e r s e t t i n g o f P r o c e s s i s e x e c u t e d Process 5: Select clock division ratio. b7 b C P U m o d e r e g i s t e r ( C P U M ) [ A d d r e s s 3 B1 Clock division ratio selection bits b7b6 0 0: f(φ) = f(XIN)/2 (high-speed mode) 0 1: f(φ)= f(XIN)/8 (middle-speed mode) 1 0: Applied from on-chip oscillator 1 1: f(φ)=f(X IN) (double-speed mode) (Note) Note: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected.

Rev.2.00 Jun 21, 2004 Fig. 2.9.8 Setting method for the oscillation stop detection circuit in main processing Process: Start on-chip oscillation when it is stopped. b 7b 0 C P U m o d e r e g i s t e r ( C P U M ) [ A d d r e s s 3 B1 O n - c h i p o s c i l l a t i o r o s c i l l a t i o n e n a b l e d P r o c e s s 2 : S e t c e r a m i c o r R C o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n a c t i v e b i t . b 7b 0 D etection function active (N ote) 6]000 N o t e : W h e n s o m e e r r o r o c c u r s i n t h e o s c i l l a t i o n c i r c u i t , s y s t e m i s r e l e a s e d f r o m r e s e t a f t e r s e t t i n g o f P r o c e s s i s e x e c u t e d

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.9 Reset

2.9.5 State transition

In the 7540 Group, the operation clock is selected from the following 4 types.

• f(XIN)/2 (high-speed mode)
• f(XIN)/8 (middle-speed mode)
• On-chip oscillator
• f(X IN) (double-speed mode) (Note 1) Note 1: f(XIN) can be used only at the ceramic oscillation. Do not use f(XIN) at RC oscillation. Also, in the 7540 Group, the function to stop CPU operation by software and to keep CPU wait in the following 2-type low power dissipation. G Stop mode with the STP instruction (Notes 2, 3, 4, 5, 6, 7) G Wait mode with the WIT instruction (Note 8) Notes 2: When the stop mode is used, set the oscillation stop detection function to “invalid”. 3: When the stop mode is used, set “0” (STP instruction enabled) the STP instruction disable bit of the watchdog timer control register. 4: Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/ “not set automaticallzy” by the oscillation stabilizing time set bit after release of the STP instruction of MISRG. When “0” is set to this bit, “0116” is set to timer 1 and “FF16” is set to prescaler 1 automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. 5: The STP instruction cannot be used during CPU is operating by the on-chip oscillator. 6: When the stop mode is used, stop the on-chip oscillator oscillation. 7: Do not execute the STP instruction during the A/D conversion. 8: When the wait mode is used, stop the clock except the operation clock source. Figure 2.9.9 shows the state transition. Fig. 2.9.9 State transition S t o p m o d eW a i t m o d e W I T i n s t r u c t i o n O s c i l l a t i o n s t o p d e t e c t i o n c i r c u i t v a l i d CPUM 4← 12 M I S R G 1← 12 I n t e r r u p t I n t e r r u p t S T P i n s t r u c t i o n WIT instruction I n t e r r u p t M I S R G 1← 02 C P U M 3← 12 C P U M 3← 02 C P U M 7 6← 1 C P U M 7 6← 0 N o t e CPUM 4← 02 M I S R G 1← 12 MISRG 1← 02 R e s e t r e l e a s e d S t a t e 1 O p e r a t i o n c l o c k s o u r c e f (XI N ) N o t e f (XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r s t o p S t a t e 2 O p e r a t i o n c l o c k s o u r c e f (XI N ) N o t e f (XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r e n a b l e d State 3 Operation clock source: On-chip oscillator (Note 3) f(X IN) oscillation enabled On-chip oscillator enalbed S t a t e 4 O p e r a t i o n c l o c k s o u r c e O n c h i p o s c i l l a t o r N o t e f (XI N ) o s c i l l a t i o n s t o p O n c h i p o s c i l l a t o r e n a l b e d N o t e s o n s w i t c h o f c l o c k I n o p e r a t i o n c l o c k s o u r c e f (XI N ) t h e f o l l o w i n g c a n b e s e l e c t e d f o r t h e C P U c l o c k d i v i s i o n r a t i o G f XI N ) h i g h s p e e d m o d e G f XI N ) m i d d l e s p e e d m o d e G f XI N ) d o u b l e s p e e d m o d e o n l y a t a c e r a m i c o s c i l l a t i o n E x e c u t e t h e s t a t e t r a n s i t i o n s t a t e t o s t a t e o r s t a t e t o s t a t e a f t e r s t a b i l i z i n g XI N o s c i l l a t i o n I n o p e r a t i o n c l o c k s o u r c e o n c h i p o s c i l l a t o r t h e m i d d l e s p e e d m o d e i s s e l e c t e d f o r t h e C P U c l o c k d i v i s i o n r a t i o W h e n t h e s t a t e t r a n s i t i o n s t a t e s t a t e s t a t e i s p e r f o r m e d e x e c u t e t h e N O P i n s t r u c t i o n a s s h o w n b e l o w a c c o r d i n g t o t h e d i v i s i o n r a t i o o f C P U c l o c k C P U M S t a t e s t a t e N O P i n s t r u c t i o n C P U M S t a t e s t a t e D o u b l e s p e e d m o d e a t o n c h i p o s c i l l a t o r N O P H i g h s p e e d m o d e a t o n c h i p o s c i l l a t o r N O P M i d d l e s p e e d m o d e a t o n c h i p o s c i l l a t o r N O P R e s e t s t a t e C P U M 7 6← 1 C P U M 7 6← 0 N o t e S t a t e 2 ’ O p e r a t i o n c l o c k s o u r c e f (XI N ) N o t e f (XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r e n a b l e d S t a t e 3 ’ O p e r a t i o n c l o c k s o u r c e O n c h i p o s c i l l a t o r N o t e f XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r e n a l b e d

Rev.2.00 Jun 21, 2004 Fig. 2.9.10 Example of mode transition (1) Example of control procedure Outline: The on-chip oscillator is used, and the intermittent operation for the low-power dissipation can be realized. Specifications: A mode is selected from the following modes 1 to 4 according to the usage condition. The return from mode 1 is executed by the timer A interrupt request which occurs every 0.5 s. Mode 1: Wait mode by the on-chip oscillator oscillation Operation clock source: On-chip oscillator CPU stop, ceramic oscillation stop, on-chip oscillator oscillation Mode 2: Middle-speed mode by the on-chip oscillator oscillation Operation clock source: On-chip oscillator CPU operation, ceramic oscillation stop, on-chip oscillator oscillation Mode 3: Middle-speed mode by the ceramic oscillation Operation clock source: Ceramic oscillation CPU operation, ceramic oscillation, on-chip oscillator oscillation Mode 4: Double-speed mode by the ceramic oscillation Operation clock source: Ceramic oscillation CPU operation, ceramic oscillation, on-chip oscillator oscillation Figure 2.9.10 shows an example of mode transition and Figure 2.9.11 shows an example of control procedure. P o w e r d i s s i p a t i o n Time M o d e 1 Mode 2 Mode 1 M o d e 2 Mode 1 Mode 2 Mode 3 M o d e 1 M o d e 2 C P U o p e r a t i o n i s s t a r t e d b y i n t e r r u p t o f t i m e r u n d e r f l o w Ceramic oscillation start Middle-speed mode (1/8) Mode 4 Ceramic oscillation Double-speed mode (1/1) W a i t m o d e b y o n c h i p o s c i l l a t i o n C P U s t o p T I m e r o p e r a t i n g

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.9 Reset Fig. 2.9.11 Control procedure N o t e s 1 : A t VC C = 5 V , t h e t i m e r A c o u n t s o u r c e w h e n a n o n - c h i p o s c i l l a t o r i s s e l e c t e d a s t h e o p e r a t i o n c l o c k i s a s f o l l o w s A b o u t M H z a b o u t k H z W h e n s e t t i n g t h e v a l u e t o t i m e r s e t i n o r d e r o f l o w o r d e r b y t e a n d h i g h o r d e r b y t e f o l l o w i n g s k H z F F o r t h e c o n c r e t e t i m e a s k t h e o s c i l l a t o r m a n u f a c t u r e M o d e s 3 , 4 ( c o m m o n ) NS w i t c h t o c e r a m i c o s c i l l a t i o n i s r e q u i r e d R E S E T S E I C L D C L T 10 000 10 CLI WIT instruction executed W a i t m o d e P r o c e s s i n g T i m e r A i n t e r r u p t p r o c e s s i n g r o u t i n e Processing Processing 10 000 00 00 010 00 Processing 10 010 00 000 T A M ( A d d r e s s 1 D 1 Count stop Set timer A mode register 001 RTI T A M ( A d d r e s s 1 D 1 T i m e r m o d e s e l e c t e d C o u n t s t o p S e t t i m e r A m o d e r e g i s t e r 001 “ 2 31 “ F 41 6” T i m e r A ( h i g h - o r d e r ) [ A d d r e s s 1 F1 Set values to timer A (Notes 2, 3) Set “0” to the timer A interrupt request bit T i m e r A ( l o w - o r d e r ) [ A d d r e s s 1 E1 M o d e s 3 , 4 O p e r a t i o n m o d e b y c e r a m i c o s c i l l a t i o n N Y Switch to double-speed mode is required? RTS 1 00 O n - c h i p o s c i l l a t o r o s c i l l a t i o n e n a b l e d XIN oscillation (ceramic) stop Applied from on-chip oscillator 00 10 Operation mode by ceramic oscillation M o d e 2 M o d e 1 M o d e 2 Y M o d e 2 M o d e 3 M o d e 4 I n i t i a l i z a t i o n S e t C P U m o d e r e g i s t e r C P U M ( A d d r e s s 3 B1 S i n g l e - c h i p m o d e O n c h i p o s c i l l a t o r o s c i l l a t i o n e n a b l e d f XI N ) o s c i l l a t i o n c e r a m i c s t o p C e r a m i c o s c i l l a t i o n A p p l i e d f r o m o n c h i p o s c i l l a t o r o t e Set CPU mode register CPUM(Address 3B16) S e t “ 0 ” t o t h e t i m e r A i n t e r r u p t e n a b l e b i t . T i m e r A i n t e r r u p t d i s a b l e d Timer A division ratio (fixed) Timer A setting value W a i t u n t i l f ( XI N ) o s c i l l a t i o n i s s t a b i l i z e d (N o t e 4) Set CPU mode register CPUM(Address 3B16) D ouble-speed mode Set CPU mode register CPUM(Address 3B16) S e t C P U m o d e r e g i s t e r CPUM(Address 3B16) S e t “ 0 ” t o t h e t i m e r A i n t e r r u p t e n a b l e b i t . T i m e r A i n t e r r u p t d i s a b l e d S e t t o o t h e r i n t e r r u p t e n a b l e b i t s O t h e r i n t e r r u p s d i s a b l e d TAM(Address 1D16) Count start Set timer A mode register f(XIN) oscillation (ceramic) enabled Middle-speed mode

Rev.2.00 Jun 21, 2004

2.9.6 Notes on oscillation stop detection circuit

Notes on using oscillation stop detection circuit are described below. (1) Note on on-chip oscillator ➀ The 7540 Group starts operation by the on-chip oscillator. ➁ On-chip oscillator operation The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Notes on oscillation circuit stop detection circuit ➀ When the stop mode is used, set the oscillation stop detection function to “invalid”. ➁ When f(XIN) oscillation is stopped, set the oscillation stop detection function to “invalid”. ➂ The oscillation stop detection circuit is not included in the emulator MCU “M37540RSS”. (3) Notes on stop mode ➀ When the stop mode is used, set the oscillation stop detection function to “invalid”. ➁ When the stop mode is used, set “0” (STP instruction enabled) to the STP instruction disable bit of the watchdog timer control register. ➂ Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/ “not set automatically” by the oscillation stabilizing time set bit after release of the STP instruction of MISRG. When “0” is set to this bit, “0116” is set to timer 1 and “FF16” is set to prescaler 1 automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. ➃ The STP instruction cannot be used during CPU is operating by the on-chip oscillator. ➄ When the stop mode is used, stop the on-chip oscillator oscillation. ➅ Do not execute the STP instruction during the A/D conversion. (4) Note on wait mode ➀ When the wait mode is used, stop the clock except the operation clock source. (5) Notes on state transition ➀ When the operation clock source is f(XIN), the CPU clock division ratio can be selected from the following;

• f(XIN)/2 (high-speed mode)
• f(XIN)/8 (middle-speed mode)
• f(XIN) (double-speed mode) The double-speed mode can be used only at ceramic oscillation. Do not use the mode at RC oscillation. ➁ Stabilize the f(X IN) oscillation to change the operation clock source from the on-chip oscillator to f(XIN).

Rev.2.00 Jun 21, 2004 APPLICATION 7540 Group 2.9 Reset ➂ When the on-chip oscillation is used as the operation clock, the CPU clock division ratio is the middle-speed mode. ➃ When the state transition state 2→ state 3→ state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock.

• CPUM 76→ 102 (State 2→ state 3)
• NOP instruction
• CPUM 4→ 12 (State 3→ state 4) Double-speed mode at on-chip oscillator: NOP✕ 3 High-speed mode at on-chip oscillator: NOP✕ 1 Middle-speed mode at on-chip oscillator: NOP✕ 0

3.1 Electrical characteristics

3.2 Typical characteristics

3.3 Notes on use

3.4 Countermeasures against

3.5 List of registers

3.6 Package outline

3.7 List of instruction code

3.8 Machine instructions

3.9 SFR memory map

3.10 Pin configurations

3.11 Differences between 7540

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics –0.3 to 6.5 (Note 1) –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 –0.3 to 13 –0.3 to VCC + 0.3 300 (Note 3) –20 to 85 –40 to 125 Power source voltage Input voltage 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7, VREF Input voltage RESET, XIN Input voltage CNVSS (Note 2) Output voltage 0–P0 7, P10–P1 4, P20–P27, P30–P3 7, XOUT Power dissipation Operating temperature Storage temperature V V V V V mW V CC VI VI VI VO Pd Topr Tstg ConditionsSymbol Ratings UnitParameter All voltages are based on VSS . Output transistors are cut off. Ta = 25°C Notes 1: This is the rating value for the Mask ROM version. The rating value for the One Time PROM version is –0.3 to 7.0 V. 2:It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version. 3: 200 mW for the 32P6U package product. 3.1.1 7540 Group (General purpose) Applied to: M37540M2-XXXFP/SP/GP, M37540M4-XXXFP/SP/GP, M37540E2FP/SP/GP, M37540E8FP/SP/GP (1) Absolute Maximum Ratings (General purpose) Table 3.1.1 Absolute maximum ratings

Rev.2.00 Jun 21, 2004 (2) Recommended Operating Conditions (General purpose) Table 3.1.2 Recommended operating conditions (1) (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 V CC VCC 4.0 2.4 2.2 4.5 4.0 2.4 2.2 4.0 2.4 2.2 2.0 0.8V CC 2.0 0.8VCC Min. Typ. Max. Symbol Parameter Unit Power source voltage (ceramic)f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) f(XIN) = 6 MHz (Double-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) f(XIN) = 1 MHz (Double-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) f(XIN) = 1 MHz (High-, Middle-speed mode) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Limits VCC V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA Power source voltage Analog reference voltage “H” input voltage 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “H” input voltage (TTL input level selected) 0, P12, P13, P36, P37 (Note 1) “H” input voltage RESET, X IN “L” input voltage 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” input voltage (TTL input level selected) 0, P12, P13, P36, P37 (Note 1) “L” input voltage RESET, CNV SS “L” input voltage X IN “H” total peak output current (Note 2) 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” total peak output current (Note 2) 0–P0 7, P10–P1 4, P20–P2 7, P37 “L” total peak output current (Note 2) 0–P3 6 “H” total average output current (Note 2) 0–P07, P10–P14, P20–P27, P30–P37 “L” total average output current (Note 2) 0–P07, P10–P14, P20–P27, P37 “L” total average output current (Note 2) 0–P3 6 Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. VCC VCC 0.3VCC 0.8 0.2VCC 0.16VCC –80 –40 V SS VREF VIH VIH VIH VIL VIL VIL VIL ∑ IOH(peak) ∑ IOL(peak) ∑ IOL(peak) ∑ IOH(avg) ∑ IOL(avg) ∑ IOL(avg) Power source voltage (RC)

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.3 Recommended operating conditions (2) (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) “H” peak output current (Note 1) P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” peak output current (Note 1) P00–P0 7, P10–P1 4, P20–P2 7, P37 “L” peak output current (Note 1) P30–P3 6 “H” average output current (Note 2) P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” average output current (Note 2) P00–P0 7, P10–P1 4, P20–P2 7, P37 “L” average output current (Note 2) P30–P3 6 Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) V CC = 4.0 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.4 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.2 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) V CC = 4.0 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.4 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.2 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) V CC = 4.0 to 5.5 V at RC oscillation High-, Middle-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.4 to 5.5 V at RC oscillation High-, Middle-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.2 to 5.5 V at RC oscillation High-, Middle-speed mode Symbol Parameter Limits Max.Typ.Min. –10 Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Unit

Rev.2.00 Jun 21, 2004 (3) Electrical Characteristics (General purpose) Table 3.1.4 Electrical characteristics (1) V CC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits Unit IOH = –5 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 2.2 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.2 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.2 to 5.5 V VI = VCC (Pin floating. Pull up transistors “off”) VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors “off”) VI = VSS VI = VSS VI = VSS (Pull up transistors “on”) When clock stopped V CC = 5.0 V, Ta = 25 °C VCC = 5.0 V, Ta = 25 °C Test conditions VCC –1.5 VCC –1.0 2.0 1000 62.5 “H” output voltage P00–P0 7, P10–P1 4, P20–P27, P30–P3 7 (Note 1) “L” output voltage P00–P0 7, P10–P1 4, P20–P2 7, P37 “L” output voltage P30–P3 6 Hysteresis CNTR 0, CNTR1, INT0, INT1(Note 2) P00–P0 7 (Note 3) Hysteresis R XD, SCLK1 , SCLK2 , SDATA2 (Note 2) Hysteresis RESET “H” input current P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “H” input current RESET “H” input current X IN “L” input current 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” input current RESET, CNV SS “L” input current X IN “L” input current 0–P0 7, P30–P3 7 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 –5.0 –5.0 –0.5 5.5 3000 187.5 V V V V V V V V V V V µA µA µA µA µA µA mA V kHz kHz V OH VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL IIL VRAM R OSC D OSC 0.4 0.5 0.5 4.0 –4.0 –0.2 2000 125 Notes 1: P11 is measured when the P11/TXD 1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: RXD 1, SCLK1 , SCLK2 , SDATA2 , INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level). 3: It is available only when operating key-on wake up.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.5 Electrical characteristics (2) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits UnitTest conditions Power source current 8.0 1.5 10.0 5.0 1000 3.2 450 1.0 6.5 1.2 8.0 5.0 900 3.2 450 1.0 mA mA mA mA µA mA mA µA mA µA µA mA mA mA mA µA mA mA µA mA µA µA I CC 5.0 0.5 6.0 2.0 350 1.6 0.2 150 0.5 0.1 3.5 0.4 4.5 2.0 300 1.6 0.2 150 0.5 0.1 High-speed mode, f(XIN) = 8 MHz Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V Output transistors “off” Double-speed mode, f(XIN) = 6 MHz Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(X IN) = 2 MHz, VCC = 2.2 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, V CC = 5V Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors “off” High-speed mode, f(X IN) = 8 MHz Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V Output transistors “off” Double-speed mode, f(XIN) = 6 MHz Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(X IN) = 2 MHz, VCC = 2.2 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, V CC = 5V Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors “off” One Time PROM version Mask ROM version Ta = 25 °C Ta = 85 °C Ta = 25 °C Ta = 85 °C

Rev.2.00 Jun 21, 2004 (4) A/D Converter Characteristics (General purpose) Table 3.1.6 A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage Conversion time Ladder resistor Reference power source input current A/D port input current Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage Conversion time Ladder resistor Reference power source input current A/D port input current Min. Typ. Max.Symbol Parameter Limits UnitTest conditions VCC = 2.7 to 5.5 V Ta = 25 °C V CC = 2.7 to 5.5 V Ta = 25 °C V CC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V VCC = 2.7 to 5.5 V Ta = 25 °C V CC = 2.7 to 5.5 V Ta = 25 °C V CC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V Bits LSB LSB mV mV mV mV tc(X IN) kΩ µA µA Bits LSB LSB mV mV mV mV tc(X IN) kΩ µA µA ±0.9 5125 3075 122 200 120 5.0 ±1.5 5150 3090 122 200 120 5.0 V OT VFST tCONV R LADDER IVREF II(AD) V OT VFST tCONV R LADDER IVREF II(AD) 5115 3069 150 5125 3075 150 5105 3060 5105 3060 One Time PROM version Mask ROM version

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics (5) Timing Requirements (General purpose) Table 3.1.7 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0 input cycle time CNTR 0, INT0, INT1, input “H” pulse width CNTR 0, INT0, INT1, input “L” pulse width CNTR 1 input cycle time CNTR 1 input “H” pulse width CNTR 1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR 0) tWH (CNTR 0) tWL (CNTR 0) tC (CNTR 1) tWH (CNTR 1) tWL (CNTR 1) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RxD1–SCLK1 ) th(SCLK1 –RxD 1) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SDATA2 –SCLK2 ) th(SCLK2 –SDATA2 ) 125 200 2000 800 800 800 370 370 220 100 1000 400 400 200 200 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Table 3.1.8 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0 input cycle time CNTR 0, INT0, INT1, input “H” pulse width CNTR 0, INT0, INT1, input “L” pulse width CNTR 1 input cycle time CNTR 1 input “H” pulse width CNTR 1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR 0) tWH (CNTR 0) tWL (CNTR 0) tC (CNTR 1) tWH (CNTR 1) tWL (CNTR 1) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RxD1–SCLK1 ) th(SCLK1 –RxD 1) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SDATA2 –SCLK2 ) th(SCLK2 –SDATA2 ) 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.

Rev.2.00 Jun 21, 2004 Table 3.1.9 Timing requirements (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0 input cycle time CNTR 0, INT0, INT1, input “H” pulse width CNTR 0, INT0, INT1, input “L” pulse width CNTR 1 input cycle time CNTR 1 input “H” pulse width CNTR 1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR 0) tWH (CNTR 0) tWL (CNTR 0) tC (CNTR 1) tWH (CNTR 1) tWL (CNTR 1) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RxD1–SCLK1 ) th(SCLK1 –RxD 1) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SDATA2 –SCLK2 ) th(SCLK2 –SDATA2 ) 500 200 200 1000 460 460 8000 3200 3200 4000 1900 1900 800 400 4000 1900 1900 800 800 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics (6) Switching Characteristics (General purpose) Table 3.1.10 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) tC (SCLK1 )/2–30 tC (SCLK1 )/2–30 –30 tC (SCLK2 )/2–30 tC (SCLK2 )/2–30 Min. Typ. Max. Symbol Parameter Limits Unit tWH (SCLK1 ) tWL (SCLK1 ) td(SCLK1 –TxD 1) tv(SCLK1 –TxD 1) tr(SCLK1 ) tf(SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td(SCLK2 –SDATA2 ) tv(SCLK2 –SDATA2 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Note 1: Pin XOUT is excluded. Table 3.1.11 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits Unit 350 350 Note 1: Pin XOUT is excluded. tWH (SCLK1 ) tWL (SCLK1 ) td(SCLK1 –TxD 1) tv(SCLK1 –TxD 1) tr(SCLK1 ) tf(SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td(SCLK2 –SDATA2 ) tv(SCLK2 –SDATA2 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) t C (SCLK1 )/2–50 tC (SCLK1 )/2–50 –30 tC (SCLK2 )/2–50 tC (SCLK2 )/2–50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 140 140 ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Rev.2.00 Jun 21, 2004 Table 3.1.12 Switching characteristics (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits Unit 450 450 Note 1: Pin XOUT is excluded. Fig. 3.1.1 Sw itching characteristics measurement circuit diagram (General purpose) / / / Measured output pin CMOS output 100 pF tWH (SCLK1 ) tWL (SCLK1 ) td(SCLK1 –TxD 1) tv(SCLK1 –TxD 1) tr(SCLK1 ) tf(SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td(SCLK2 –SDATA2 ) tv(SCLK2 –SDATA2 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) t C (SCLK1 )/2–70 tC (SCLK1 )/2–70 –30 tC (SCLK2 )/2–70 tC (SCLK2 )/2–70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics Fig. 3.1.2 Timing chart (General purpose) 0.2VCC td(SCLK1 -TxD1) tf 0.2VCC 0.8VCC 0.8VCC tr tsu(RxD1-SCLK1 )t h(SCLK1 -RxD1) tv(SCLK1 -TxD1) tC (SCLK1 ) tWL (SCLK1 ) tWH (SCLK1 ) R XD 1 (at receive) SCLK1 0.2VCC tWL (XIN) 0.8VCC tWH (XIN) tC (XIN) XIN 0.2VCC 0.8VCC tW (RESET) RESET 0.2VCC tWL (CNTR 0) 0.8VCC tWH (CNTR 0) tC (CNTR 0) TXD 1 (at transmit) CNTR 0 0.2VCC tWL (CNTR 0) 0.8VCC tWH (CNTR 0) INT0, INT1 0.2VCC tWL (CNTR 1) 0.8VCC tWH (CNTR 1) tC (CNTR 1) CNTR 1 0.2VCC td(SCLK2 -SDATA2 ) tf 0.2VCC 0.8VCC 0.8VCC tr tsu(SDATA2 -SCLK2 )t h(SCLK2 -SDATA2 ) tv(SCLK2 -SDATA2 ) tC (SCLK2 ) tWL (SCLK2 ) tWH (SCLK2 ) SDATA2 (at receive) SCLK2 SDATA2 (at transmit)

Rev.2.00 Jun 21, 2004 3.1.2 7540Group (Extended operating temperature version) Applied to: M37540M2T-XXXFP/GP, M37540M4T-XXXFP/GP, M37540E8T-XXXFP/GP (2) Absolute Maximum Ratings (Extended operating temperature version) Table 3.1.13 Absolute maximum ratings –0.3 to 6.5 (Note 1) –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 300 (Note 2) –40 to 85 –65 to 150 Power source voltage Input voltage 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7, VREF Input voltage RESET, XIN, CNVSS Output voltage 0–P0 7, P10–P1 4, P20–P27, P30–P3 7, XOUT Power dissipation Operating temperature Storage temperature V V V V mW V CC VI VI VO Pd Topr Tstg ConditionsSymbol Ratings UnitParameter All voltages are based on VSS . Output transistors are cut off. Ta = 25°C Notes 1: This is the rating value for the Mask ROM version. The rating value for the One Time PROM version is –0.3 to 7.0 V. 2:200 mW for the 32P6U package product.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics (2) Recommended Operating Conditions (Extended operating temperature version) Table 3.1.14 Recommended operating conditions (1) (VCC = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 V CC VCC VCC VCC 4.0 2.4 4.5 4.0 2.4 4.0 2.4 2.0 0.8V CC 2.0 0.8VCC Min. Typ. Max. Symbol Parameter Unit Power source voltage (ceramic)f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 6 MHz (Double-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Limits VCC V V V V V V V V V V V V V V V V mA mA mA mA mA mA Power source voltage Analog reference voltage “H” input voltage 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “H” input voltage (TTL input level selected) 0, P12, P13, P36, P37 (Note 1) “H” input voltage RESET, X IN “L” input voltage 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” input voltage (TTL input level selected) 0, P12, P13, P36, P37 (Note 1) “L” input voltage RESET, CNV SS “L” input voltage X IN “H” total peak output current (Note 2) 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” total peak output current (Note 2) 0–P0 7, P10–P1 4, P20–P2 7, P37 “L” total peak output current (Note 2) 0–P3 6 “H” total average output current (Note 2) 0–P07, P10–P14, P20–P27, P30–P37 “L” total average output current (Note 2) 0–P07, P10–P14, P20–P27, P37 “L” total average output current (Note 2) 0–P3 6 Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 0.3VCC 0.8 0.2VCC 0.16VCC –80 –40 V SS VREF VIH VIH VIH VIL VIL VIL VIL ∑ IOH(peak) ∑ IOL(peak) ∑ IOL(peak) ∑ IOH(avg) ∑ IOL(avg) ∑ IOL(avg) Power source voltage (RC)

Rev.2.00 Jun 21, 2004 Table 3.1.15 Recommended operating conditions (2) (VCC = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted) “H” peak output current (Note 1) P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” peak output current (Note 1) P00–P0 7, P10–P1 4, P20–P2 7, P37 “L” peak output current (Note 1) P30–P3 6 “H” average output current (Note 2) P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” average output current (Note 2) P00–P0 7, P10–P1 4, P20–P2 7, P37 “L” average output current (Note 2) P30–P3 6 Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) V CC = 4.0 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.4 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) V CC = 4.0 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.4 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) V CC = 4.0 to 5.5 V at RC oscillation High-, Middle-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.4 to 5.5 V at RC oscillation High-, Middle-speed mode mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz MHz Symbol Parameter Limits UnitMax.Typ.Min. –10 Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN)

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics (3) Electrical Characteristics (Extended operating temperature version) Table 3.1.16 Electrical characteristics (1) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits Unit IOH = –5 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 2.4 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.4 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.4 to 5.5 V VI = VCC (Pin floating. Pull up transistors “off”) VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors “off”) VI = VSS VI = VSS VI = VSS (Pull up transistors “on”) When clock stopped V CC = 5.0 V, Ta = 25 °C VCC = 5.0 V, Ta = 25 °C Test conditions VCC –1.5 VCC –1.0 2.0 1000 62.5 “H” output voltage P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 (Note 1) “L” output voltage P00–P0 7, P10–P1 4, P20–P2 7, P37 “L” output voltage P30–P3 6 Hysteresis CNTR 0, CNTR1, INT0, INT1(Note 2) P00–P0 7 (Note 3) Hysteresis R XD, SCLK1 , SCLK2 , SDATA2 (Note 2) Hysteresis RESET “H” input current P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “H” input current RESET “H” input current X IN “L” input current 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” input current RESET, CNV SS “L” input current X IN “L” input current 0–P0 7, P30–P3 7 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 –5.0 –5.0 –0.5 5.5 3000 187.5 V V V V V V V V V V V µA µA µA µA µA µA mA V kHz kHz V OH VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL IIL VRAM R OSC D OSC 0.4 0.5 0.5 4.0 –4.0 –0.2 2000 125 Notes 1: P11 is measured when the P11/TXD 1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: RXD1, SCLK1 , SCLK2 , SDATA2 , INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level). 3: It is available only when operating key-on wake up.

Rev.2.00 Jun 21, 2004 Table 3.1.17 Electrical characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Min. Typ. Max.Symbol Limits Unit 8.0 1.5 10.0 5.0 1000 3.2 450 1.0 6.5 1.2 8.0 5.0 900 3.2 450 1.0 mA mA mA mA µA mA mA µA mA µA µA mA mA mA mA µA mA mA µA mA µA µA I CC 5.0 0.5 6.0 2.0 350 1.6 0.2 150 0.5 0.1 3.5 0.4 4.5 2.0 300 1.6 0.2 150 0.5 0.1 High-speed mode, f(XIN) = 8 MHz Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors “off” Double-speed mode, f(XIN) = 6 MHz, Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz, Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(X IN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, V CC = 5V (in WIT state), functions except timer 1 disabled, Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors “off” High-speed mode, f(X IN) = 8 MHz Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors “off” Double-speed mode, f(XIN) = 6 MHz Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(X IN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, V CC = 5V (in WIT state), functions except timer 1 disabled, Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors “off” Ta = 25 °C Ta = 85 °C Test conditions One Time PROM version Mask ROM version Ta = 25 °C Ta = 85 °C

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics (4) A/D Converter Characteristics (Extended operating temperature version) Table 3.1.18 A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage Conversion time Ladder resistor Reference power source input current A/D port input current Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage Conversion time Ladder resistor Reference power source input current A/D port input current Min. Typ. Max.Symbol Parameter Limits UnitTest conditions VCC = 2.7 to 5.5 V Ta = 25 °C V CC = 2.7 to 5.5 V Ta = 25 °C V CC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V VCC = 2.7 to 5.5 V Ta = 25 °C V CC = 2.7 to 5.5 V Ta = 25 °C V CC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V Bits LSB LSB mV mV mV mV tc(X IN) kΩ µA µA Bits LSB LSB mV mV mV mV tc(X IN) kΩ µA µA ±0.9 5125 3075 122 200 120 5.0 ±1.5 5150 3090 122 200 120 5.0 V OT VFST tCONV R LADDER IVREF II(AD) V OT VFST tCONV R LADDER IVREF II(AD) 5115 3069 150 5125 3075 150 5105 3060 5105 3060 One Time PROM version Mask ROM version

Rev.2.00 Jun 21, 2004 (5) Timing Requirements (Extended operating temperature version) Table 3.1.19 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0 input cycle time CNTR 0, INT0, INT1, input “H” pulse width CNTR 0, INT0, INT1, input “L” pulse width CNTR 1 input cycle time CNTR 1 input “H” pulse width CNTR 1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR 0) tWH (CNTR 0) tWL (CNTR 0) tC (CNTR 1) tWH (CNTR 1) tWL (CNTR 1) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RxD1–SCLK1 ) th(SCLK1 –RxD 1) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SDATA2 –SCLK2 ) th(SCLK2 –SDATA2 ) 125 200 2000 800 800 800 370 370 220 100 1000 400 400 200 200 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Table 3.1.20 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0 input cycle time CNTR 0, INT0, INT1, input “H” pulse width CNTR 0, INT0, INT1, input “L” pulse width CNTR 1 input cycle time CNTR 1 input “H” pulse width CNTR 1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR 0) tWH (CNTR 0) tWL (CNTR 0) tC (CNTR 1) tWH (CNTR 1) tWL (CNTR 1) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RxD1–SCLK1 ) th(SCLK1 –RxD 1) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SDATA2 –SCLK2 ) th(SCLK2 –SDATA2 ) 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics Fig. 3.1.3 Switching characteristics measurement circuit diagram (Extended operating temperature) / / / Measured output pin CMOS output 100 pF (6) Switching Characteristics (Extended operating temperature version) Table 3.1.21 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) tC (SCLK1 )/2–30 tC (SCLK1 )/2–30 –30 tC (SCLK2 )/2–30 tC (SCLK2 )/2–30 Min. Typ. Max. Symbol Parameter Limits Unit tWH (SCLK1 ) tWL (SCLK1 ) td(SCLK1 –TxD 1) tv(SCLK1 –TxD 1) tr(SCLK1 ) tf(SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td(SCLK2 –SDATA2 ) tv(SCLK2 –SDATA2 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Note 1: Pin XOUT is excluded. Table 3.1.22 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits Unit 350 350 Note 1: Pin XOUT is excluded. tWH (SCLK1 ) tWL (SCLK1 ) td(SCLK1 –TxD 1) tv(SCLK1 –TxD 1) tr(SCLK1 ) tf(SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td(SCLK2 –SDATA2 ) tv(SCLK2 –SDATA2 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) t C (SCLK1 )/2–50 tC (SCLK1 )/2–50 –30 tC (SCLK2 )/2–50 tC (SCLK2 )/2–50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 140 140 ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Rev.2.00 Jun 21, 2004 Fig. 3.1.4 Timing chart (Extended operating temperature version) 0.2VCC td(SCLK1 -TxD1) tf 0.2VCC 0.8VCC 0.8VCC tr tsu(RxD1-SCLK1 )t h(SCLK1 -RxD1) tv(SCLK1 -TxD1) tC (SCLK1 ) tWL (SCLK1 ) tWH (SCLK1 ) R XD 1 (at receive) SCLK1 0.2VCC tWL (XIN) 0.8VCC tWH (XIN) tC (XIN) XIN 0.2VCC 0.8VCC tW (RESET) RESET 0.2VCC tWL (CNTR 0) 0.8VCC tWH (CNTR 0) tC (CNTR 0) TXD 1 (at transmit) CNTR 0 0.2VCC tWL (CNTR 0) 0.8VCC tWH (CNTR 0) INT0, INT1 0.2VCC tWL (CNTR 1) 0.8VCC tWH (CNTR 1) tC (CNTR 1) CNTR 1 0.2VCC td(SCLK2 -SDATA2 ) tf 0.2VCC 0.8VCC 0.8VCC tr tsu(SDATA2 -SCLK2 )t h(SCLK2 -SDATA2 ) tv(SCLK2 -SDATA2 ) tC (SCLK2 ) tWL (SCLK2 ) tWH (SCLK2 ) SDATA2 (at receive) SCLK2 SDATA2 (at transmit)

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics 3.1.3 7540Group (Extended operating temperature 125 °C version) Applied to: M37540M2V-XXXFP/GP, M37540M4V-XXXFP/GP, M37540E8V-XXXFP/GP (1) Absolute Maximum Ratings (Extended operating temperature 125 °C version) Table 3.1.23 Absolute maximum ratings –0.3 to 6.5 (Note 1) –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 300 (Note 2) –40 to 125 (Note 3) –65 to 150 Power source voltage Input voltage 0–P0 7, P10–P14, P20–P2 7, P30–P3 7, VREF Input voltage RESET, XIN, CNVSS Output voltage 0–P0 7, P10–P14, P20–P27, P30–P3 7, XOUT Power dissipation Operating temperature Storage temperature V V V V mW V CC VI VI VO Pd Topr Tstg ConditionsSymbol Ratings UnitParameter All voltages are based on VSS . Output transistors are cut off. Ta = 25°C Notes 1: This is the rating value for the Mask ROM version. The rating value for the One Time PROM version is –0.3 to 7.0 V. 2:200 mW for the 32P6U package product. 3: In this version, the operating temperature range and total time are limited as follows; 55 °C to 85 °C: within total 6000 hours, 85 °C to 125 °C: within total 1000 hours.

Rev.2.00 Jun 21, 2004 (2) Recommended Operating Conditions (Extended operating temperature 125 °C version) Table 3.1.24 Recommended operating conditions (1) (VCC = 2.4 to 5.5 V, Ta = –40 to 125 °C, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 V CC VCC VCC VCC 4.0 2.4 4.0 2.4 4.0 2.4 2.0 0.8V CC 2.0 0.8VCC Min. Typ. Max. Symbol Parameter Unit Power source voltage (ceramic)f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) 5.0 5.0 5.0 5.0 5.0 5.0 Limits VCC V V V V V V V V V V V V V V V mA mA mA mA mA mA Power source voltage Analog reference voltage “H” input voltage 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “H” input voltage (TTL input level selected) 0, P12, P13, P36, P37 (Note 1) “H” input voltage RESET, X IN “L” input voltage 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” input voltage (TTL input level selected) 0, P12, P13, P36, P37 (Note 1) “L” input voltage RESET, CNV SS “L” input voltage X IN “H” total peak output current (Note 2) 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” total peak output current (Note 2) 0–P0 7, P10–P1 4, P20–P2 7, P37 “L” total peak output current (Note 2) 0–P3 6 “H” total average output current (Note 2) 0–P07, P10–P14, P20–P27, P30–P37 “L” total average output current (Note 2) 0–P07, P10–P14, P20–P27, P37 “L” total average output current (Note 2) 0–P3 6 Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 0.3VCC 0.8 0.2VCC 0.16VCC –80 –40 V SS VREF VIH VIH VIH VIL VIL VIL VIL ∑ IOH(peak) ∑ IOL(peak) ∑ IOL(peak) ∑ IOH(avg) ∑ IOL(avg) ∑ IOL(avg) Power source voltage (RC)

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.25 Recommended operating conditions (2) (VCC = 2.4 to 5.5 V, Ta = –40 to 125 °C, unless otherwise noted) “H” peak output current (Note 1) P00–P0 7, P10–P14, P20–P2 7, P30–P37 “L” peak output current (Note 1) P00–P0 7, P10–P14, P20–P2 7, P37 “L” peak output current (Note 1) P30–P3 6 “H” average output current (Note 2) P00–P0 7, P10–P14, P20–P2 7, P30–P37 “L” average output current (Note 2) P00–P0 7, P10–P14, P20–P2 7, P37 “L” average output current (Note 2) P30–P3 6 Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.4 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) V CC = 4.0 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.4 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) V CC = 4.0 to 5.5 V at RC oscillation High-, Middle-speed mode Internal clock oscillation frequency (Note 3) V CC = 2.4 to 5.5 V at RC oscillation High-, Middle-speed mode mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz Symbol Parameter Limits UnitMax.Typ.Min. –10 Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN)

Rev.2.00 Jun 21, 2004 (3) Electrical Characteristics (Extended operating temperature 125 °C version) Table 3.1.26 Electrical characteristics (1) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits Unit IOH = –5 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 2.4 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.4 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.4 to 5.5 V VI = VCC (Pin floating. Pull up transistors “off”) VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors “off”) VI = VSS VI = VSS VI = VSS (Pull up transistors “on”) When clock stopped V CC = 5.0 V, Ta = 25 °C VCC = 5.0 V, Ta = 25 °C Test conditions VCC –1.5 VCC –1.0 2.0 1000 62.5 “H” output voltage P00–P0 7, P10–P1 4, P20–P27, P30–P3 7 (Note 1) “L” output voltage P00–P0 7, P10–P1 4, P20–P2 7, P37 “L” output voltage P30–P3 6 Hysteresis CNTR 0, CNTR1, INT0, INT1(Note 2) P00–P0 7 (Note 3) Hysteresis R XD, SCLK1 , SCLK2 , SDATA2 (Note 2) Hysteresis RESET “H” input current P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “H” input current RESET “H” input current X IN “L” input current 0–P0 7, P10–P1 4, P20–P2 7, P30–P3 7 “L” input current RESET, CNV SS “L” input current X IN “L” input current 0–P0 7, P30–P3 7 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 –5.0 –5.0 –0.5 5.5 3000 187.5 V V V V V V V V V V V µA µA µA µA µA µA mA V kHz kHz V OH VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL IIL VRAM R OSC D OSC 0.4 0.5 0.5 4.0 –4.0 –0.2 2000 125 Notes 1: P11 is measured when the P11/TXD 1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: RXD1, SCLK1 , SCLK2 , SDATA2 , INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level). 3: It is available only when operating key-on wake up.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.27 Electrical characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Min. Typ. Max.Symbol Limits Unit 8.0 1.5 5.0 1000 3.2 450 1.0 6.5 1.2 5.0 900 3.2 450 1.0 mA mA mA µA mA mA µA mA µA µA mA mA mA µA mA mA µA mA µA µA I CC 5.0 0.5 2.0 350 1.6 0.2 150 0.5 0.1 3.5 0.4 2.0 300 1.6 0.2 150 0.5 0.1 High-speed mode, f(XIN) = 8 MHz Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz, Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(X IN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, V CC = 5V (in WIT state), functions except timer 1 disabled, Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors “off” High-speed mode, f(X IN) = 8 MHz Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz, Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(X IN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, V CC = 5V (in WIT state), functions except timer 1 disabled, Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped (in STP state) Output transistors “off” Ta = 25 °C Ta = 125 °C Test conditions One Time PROM version Mask ROM version Ta = 25 °C Ta = 125 °C

Rev.2.00 Jun 21, 2004 (4) A/D Converter Characteristics (Extended operating temperature 125 °C version) Table 3.1.28 A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage Conversion time Ladder resistor Reference power source input current A/D port input current Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage Conversion time Ladder resistor Reference power source input current A/D port input current Min. Typ. Max.Symbol Parameter Limits UnitTest conditions VCC = 2.7 to 5.5 V Ta = 25 °C V CC = 2.7 to 5.5 V Ta = 25 °C V CC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V VCC = 2.7 to 5.5 V Ta = 25 °C V CC = 2.7 to 5.5 V Ta = 25 °C V CC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V Bits LSB LSB mV mV mV mV tc(X IN) kΩ µA µA Bits LSB LSB mV mV mV mV tc(X IN) kΩ µA µA ±0.9 5125 3075 122 200 120 7.0 ±1.5 5150 3090 122 200 120 7.0 V OT VFST tCONV R LADDER IVREF II(AD) V OT VFST tCONV R LADDER IVREF II(AD) 5115 3069 150 5125 3075 150 5105 3060 5105 3060 One Time PROM version Mask ROM version

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics (5) Timing Requirements (Extended operating temperature 125 °C version) Table 3.1.29 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0 input cycle time CNTR 0, INT0, INT1, input “H” pulse width CNTR 0, INT0, INT1, input “L” pulse width CNTR 1 input cycle time CNTR 1 input “H” pulse width CNTR 1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR 0) tWH (CNTR 0) tWL (CNTR 0) tC (CNTR 1) tWH (CNTR 1) tWL (CNTR 1) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RxD1–SCLK1 ) th(SCLK1 –RxD 1) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SDATA2 –SCLK2 ) th(SCLK2 –SDATA2 ) 125 200 2000 800 800 800 370 370 220 100 1000 400 400 200 200 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Table 3.1.30 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0 input cycle time CNTR 0, INT0, INT1, input “H” pulse width CNTR 0, INT0, INT1, input “L” pulse width CNTR 1 input cycle time CNTR 1 input “H” pulse width CNTR 1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR 0) tWH (CNTR 0) tWL (CNTR 0) tC (CNTR 1) tWH (CNTR 1) tWL (CNTR 1) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RxD1–SCLK1 ) th(SCLK1 –RxD 1) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SDATA2 –SCLK2 ) th(SCLK2 –SDATA2 ) 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.

Rev.2.00 Jun 21, 2004 Fig. 3.1.5 Switching characteristics measurement circuit diagram (Extended operating temperature 125 °C version) / / / Measured output pin CMOS output 100 pF (6) Switching Characteristics (Extended operating temperature 125 °C version) Table 3.1.30 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) tC (SCLK1 )/2–50 tC (SCLK1 )/2–50 –30 tC (SCLK2 )/2–50 tC (SCLK2 )/2–50 Min. Typ. Max. Symbol Parameter Limits Unit tWH (SCLK1 ) tWL (SCLK1 ) td(SCLK1 –TxD 1) tv(SCLK1 –TxD 1) tr(SCLK1 ) tf(SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td(SCLK2 –SDATA2 ) tv(SCLK2 –SDATA2 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Note 1: Pin XOUT is excluded. Table 3.1.31 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Min. Typ. Max.Symbol Parameter Limits Unit 350 350 Note 1: Pin XOUT is excluded. tWH (SCLK1 ) tWL (SCLK1 ) td(SCLK1 –TxD 1) tv(SCLK1 –TxD 1) tr(SCLK1 ) tf(SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td(SCLK2 –SDATA2 ) tv(SCLK2 –SDATA2 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) t C (SCLK1 )/2–80 tC (SCLK1 )/2–80 –30 tC (SCLK2 )/2–80 tC (SCLK2 )/2–80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 140 140 ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics Fig. 3.1.6 Timing chart (Extended operating temperature 125 °C version) 0.2VCC td(SCLK1 -TxD1) tf 0.2VCC 0.8VCC 0.8VCC tr tsu(RxD1-SCLK1 )t h(SCLK1 -RxD1) tv(SCLK1 -TxD1) tC (SCLK1 ) tWL (SCLK1 ) tWH (SCLK1 ) R XD 1 (at receive) SCLK1 0.2VCC tWL (XIN) 0.8VCC tWH (XIN) tC (XIN) XIN 0.2VCC 0.8VCC tW (RESET) RESET 0.2VCC tWL (CNTR 0) 0.8VCC tWH (CNTR 0) tC (CNTR 0) TXD 1 (at transmit) CNTR 0 0.2VCC tWL (CNTR 0) 0.8VCC tWH (CNTR 0) INT0, INT1 0.2VCC tWL (CNTR 1) 0.8VCC tWH (CNTR 1) tC (CNTR 1) CNTR 1 0.2VCC td(SCLK2 -SDATA2 ) tf 0.2VCC 0.8VCC 0.8VCC tr tsu(SDATA2 -SCLK2 )t h(SCLK2 -SDATA2 ) tv(SCLK2 -SDATA2 ) tC (SCLK2 ) tWL (SCLK2 ) tWH (SCLK2 ) SDATA2 (at receive) SCLK2 SDATA2 (at transmit)

Rev.2.00 Jun 21, 2004 Standard characteristics described below are just examples of the 7540 Group’s characteristics and are not guaranteed. For rated values, refer to “3.1 Electrical characteristics”.

3.2.1 Mask ROM version

(1) Power source current characteristic example (VCC -ICC characteristics) Fig. 3.2.1 VCC -ICC characteristics (in double-speed mode: Mask ROM version) Measuring condition: When system is operating in double-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Power source voltage Vcc [V] f(XIN) = 6 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz f(XIN) = 1 MHz 23456 Fig. 3.2.2 VCC -ICC characteristics (in high-speed mode: Mask ROM version) Measuring condition: When system is operating in high-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Power source voltage Vcc [V] f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz Fig. 3.2.3 VCC -ICC characteristics (in middle-speed mode: Mask ROM version) Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Power source voltage Vcc [V] f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 0.0 0.5 1.0 1.5 23456 23456 Fig. 3.2.4 VCC -ICC characteristics (at WIT instruction execution: Mask ROM version) Measuring condition: At WIT instruction execution (at wait), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Power source voltage Vcc [V] f(XIN) = 6 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz Fig. 3.2.5 VCC -ICC characteristics (at STP instruction execution: Mask ROM version) Measuring condition: At STP instruction execution (at stop), Ta = 25 °C, On-chip oscillator stop Power source current Icc [nA] Power source voltage Vcc [V]

Rev.2.00 Jun 21, 2004 Fig. 3.2.6 VCC -ICC characteristics (addition when operating A/D conversion, f(XIN) = 8 MHz in high- speed mode: Mask ROM version) Measuring condition: A/D conversion executed/not executed (f(XIN) = 8 MHz in high-speed mode), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Power source voltage Vcc [V] During A/D conversion Power source current Icc [mA] Power source voltage Vcc [V] During not A/D conversion Fig. 3.2.7 VCC -ICC characteristics (addition when operating A/D conversion, f(XIN) = 6 MHz in double- speed mode: Mask ROM version) Measuring condition: A/D conversion executed/not executed (f(XIN) = 6 MHz in double-speed mode), Ta = 25 °C, Ceramic oscillation During A/D conversion During not A/D conversion

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 100 200 300 23456 200 400 600 23456 Fig. 3.2.8 VCC -ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: Mask ROM version) Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed), Ceramic oscillation stop Power source current Icc [ µA] Power source voltage Vcc [V] Ta = –25 °C Ta = 25 °C Ta = –45 °C Fig. 3.2.9 VCC -ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: Mask ROM version) Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution Ceramic oscillation stop Power source current Icc [ µA] Power source voltage Vcc [V] Ta = 90 °C Ta = 130 °C Ta = –25 °C Ta = 25 °C Ta = –45 °C Ta = 90 °C Ta = 130 °C

Rev.2.00 Jun 21, 2004 0.0 0.5 1.0 1.5 2.0 2.5 2345678 23456780 123456 Fig. 3.2.10 f(XIN)-ICC characteristics (in double-speed mode: Mask ROM version) Measuring condition: When system is operating in double-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Oscillation frequency f(XIN) [MHz] V CC = 5.0 V V CC = 3.0 V Fig. 3.2.11 f(XIN)-ICC characteristics (in high-speed mode: Mask ROM version) Measuring condition: When system is operating in high-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Oscillation frequency f(XIN) [MHz] Fig. 3.2.12 f(XIN)-ICC characteristics (in middle-speed mode: Mask ROM version) Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Oscillation frequency f(XIN) [MHz] V CC = 5.0 V V CC = 3.0 V V CC = 5.0 V V CC = 3.0 V (2) Power source current characteristic example (f(XIN)-ICC characteristics)

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 100 150 200 -50 -25 0 25 50 75 100 125 150 100 200 300 400 -50 -25 0 25 50 75 100 125 150 0.0 0.5 1.0 1.5 2.0 12345678 Fig. 3.2.13 f(XIN)-ICC characteristics (at WIT instruction execution: Mask ROM version) Measuring condition: At WIT instruction execution, Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Oscillation frequency f(XIN) [MHz] Fig. 3.2.14 Ta-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: Mask ROM version) Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed), Ceramic oscillation stop Power source current Icc [ µA] Operating temperature range [°C] Fig. 3.2.15 Ta-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: Mask ROM version) Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop Power source current Icc [ µA] Operating temperature range Ta [°C] (3) Power source current characteristic example (Ta-ICC characteristics) V CC = 5.0 V V CC = 3.0 V V CC = 5.0 V V CC = 3.0 V V CC = 5.0 V V CC = 3.0 V

Rev.2.00 Jun 21, 2004 Fig. 3.2.16 VCC -VIHL characteristics (I/O port (CMOS): Mask ROM version) Measuring condition: VCC –V IHL characteristics of I/O port (CMOS), VCC = 5.0 V, Ta = 25 °C (same characteristics pins: P01–P0 7, P11, P20–P2 7, P30–P3 5) Input voltage V IHL [V] Power source voltage Vcc [V] Fig. 3.2.17 VCC -VIHL characteristics (I/O port (TTL): Mask ROM version) Measuring condition: VCC –V IHL characteristics of I/O port (TTL), VCC = 5.0 V, Ta = 25 °C (same characteristics pins: P10, P12, P13, P36, P37) Input voltage V IHL [V] Power source voltage Vcc [V] (4) Port typical characteristic example (VCC -VIHL characteristics)

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 23456 23456 Fig. 3.2.19 VCC -VIHL characteristics (XIN pin: Mask ROM version) Power source voltage Vcc [V] Fig. 3.2.20 VCC -VIL characteristics (CNVSS pin: Mask ROM version) Measuring condition: VCC –V IL characteristics of CNVSS pin, VCC = 5.0 V, Ta = 25 °C Input voltage V IL [V] Power source voltage Vcc [V] Measuring condition: VCC –V IHL characteristics of XIN pin, VCC = 5.0 V, Ta = 25 °C Input voltage V IHL [V] 23456 Fig. 3.2.18 VCC -VIHL characteristics (RESET pin: Mask ROM version) Measuring condition: VCC –V IHL characteristics of RESET pin, VCC = 5.0 V, Ta = 25 °C Input voltage V IHL [V] Power source voltage Vcc [V] “H” input voltage (VIH) “L” input voltage (VIL)

Rev.2.00 Jun 21, 2004 0.0 0.2 0.4 0.6 0.8 1.0 23456 0.0 0.2 0.4 0.6 0.8 1.0 23456 0.0 0.2 0.4 0.6 0.8 1.0 23456 Fig. 3.2.21 VCC -HYS characteristics (RESET pin: Mask ROM version) Measuring condition: VCC –HYS characteristics of RESET pin, VCC = 5.0 V, Ta = 25 °C Hysteresis HYS [V] Power source voltage Vcc [V] Fig. 3.2.22 VCC -HYS characteristics (SIO pin: Mask ROM version) Measuring condition: VCC –HYS characteristics of SIO pin, VCC = 5.0 V, Ta = 25 °C (same characteristics pins: RxD1, SCLK1 , SCLK2 , SDATA2 ) Hysteresis HYS [V] Power source voltage Vcc [V] Fig. 3.2.23 VCC -HYS characteristics (INT pin: Mask ROM version) Measuring condition: VCC –HYS characteristics of INT pin, VCC = 5.0 V, Ta = 25 °C (same characteristics pins: CNTR0, CNTR 1, INT0, INT1, P00–P0 7) Hysteresis HYS [V] Power source voltage Vcc [V]

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics -40 -30 -20 -10 012345 -15 -10 0123 Fig. 3.2.24 VOH -IOH characteristics of P-channel (VCC = 3.0 V, normal port: Mask ROM version) Measuring condition: VOH –IOH characteristics of P-channel (normal port), VCC = 3.0 V (same characteristics pins: P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7) “H” output current I OH [mA] “H” output voltage VOH [V] Ta = 25 °C Ta = 125 °C Ta = –40 °C Fig. 3.2.25 VOH -IOH characteristics of P-channel (VCC = 5.0 V, normal port: Mask ROM version) Measuring condition: VOH –IOH characteristics of P-channel (normal port), VCC = 5.0 V (same characteristics pins: P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7) “H” output current I OH [mA] “H” output voltage VOH [V] Ta = 25 °C Ta = 125 °C Ta = –40 °C (5) Port typical characteristic example (VOH -IOH characteristics)

Rev.2.00 Jun 21, 2004 Fig. 3.2.26 VOL -IOL characteristics of N-channel (VCC = 3.0 V, normal port: Mask ROM version) Measuring condition: VOL –IOL characteristics of N-channel (normal port), VCC = 3.0 V (same characteristics pins: P00–P0 7, P10–P1 4, P20–P2 7, P37) “L” output current I OL [mA] “L” output voltage VOL [V] Ta = 25 °C Ta = 125 °C Ta = –40 °C Fig. 3.2.27 VOL -IOL characteristics of N-channel (VCC = 5.0 V, normal port: Mask ROM version) Measuring condition: VOL –IOL characteristics of N-channel (normal port), VCC = 5.0 V (same characteristics pins: P00–P0 7, P10–P1 4, P20–P2 7, P37) “L” output current I OL [mA] “L” output voltage VOL [V] Ta = 25 °C Ta = 125 °C Ta = –40 °C (6) Port typical characteristic example (VOL -IOL characteristics)

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 100 012345 0123 Fig. 3.2.28 VOL -IOL characteristics of N-channel (VCC = 3.0 V, LED drive port: Mask ROM version) Measuring condition: VOL –IOL characteristics of N-channel (LED drive port), VCC = 3.0 V (same characteristics pins: P30–P3 6) “L” output current I OL [mA] “L” output voltage VOL [V] Ta = 25 °C Ta = 125 °C Ta = –40 °C Fig. 3.2.29 VOL -IOL characteristics of N-channel (VCC = 5.0 V, LED drive port: Mask ROM version) Measuring condition: VOL –IOL characteristics of N-channel (LED drive port), VCC = 5.0 V (same characteristics pins: P30–P3 6) “L” output current I OL [mA] “L” output voltage VOL [V] Ta = 25 °C Ta = 125 °C Ta = –40 °C

Rev.2.00 Jun 21, 2004 -0.4 -0.3 -0.2 -0.1 23456 (7) Port typical characteristic example (VCC -IIL characteristics) Fig. 3.2.30 VCC -IIL characteristics (Port “L” input current when connecting pull-up transistor: Mask ROM version) Measuring condition: Port “L” input current when connecting pull-up transistor (same characteristics pins: P00–P0 7, P30–P3 7) “L” output current IIL [mA] Power source voltage VCC [V] Ta = –25 °C Ta = 130 °C Ta = –45 °C Ta = 90 °C Ta = 25 °C

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics -0.3 -0.2 -0.1 0.1 0.2 0.3 012345-0.3 -0.2 -0.1 0.1 0.2 0.3 012345 -0.3 -0.2 -0.1 0.1 0.2 0.3 012345 Fig. 3.2.31 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 8 MHz in high-speed mode: Mask ROM version) Measuring condition: f(XIN) = 8 MHz in high-speed mode, VCC = 5.0 V, Ta = 25 °C (same characteristics pins: P20–P2 7) Input current II(AD) [ µA] Input voltage VIN [V] Fig. 3.2.32 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 6 MHz in double-speed mode: Mask ROM version) Measuring condition: f(XIN) = 6 MHz in double-speed mode, VCC = 5.0 V, Ta = 25 °C (same characteristics pins: P20–P2 7) Input current II(AD) [ µA] Input voltage VIN [V] Fig. 3.2.33 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 4 MHz in double-speed mode: Mask ROM version) Measuring condition: f(XIN) = 4 MHz in double-speed mode, VCC = 5.0 V, Ta = 25 °C (same characteristics pins: P20–P2 7) Input current II(AD) [ µA] (8) Port typical characteristic example (VIN-II(AD) characteristics) Input voltage VIN [V]

Rev.2.00 Jun 21, 2004 -60 -40 -20 0 20 40 60 80 100 120 140 23456 Fig. 3.2.34 VCC -ROSC characteristics (on-chip oscillator frequency: Mask ROM version) Measuring parameter: On-chip oscillator frequency On-chip oscillator frequency R OSC [MHz] Power source voltage Vcc [V] Fig. 3.2.35 Ta-ROSC characteristics (on-chip oscillator frequency: Mask ROM version) Measuring parameter: On-chip oscillator frequency On-chip oscillator frequency R OSC [MHz] Operating temperature range Ta [°C] (9) On-chip oscillator frequency typical characteristic example Ta = –25 °C Ta = 130 °C Ta = –45 °C Ta = 90 °C Ta = 25 °C V CC = 5.0 V V CC = 3.0 V

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 0 1 02 03 04 05 06 0 0 1 02 03 04 05 0 Fig. 3.2.36 R-f(XIN) characteristics (RC oscillation frequency: Mask ROM version) Measuring parameter: RC oscillation frequency Measuring condition: VCC = 5.0 V, Ta = 25 °C, C = 33 pF RC oscillation frequency f(X IN ) [MHz] External resistor R [kΩ ] Fig. 3.2.37 C-f(XIN) characteristics (RC oscillation frequency: Mask ROM version) Measuring parameter: RC oscillation frequency Measuring condition: VCC = 5.0 V, Ta = 25 °C, R = 6.8 kΩ (fixed) RC oscillation frequency f(X IN ) [MHz] External capacitor C [pF] (10) RC oscillation frequency typical characteristic example

Rev.2.00 Jun 21, 2004 3.0 3.5 4.0 4.5 5.0 -60 -40 -20 0 20 40 60 80 100 120 140 23456 Fig. 3.2.38 VCC -f(XIN) characteristics (RC oscillation frequency: Mask ROM version) Measuring parameter: RC oscillation frequency Measuring condition: Ta = 25 °C, f(XIN) ≅ 4 MHz (R = 5.1 kΩ , C = 20 pF) RC oscillation frequency f(X IN ) [MHz] Power source voltage VCC [V] Fig. 3.2.39 Ta-f(XIN) characteristics (RC oscillation frequency: Mask ROM version) Measuring parameter: RC oscillation frequency Measuring condition: f(XIN) ≅ 4 MHz (R = 5.1 kΩ , C = 20 pF) RC oscillation frequency f(X IN ) [MHz] Operating temperature range Ta [°C] V CC = 5.0 V V CC = 3.0 V

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics (11) A/D conversion typical characteristics example ➀ Definition of A/D conversion accuracy The A/D conversion accuracy is defined below (refer to Fig. 3.2.40). G Relative accuracy

• Zero transition voltage (VOT ) This means an analog input voltage when the actual A/D conversion output data changes from “0” to “1.”
• Full-scale transition voltage (VFST ) This means an analog input voltage when the actual A/D conversion output data changes from “1023” to “1022.”
• Non-linearity error This means a deviation from the line between VOT and VFST of a converted value between VOT and V FST .
• Differential non-linearity error This means a deviation from the input potential difference required to change a converted value between V OT and VFST by 1 LSB of the 1 LSB at the relative accuracy. G Absolute accuracy This means a deviation from the ideal characteristics between 0 to VREF of actual A/D conversion characteristics. V REF 1024 Fig. 3.2.40 Definition of A/D conversion accuracy Vn: Analog input voltage when the output data changes from “n” to “n + 1” (n = 0 to 1022)
• 1 LSB at relative accuracy → (V)
• 1 LSB at absolute accuracy → (V) V FST – VOT 1022 Analog voltageVR E FV1 2VnV1V0 Z e r o t r a n s i t i o n v o l t a g e ( V0 Full-scale transition voltage (VFST ) N o n - l i n e a r i t y e r r o r = Actual A/D conversion characteristics Vn n+1 n 1022 I d e a l l i n e o f A / D c o n v e r s i o n b e t w e e n t o Output data b a a : 1 L S B a t r e l a t i v e a c c u r a c y b Vn Vn c D i f f e r e n c e b e t w e e n t h e i d e a l V n a n d a c t u a l V n Differential non-linearity error=b-a a [LSB] c c a [LSB]

Rev.2.00 Jun 21, 2004 -15 -10 0 32 64 96 128 160 192 224 256 -15 -10 256 288 320 352 384 416 448 480 512 -15 -10 512 544 576 608 640 672 704 736 768 -15 -10 768 800 832 864 896 928 960 992 1024 Fig. 3.2.41 A/D conversion accuracy typical characteristic example-1 (Mask ROM version)

• VCC = 5.12 [V]
• VREF = 5.12 [V]
• XIN = 4 [MHz]
• Temp. = 25 [°C]
• CPU mode = double-speed mode
• Zero transition voltage: 13.75 mV
• Full-scale transition voltage: 5120.94 mV
• Differential non-linearity error: –1.72 mV (–0.34 LSB)
• Non-linearity error: –5.09 mV (–1.02 LSB) M37540M4-XXXFP A/D CONVERTER STEP WIDTH MEASUREMENT Reference(ERROR(ABSOLUTE)) ERROR/1LSB WIDTH [mV] ERROR (LINEARITY) 1LSB WIDTH ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ➁ A/D conversion accuracy typical characteristics-1

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics -15 -10 0 32 64 96 128 160 192 224 256 -15 -10 256 288 320 352 384 416 448 480 512 -15 -10 512 544 576 608 640 672 704 736 768 -15 -10 768 800 832 864 896 928 960 992 1024 Fig. 3.2.42 A/D conversion accuracy typical characteristic example-2 (Mask ROM version)

• VCC = 5.12 [V]
• VREF = 5.12 [V]
• XIN = 6 [MHz]
• Temp. = 25 [°C]
• CPU mode = double-speed mode
• Zero transition voltage: 14.38 mV
• Full-scale transition voltage: 5121.88 mV
• Differential non-linearity error: 1.41 mV (0.28 LSB)
• Non-linearity error: –4.23 mV (–0.85 LSB) M37540M4-XXXFP A/D CONVERTER STEP WIDTH MEASUREMENT Reference(ERROR(ABSOLUTE)) ERROR/1LSB WIDTH [mV] ERROR (LINEARITY) 1LSB WIDTH ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ➂ A/D conversion accuracy typical characteristics-2

Rev.2.00 Jun 21, 2004 -10 0 32 64 96 128 160 192 224 256 -10 256 288 320 352 384 416 448 480 512 -10 512 544 576 608 640 672 704 736 768 -10 768 800 832 864 896 928 960 992 1024 Fig. 3.2.43 A/D conversion accuracy typical characteristic example-3 (Mask ROM version)

• VCC = 5.12 [V]
• VREF = 5.12 [V]
• XIN = 8 [MHz]
• Temp. = 25 [°C]
• CPU mode = high-speed mode
• Zero transition voltage: 30.31 mV
• Full-scale transition voltage: 5143.33 mV
• Differential non-linearity error: 1.72 mV (0.34 LSB)
• Non-linearity error: –7.64 mV (–1.53 LSB) M37540M4-XXXFP A/D CONVERTER STEP WIDTH MEASUREMENT Reference(ERROR(ABSOLUTE)) ERROR/1LSB WIDTH [mV] ERROR (LINEARITY) 1LSB WIDTH ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ➃ A/D conversion accuracy typical characteristics-3

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 23456 23456 23456

3.2.2 One Time PROM version

(1) Power source current characteristic example (VCC -ICC characteristics) Fig. 3.2.44 VCC -ICC characteristics (in double-speed mode: One Time PROM version) Measuring condition: When system is operating in double-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Power source voltage Vcc [V] f(XIN) = 6 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz f(XIN) = 1 MHz Fig. 3.2.45 VCC -ICC characteristics (in high-speed mode: One Time PROM version) Measuring condition: When system is operating in high-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Power source voltage Vcc [V] f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz Fig. 3.2.46 VCC -ICC characteristics (in middle-speed mode: One Time PROM version) Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Power source voltage Vcc [V] f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz

Rev.2.00 Jun 21, 2004 Fig. 3.2.47 VCC -ICC characteristics (at WIT instruction execution: One Time PROM version) Measuring condition: At WIT instruction execution (at wait), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Power source voltage Vcc [V] f(XIN) = 6 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz Fig. 3.2.48 VCC -ICC characteristics (at STP instruction execution: One Time PROM version) Measuring condition: At STP instruction execution (at stop), Ta = 25 °C, On-chip oscillator stop Power source current Icc [nA] Power source voltage Vcc [V]

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics Fig. 3.2.49 VCC -ICC characteristics (addition when operating A/D conversion, f(XIN) = 8 MHz in high- speed mode: One Time PROM version) Measuring condition: A/D conversion executed/not executed (f(XIN) = 8 MHz in high-speed mode), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Power source voltage Vcc [V] During A/D conversion Power source current Icc [mA] Power source voltage Vcc [V] During not A/D conversion Fig. 3.2.50 VCC -ICC characteristics (addition when operating A/D conversion, f(XIN) = 6 MHz in double- speed mode: One Time PROM version) Measuring condition: A/D conversion executed/not executed (f(XIN) = 6 MHz in double-speed mode), Ta = 25 °C, Ceramic oscillation During A/D conversion During not A/D conversion

Rev.2.00 Jun 21, 2004 Fig. 3.2.51 VCC -ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: One Time PROM version) Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed), Ceramic oscillation stop Power source current Icc [ µA] Power source voltage Vcc [V] Ta = –25 °C Ta = 25 °C Ta = –45 °C Fig. 3.2.52 VCC -ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: One Time PROM version) Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution Ceramic oscillation stop Power source current Icc [ µA] Power source voltage Vcc [V] Ta = 90 °C Ta = 130 °C Ta = –25 °C Ta = 25 °C Ta = –45 °C Ta = 90 °C Ta = 130 °C

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 2345678 2345678 123456 Fig. 3.2.53 f(XIN)-ICC characteristics (in double-speed mode: One Time PROM version) Measuring condition: When system is operating in double-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Oscillation frequency f(XIN) [MHz] V CC = 5.0 V V CC = 3.0 V Fig. 3.2.54 f(XIN)-ICC characteristics (in high-speed mode: One Time PROM version) Measuring condition: When system is operating in high-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Oscillation frequency f(XIN) [MHz] Fig. 3.2.55 f(XIN)-ICC characteristics (in middle-speed mode: One Time PROM version) Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed), Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Oscillation frequency f(XIN) [MHz] V CC = 5.0 V V CC = 3.0 V V CC = 5.0 V V CC = 3.0 V (2) Power source current characteristic example (f(XIN)-ICC characteristics)

Rev.2.00 Jun 21, 2004 -50 -25 0 25 50 75 100 125 150 100 200 300 400 500 -50 -25 0 25 50 75 100 125 150 0.0 0.5 1.0 1.5 2.0 12345678 Fig. 3.2.56 f(XIN)-ICC characteristics (at WIT instruction execution: One Time PROM version) Measuring condition: At WIT instruction execution, Ta = 25 °C, Ceramic oscillation Power source current Icc [mA] Oscillation frequency f(XIN) [MHz] Fig. 3.2.57 Ta-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: One Time PROM version) Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed), Ceramic oscillation stop Power source current Icc [ µA] Operating temperature range [°C] Fig. 3.2.58 Ta-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: One Time PROM version) Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop Power source current Icc [ µA] Operating temperature range Ta [°C] (3) Power source current characteristic example (Ta-ICC characteristics) V CC = 5.0 V V CC = 3.0 V V CC = 5.0 V V CC = 3.0 V V CC = 5.0 V V CC = 3.0 V

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 3456 23456 Fig. 3.2.59 VCC -VIHL characteristics (I/O port (CMOS): One Time PROM version) Measuring condition: VCC –V IHL characteristics of I/O port (CMOS), VCC = 5.0 V, Ta = 25 °C (same characteristics pins: P01–P0 7, P11, P20–P2 7, P30–P3 5) Input voltage V IHL [V] Power source voltage Vcc [V] Fig. 3.2.60 VCC -VIHL characteristics (I/O port (TTL): One Time PROM version) Measuring condition: VCC –V IHL characteristics of I/O port (TTL), VCC = 5.0 V, Ta = 25 °C (same characteristics pins: P10, P12, P13, P36, P37) Input voltage V IHL [V] Power source voltage Vcc [V] (4) Port typical characteristic example (VCC -VIHL characteristics)

Rev.2.00 Jun 21, 2004 Fig. 3.2.62 VCC -VIHL characteristics (XIN pin: One Time PROM version) Power source voltage Vcc [V] Fig. 3.2.63 VCC -VIL characteristics (CNVSS pin: One Time PROM version) Measuring condition: VCC –V IL characteristics of CNVSS pin, VCC = 5.0 V, Ta = 25 °C Input voltage V IL [V] Power source voltage Vcc [V] Measuring condition: VCC –V IHL characteristics of XIN pin, VCC = 5.0 V, Ta = 25 °C Input voltage V IHL [V] Fig. 3.2.61 VCC -VIHL characteristics (RESET pin: One Time PROM version) Measuring condition: VCC –V IHL characteristics of RESET pin, VCC = 5.0 V, Ta = 25 °C Input voltage V IHL [V] Power source voltage Vcc [V] “H” input voltage (VIH) “L” input voltage (VIL)

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 0.0 0.2 0.4 0.6 0.8 1.0 23456 0.0 0.2 0.4 0.6 0.8 1.0 23456 0.0 0.2 0.4 0.6 0.8 1.0 23456 Fig. 3.2.64 VCC -HYS characteristics (RESET pin: One Time PROM version) Measuring condition: VCC –HYS characteristics of RESET pin, VCC = 5.0 V, Ta = 25 °C Hysteresis HYS [V] Power source voltage Vcc [V] Fig. 3.2.65 VCC -HYS characteristics (SIO pin: One Time PROM version) Measuring condition: VCC –HYS characteristics of SIO pin, VCC = 5.0 V, Ta = 25 °C (same characteristics pins: RxD1, SCLK1 , SCLK2 , SDATA2 ) Hysteresis HYS [V] Power source voltage Vcc [V] Fig. 3.2.66 VCC -HYS characteristics (INT pin: One Time PROM version) Measuring condition: VCC –HYS characteristics of INT pin, VCC = 5.0 V, Ta = 25 °C (same characteristics pins: CNTR0, CNTR 1, INT0, INT1, P00–P0 7) Hysteresis HYS [V] Power source voltage Vcc [V]

Rev.2.00 Jun 21, 2004 -50 -40 -30 -20 -10 012345 -15 -10 0123 Fig. 3.2.67 VOH -IOH characteristics of P-channel (VCC = 3.0 V, normal port: One Time PROM version) Measuring condition: VOH –IOH characteristics of P-channel (normal port), VCC = 3.0 V (same characteristics pins: P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7) “H” output current I OH [mA] “H” output voltage VOH [V] Ta = 25 °C Ta = 125 °C Fig. 3.2.68 VOH -IOH characteristics of P-channel (VCC = 5.0 V, normal port: One Time PROM version) Measuring condition: VOH –IOH characteristics of P-channel (normal port), VCC = 5.0 V (same characteristics pins: P00–P0 7, P10–P1 4, P20–P2 7, P30–P3 7) “H” output current I OH [mA] “H” output voltage VOH [V] Ta = 25 °C Ta = 125 °C Ta = –40 °C (5) Port typical characteristic example (VOH -IOH characteristics)

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 012345 0123 Fig. 3.2.69 VOL -IOL characteristics of N-channel (VCC = 3.0 V, normal port: One Time PROM version) Measuring condition: VOL –IOL characteristics of N-channel (normal port), VCC = 3.0 V (same characteristics pins: P00–P0 7, P10–P1 4, P20–P2 7, P37) “L” output current I OL [mA] “L” output voltage VOL [V] Ta = 25 °C Ta = 125 °C Fig. 3.2.70 VOL -IOL characteristics of N-channel (VCC = 5.0 V, normal port: One Time PROM version) Measuring condition: VOL –IOL characteristics of N-channel (normal port), VCC = 5.0 V (same characteristics pins: P00–P0 7, P10–P1 4, P20–P2 7, P37) “L” output current I OL [mA] “L” output voltage VOL [V] Ta = 25 °C Ta = 125 °C Ta = –40 °C (6) Port typical characteristic example (VOL -IOL characteristics)

Rev.2.00 Jun 21, 2004 Fig. 3.2.71 VOL -IOL characteristics of N-channel (VCC = 3.0 V, LED drive port: One Time PROM version) Measuring condition: VOL –IOL characteristics of N-channel (LED drive port), VCC = 3.0 V (same characteristics pins: P30–P3 6) “L” output current I OL [mA] “L” output voltage VOL [V] Ta = 25 °C Ta = 125 °C Fig. 3.2.72 VOL -IOL characteristics of N-channel (VCC = 5.0 V, LED drive port: One Time PROM version) Measuring condition: VOL –IOL characteristics of N-channel (LED drive port), VCC = 5.0 V (same characteristics pins: P30–P3 6) “L” output current I OL [mA] “L” output voltage VOL [V] Ta = 25 °C Ta = 125 °C Ta = –40 °C

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics -0.5 -0.4 -0.3 -0.2 -0.1 23456 (7) Port typical characteristic example (VCC -IIL characteristics) Fig. 3.2.73 VCC -IIL characteristics (Port “L” input current when connecting pull-up transistor: One Time PROM version) Measuring condition: Port “L” input current when connecting pull-up transistor (same characteristics pins: P00–P0 7, P30–P3 7) “L” output current IIL [mA] Power source voltage VCC [V] Ta = –25 °C Ta = 130 °C Ta = –45 °C Ta = 90 °C Ta = 25 °C

Rev.2.00 Jun 21, 2004 -0.3 -0.2 -0.1 0.1 0.2 0.3 012345 Fig. 3.2.74 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 8 MHz in high-speed mode: One Time PROM version) Measuring condition: f(XIN) = 8 MHz in high-speed mode, VCC = 5.0 V, Ta = 25 °C (same characteristics pins: P20–P2 7) Input current II(AD) [ µA] Input voltage VIN [V] Fig. 3.2.75 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 6 MHz in double-speed mode: One Time PROM version) Measuring condition: f(XIN) = 6 MHz in double-speed mode, VCC = 5.0 V, Ta = 25 °C (same characteristics pins: P20–P2 7) Input current II(AD) [ µA] Input voltage VIN [V] Fig. 3.2.76 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 4 MHz in double-speed mode: One Time PROM version) Measuring condition: f(XIN) = 4 MHz in double-speed mode, VCC = 5.0 V, Ta = 25 °C (same characteristics pins: P20–P2 7) Input current II(AD) [ µA] (8) Port typical characteristic example (VIN-II(AD) characteristics) Input voltage VIN [V] -0.3 -0.2 -0.1 0.1 0.2 0.3 012345 -0.3 -0.2 -0.1 0.1 0.2 0.3 012345

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics -60 -40 -20 0 20 40 60 80 100 120 140 23456 Fig. 3.2.77 VCC -ROSC characteristics (on-chip oscillator frequency: One Time PROM version) Measuring parameter: On-chip oscillator frequency On-chip oscillator frequency R OSC [MHz] Power source voltage Vcc [V] Fig. 3.2.78 Ta-ROSC characteristics (on-chip oscillator frequency: One Time PROM version) Measuring parameter: On-chip oscillator frequency On-chip oscillator frequency R OSC [MHz] Operating temperature range Ta [°C] (9) On-chip oscillator frequency typical characteristic example Ta = –25 °C Ta = 130 °C Ta = –45 °C Ta = 90 °C Ta = 25 °C V CC = 5.0 V V CC = 3.0 V

Rev.2.00 Jun 21, 2004 Fig. 3.2.79 R-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) Measuring parameter: RC oscillation frequency Measuring condition: VCC = 5.0 V, Ta = 25 °C RC oscillation frequency f(X IN ) [MHz] External resistor R [kΩ ] Fig. 3.2.80 C-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) Measuring parameter: RC oscillation frequency Measuring condition: VCC = 5.0 V, Ta = 25 °C RC oscillation frequency f(X IN ) [MHz] External capacitor C [pF] (10) RC oscillation frequency typical characteristic example 0 1 02 03 04 05 0 C = 33 pF C = 20 pF C = 47 pF R = 5.1 kΩ R = 10 kΩ R = 15 kΩ

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics 4.0 4.2 4.4 4.6 4.8 5.0 -60 -30 0 30 60 90 120 150 0.0 1.0 2.0 3.0 4.0 5.0 23456 Fig. 3.2.81 VCC -f(XIN) characteristics (RC oscillation frequency: One Time PROM version) Measuring parameter: RC oscillation frequency Measuring condition: Ta = 25 °C, R = 5.1 kΩ /C = 33 pF RC oscillation frequency f(X IN ) [MHz] Power source voltage VCC [V] Fig. 3.2.82 Ta-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) Measuring parameter: RC oscillation frequency Measuring condition: R = 5.1 kΩ , C = 33 pF RC oscillation frequency f(X IN ) [MHz] Operating temperature range Ta [°C] V CC = 5.0 V V CC = 3.0 V

Rev.2.00 Jun 21, 2004 (11) A/D conversion typical characteristics example ➀ Definition of A/D conversion accuracy The A/D conversion accuracy is defined below (refer to Fig. 3.2.83). G Relative accuracy

• Zero transition voltage (VOT ) This means an analog input voltage when the actual A/D conversion output data changes from “0” to “1.”
• Full-scale transition voltage (VFST ) This means an analog input voltage when the actual A/D conversion output data changes from “1023” to “1022.”
• Non-linearity error This means a deviation from the line between VOT and VFST of a converted value between VOT and V FST .
• Differential non-linearity error This means a deviation from the input potential difference required to change a converted value between V OT and VFST by 1 LSB of the 1 LSB at the relative accuracy. G Absolute accuracy This means a deviation from the ideal characteristics between 0 to VREF of actual A/D conversion characteristics. V REF 1024 Fig. 3.2.83 Definition of A/D conversion accuracy Vn: Analog input voltage when the output data changes from “n” to “n + 1” (n = 0 to 1022)
• 1 LSB at relative accuracy → (V)
• 1 LSB at absolute accuracy → (V) V FST – VOT 1022 Analog voltageVR E FV1 2VnV1V0 Z e r o t r a n s i t i o n v o l t a g e ( V0 Full-scale transition voltage (VFST ) N o n - l i n e a r i t y e r r o r = Actual A/D conversion characteristics Vn n+1 n 1022 I d e a l l i n e o f A / D c o n v e r s i o n b e t w e e n t o Output data b a a : 1 L S B a t r e l a t i v e a c c u r a c y b Vn Vn c D i f f e r e n c e b e t w e e n t h e i d e a l V n a n d a c t u a l V n Differential non-linearity error=b-a a [LSB] c c a [LSB]

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics -10 0 32 64 96 128 160 192 224 256 -10 256 288 320 352 384 416 448 480 512 -10 512 544 576 608 640 672 704 736 768 -10 768 800 832 864 896 928 960 992 1024 Fig. 3.2.84 A/D conversion accuracy typical characteristic example-1 (One Time PROM version)

• VCC = 5.12 [V]
• VREF = 5.12 [V]
• XIN = 4 [MHz]
• Temp. = 25 [°C]
• CPU mode = double-speed mode
• Zero transition voltage: 6.88 mV
• Full-scale transition voltage: 5115.63 mV
• Differential non-linearity error: –2.34 mV (–0.47 LSB)
• Non-linearity error: –5.66 mV (–1.13 LSB) M37540E8FP A/D CONVERTER STEP WIDTH MEASUREMENT Reference(ERROR(ABSOLUTE)) ERROR/1LSB WIDTH [mV] ERROR (LINEARITY) 1LSB WIDTH ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ➁ A/D conversion accuracy typical characteristics-1

Rev.2.00 Jun 21, 2004 -10 0 32 64 96 128 160 192 224 256 -10 256 288 320 352 384 416 448 480 512 -10 512 544 576 608 640 672 704 736 768 -10 768 800 832 864 896 928 960 992 1024 Fig. 3.2.85 A/D conversion accuracy typical characteristic example-2 (One Time PROM version)

• VCC = 5.12 [V]
• VREF = 5.12 [V]
• XIN = 6 [MHz]
• Temp. = 25 [°C]
• CPU mode = double-speed mode
• Zero transition voltage: 5.94 mV
• Full-scale transition voltage: 5113.44 mV
• Differential non-linearity error: 3.28 mV (0.66 LSB)
• Non-linearity error: –4.91 mV (–0.98 LSB) M37540E8FP A/D CONVERTER STEP WIDTH MEASUREMENT Reference(ERROR(ABSOLUTE)) ERROR/1LSB WIDTH [mV] ERROR (LINEARITY) 1LSB WIDTH ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ➂ A/D conversion accuracy typical characteristics-2

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.2 Typical characteristics -10 0 32 64 96 128 160 192 224 256 -10 256 288 320 352 384 416 448 480 512 -10 512 544 576 608 640 672 704 736 768 -10 768 800 832 864 896 928 960 992 1024 Fig. 3.2.86 A/D conversion accuracy typical characteristic example-3 (One Time PROM version)

• VCC = 5.12 [V]
• VREF = 5.12 [V]
• XIN = 8 [MHz]
• Temp. = 25 [°C]
• CPU mode = high-speed mode
• Zero transition voltage: 5.63 mV
• Full-scale transition voltage: 5115.31 mV
• Differential non-linearity error: –2.66 mV (–0.53 LSB)
• Non-linearity error: –5.99 mV (–1.20 LSB) M37540E8FP A/D CONVERTER STEP WIDTH MEASUREMENT Reference(ERROR(ABSOLUTE)) ERROR/1LSB WIDTH [mV] ERROR (LINEARITY) 1LSB WIDTH ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ERROR/1LSB WIDTH [mV] ➃ A/D conversion accuracy typical characteristics-3

Rev.2.00 Jun 21, 2004

3.3.1 Notes on input and output ports

Notes on using input and output ports are described below. (1) Notes in stand-by state In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O port “undefined”. Pull-up (connect the port to V CC ) or pull-down (connect the port to VSS ) these ports through a resistor. When determining a resistance value, note the following points:

• External circuit
• Variation of output levels during the ordinary operation When using a built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external. G Reason The output transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes “undefined” depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an I/O port are “undefined”. This may cause power source current. 1 stand-by state : the stop mode by executing the STP instruction the wait mode by executing the WIT instruction (2) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the unspecified bit may be changed. G Reason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port : The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port : The bit value of the port latch is read in the CPU, and is written to this bit after bit managing. Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. 2 bit managing instructions : SEB , and CLB instructions (3) Usage for the 32-pin version ➀ Fix the P35, P36 pull-up control bit of the pull-up control register to “1”. ➁ Keep the P36/INT1 input level selection bit of the port P1P3 control register “0” (initial state).

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.3 Notes on use

3.3.2 Termination of unused pins

(1) Terminate unused pins ➀ I/O ports :

• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of 1 kΩ to 10 kΩ . Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/ O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) Termination remarks ➀ Input ports and I/O ports : Do not open in the input mode. G Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and ➂ shown on the above. ➁ I/O ports : When setting for the input mode, do not connect to V CC or VSS directly. G Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and VCC (or VSS ). ➂ I/O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. G Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins.

Rev.2.00 Jun 21, 2004

3.3.3 Notes on Timer

• When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
• When a count source of timer X, timer Y or timer Z is switched, stop a count of timer X.

3.3.4 Notes on Timer A

Notes on using timer A are described below. (1) Common to all modes ➀ When reading timer A (high-order) (TAH) and timer A (low-order) (TAL), the contents of timer A is read out. Read both registers in order of TAH and TAL following, certainly. TAH and TAL keep the values until they are read out. Also, do not write to them during read. In this case, unexpected operation may occur. ➁ When writing data to TAL and TAH even when timer A is operating or stopped, the data are set to timer A and timer A latch simultaneously. Write both registers in order of TAL and TAH following, certainly. Also, do not read them during write. In this case, unexpected operation may occur. (2) Period measurement mode, event counter mode, and pulse width HL continuously measurement mode ➀ In order to use CNTR 1 pin, set “0” to bit 0 of the port P0 direction register (input mode). ➁ In order to use CNTR1 pin, set “1” to bit 7 of the interrupt control register to disable the P00 key- on wakeup function. ➂ CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. When this bit is “0”, the CNTR 1 interrupt request bit is set to “1” at the falling edge of the CNTR1 pin input signal. When this bit is “1”, the CNTR1 interrupt request bit is set to “1” at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR 1 active edge switch bit.

3.3.5 Notes on timer 1

Note on timer 1 is described below. (1) Notes on set of the oscillation stabilizing time Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/ “not set automatically” by the oscillation stabilizing time set bit after release of the STP instruction of MISRG. When “0” is set to this bit, “0116” is set to timer 1 and “FF16” is set to prescaler 1 automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.3 Notes on use

3.3.6 Notes on Timer X

Notes on using each mode of timer X are described below. (1) Count source ➀ f(XIN) can be used only when a ceramic oscillator or an on-chip oscillator is used. Do not use f(XIN) at RC oscillation. (2) Pulse output mode ➀ In order to use CNTR0 pin, set “1” to bit 4 of the port P1 direction register (output mode). ➁ In order to use TXOUT pin, set “1” to bit 3 of the port P0 direction register (output mode). ➂ CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is “0”, the CNTR 0 interrupt request bit is set to “1” at the falling edge of CNTR0 pin input signal. When this bit is “1”, the CNTR0 interrupt request bit is set to “1” at the rising edge of CNTR0 pin input signal. (3) Pulse width measurement mode ➀ In order to use CNTR0 pin, set “1” to bit 4 of the port P1 direction register (output mode). ➁ CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is “0”, the CNTR 0 interrupt request bit is set to “1” at the falling edge of CNTR0 pin input signal. When this bit is “1”, the CNTR0 interrupt request bit is set to “1” at the rising edge of CNTR0 pin input signal.

Rev.2.00 Jun 21, 2004

3.3.7 Notes on timer Y and timer Z

Notes on using each mode of Timer Y and Timer Z are described below. (1) Timer mode (timer Y and timer Z) ➀ In the timer mode, TYP and TYS is not used. (2) Programmable waveform generation mode (timer Y and timer Z) ➀ In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again. ➁ In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultaneously. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Y interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary and a secondary setting values, and primary write timing, it may be impossible.) ➂ The waveform extension function by the timer Y waveform extension control bits can be used only when “00 16” is set to Prescaler Y. When the value other than “0016” is set to Prescaler Y, be sure to set “0” to EXPYP and EXPYS. The waveform extension function by the timer Z waveform extension control bits can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. ➃ When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch only”. ➄ When TYS is read out, the undefined value is read out. However, while timer Y counts the setting value of TYS, the count value during the secondary interval can be obtained by reading the timer Y primary. ➅ In order to use TY OUT pin, set “1” to bit 1 of the port P0 direction register (output mode). (3) Programmable one-shot generation mode (timer Z) ➀ In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again. ➁ In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow simultaneously.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.3 Notes on use ➂ The waveform extension function by the timer Z waveform extension control bits can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. An example of a measurement is shown below. ex.) The underflow of timer is stored by polling etc. using timer Z interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT 0 pin, it may be impossible.) ➃ When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. ➄ In order to use TZOUT pin, set “1” to bit 2 of the port P0 direction register (output mode). ➅ Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit. (4) Programmable wait one-shot generation mode (timer Z) ➀ In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Z interrupt. Writing is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT 0 pin, it may be impossible.) ➁ In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultaneously. ➂ The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. ➃ When using this mode, be sure to set “1” to the timer Z write control bits to select “write to latch only”. ➄ When TZS is read out, the undefined value is read out. However, while Timer Z counts the setting value of TZS (during one-shot output), the count value during the secondary interval can be obtained by reading TZP. ➅ In order to use TZ OUT pin, set “1” to bit 2 of the port P0 direction register (output mode). ➆ Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit.

Rev.2.00 Jun 21, 2004 (5) Common to all modes (timer Y and timer Z) Timer Y can stop counting by setting “1” to the timer Y count stop bit in any mode. Also, when Timer Y underflows, the timer Y interrupt request bit is set to “1”. Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.)

3.3.8 Notes on Serial I/O1

Notes on using serial I/O1 are described below. (1) Notes when selecting clock synchronous serial I/O ➀ When the clock synchronous serial I/O1 is used, serial I/O2 cannot be used. ➁ When the transmit operation is stopped, clear the serial I/O1 enable bit and the transmit enable bit to “0” (serial I/O1 and transmit disabled). G Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD 1, RxD1, SCLK1 , and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD 1 pin and an operation failure occurs. ➂ When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0” (serial I/O1 disabled). ➃ When the transmit/receive operation is stopped, clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) simultaneously. (any one of data transmission and reception cannot be stopped.) G Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit cannot be initialized even if the serial I/O1 enable bit is cleared to “0” (serial I/O1 disabled) (same as ➁ ). ➄ When signals are output from the S RDY1 pin on the reception side by using an external clock, set all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to “1”. ➅ When the SRDY1 signal input is used, set the using pin to the input mode before data is written to the transmit/receive buffer register. ➆ Setup of a serial I/O1 synchronous clock selection bit when a clock synchronous serial I/O is selected; “0” : P12 pin turns into an output pin of a synchronous clock. “1” : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY1 ) when a clock synchronous serial I/O1 is selected; “0” : P13 pin can be used as a normal I/O pin. “1” : P13 pin turns into a SRDY1 output pin.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.3 Notes on use (2) Notes when selecting UART ➀ When the clock asynchronous serial I/O1 (UART) is used, serial I/O2 can be used only when BRG output divided by 16 is selected as the synchronous clock. ➁ When the transmit operation is stopped, clear the transmit enable bit to “0” (transmit disabled). G Reason Same as (1) ➁ . ➂ When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled). ➃ When the transmit/receive operation is stopped, clear the transmit enable bit to “0” (transmit disabled) and receive enable bit to “0” (receive disabled). ➄ Setup of a serial I/O1 synchronous clock selection bit when a clock asynchronous (UART) serial I/O is selected; “0”: P12 pin can be used as a normal I/O pin. “1”: P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. (3) Notes common to clock synchronous serial I/O and UART ➂ When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set “1” to the transmit enable bit while the SCLK1 is “H” state. Also, write to the transmit buffer register while the SCLK1 is “H” state. ➃ When the transmit interrupt is used, set as the following sequence. ❶ Serial I/O1 transmit interrupt enable bit is set to “0” (disabled). ❷ Serial I/O1 transmit enable bit is set to “1”. ❸ Serial I/O1 transmit interrupt request bit is set to “0”. ❹ Serial I/O1 transmit interrupt enable bit is set to “1” (enabled). G Reason When the transmit enable bit is set to “1”, the transmit buffer empty flag and transmit shift completion flag are set to “1”. Accordingly, even if the timing when any of the above flags is set to “1” is selected for the transmit interrupt source, interrupt request occurs and the transmit interrupt request bit is set. ➄ Write to the baud rate generator (BRG) while the transmit/receive operation is stopped. Fig. 3.3.1 Sequence of setting serial I/O1 control register again ➀ Set the serial I/O control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0.” ➁ The transmit shift completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. Can be set with the LDM instruction at the same time Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1”

Rev.2.00 Jun 21, 2004

3.3.9 Notes on serial I/O2

Notes on using serial I/O2 are described below. (1) Note on serial I/O1 Serial I/O2 can be used only when serial I/O1 is not used or serial I/O1 is used as UART and the BRG output divided by 16 is selected as the synchronous clock. (2) Note on SCLK2 pin When an external clock is selected, set “0” to bit 2 of the port P1 direction register (input mode). (3) Note on SDATA2 pin When P1 3/SRDY1 /SDATA2 pin is used as the SDATA input, set “0” to bit 3 of the port P1 direction register (input mode). When the internal clock is selected as the transfer and P13/SDATA2 pin is set to the input mode, the S DATA2 pin is in a high-impedance state after the data transfer is completed. (4) Notes on serial I/O2 transmit/receive shift completion flag ➀ The transmit/receive shift completion flag of the serial I/O2 control register is “1” after transmit/ receive shift is completed. In order to set “0” to this flag, set data (dummy data at receive) to the serial I/O2 register by program. ➁ Bit 7 (transmit/receive shift completion flag) of the serial I/O2 control register is set earlier than the completion of the actual shift operation for a half cycle of shift clock. Accordingly, when the shift completion is checked by using this bit, read/write the serial I/O2 register after a half or more cycle of clock from the setting “1” to this bit is checked.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.3 Notes on use

3.3.10 Notes on A/D converter

Notes on A/D converter are described below. (1) Analog input pin Figure 3.3.2 shows the internal equivalent circuit of an analog input. In order to execute the A/D conversion correctly, to complete the charge to an internal capacitor within the specified time is required. The maximum output impedance of the analog input source required to complete the charge to a capacitor within the specified time is as follows; About 35 kΩ (at f(X IN) = 8 MHz) When the maximum output impedance exceeds the above value, equip an analog input pin with an external capacitor of 0.01µF to 1µF between an analog input pin and VSS . Further, be sure to verify the operation of application products on the user side. G Reason An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion/comparison precision to be worse. (2) Clock frequency during A/D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A/D conversion.

• f(X IN) is 500 kHz or more
• Do not execute the STP instruction (3) Note on A/D converter As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value. (2) When VREF voltage is lower than [3.0 V], the accuracy at the low temperature may become extremely low compared with that at room temperature When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. Fig. 3.3.2 Connection diagram ANi (i=0 to 7: 36-pin version i=0 to 5: 32-pin version) 12 pF(Typical) Notes 1: This is a parasitic diode. 2: Only the selected analog input pin is turned on. 1.5 pF(Typical) Chopper Amp. A/D control circuit Typical voltage generation circuit Switch tree, ladder resistor 1.5 kΩ (Typical) V SS VSS VCC VSS VREF R (Note 1) SW1 (Note 2) (Note 1)

Rev.2.00 Jun 21, 2004

3.3.11 Notes on oscillation stop detection circuit

Notes on using oscillation stop detection circuit are described below. (1) Note on on-chip oscillator ➀ The 7540 Group starts operation by the on-chip oscillator. ➁ On-chip oscillator operation The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Notes on oscillation circuit stop detection circuit ➀ When the stop mode is used, set the oscillation stop detection function to “invalid”. ➁ When f(XIN) oscillation is stopped, set the oscillation stop detection function to “invalid”. ➂ The oscillation stop detection circuit is not included in the emulator MCU “M37540RSS”. (3) Notes on stop mode ➀ When the stop mode is used, set the oscillation stop detection function to “invalid”. ➁ When the stop mode is used, set “0” (STP instruction enabled) to the STP instruction disable bit of the watchdog timer control register. ➂ Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/ “not set automatically” by the oscillation stabilizing time set bit after release of the STP instruction of MISRG. When “0” is set to this bit, “0116” is set to timer 1 and “FF16” is set to prescaler 1 automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. ➃ The STP instruction cannot be used during CPU is operating by the on-chip oscillator. ➄ When the stop mode is used, stop the on-chip oscillator oscillation. ➅ Do not execute the STP instruction during the A/D conversion. (4) Note on wait mode ➀ When the wait mode is used, stop the clock except the operation clock source. (5) Notes on state transition ➀ When the operation clock source is f(XIN), the CPU clock division ratio can be selected from the following;

• f(XIN)/2 (high-speed mode)
• f(XIN)/8 (middle-speed mode)
• f(XIN) (double-speed mode) The double-speed mode can be used only at ceramic oscillation. Do not use the mode at RC oscillation. ➁ Stabilize the f(X IN) oscillation to change the operation clock source from the on-chip oscillator to f(XIN).

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.3 Notes on use ➂ When the on-chip oscillation is used as the operation clock, the CPU clock division ratio is the middle-speed mode. ➃ When the state transition state 2→ state 3→ state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock.

• CPUM 76→ 102 (State 2→ state 3)
• NOP instruction
• CPUM 4→ 12 (State 3→ state 4) Double-speed mode at on-chip oscillator: NOP✕ 3 High-speed mode at on-chip oscillator: NOP✕ 1 Middle-speed mode at on-chip oscillator: NOP✕ 0 (6) Switch of ceramic and RC oscillations After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register. (7) Double-speed mode When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected. (8) Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Figure 3.3.3 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Figure 3.3.3. Fig. 3.3.3 State transition S t o p m o d e Wait mode W I T i n s t r u c t i o n O s c i l l a t i o n s t o p d e t e c t i o n c i r c u i t v a l i d CPUM 4← 12 M I S R G 1← 12 I n t e r r u p t I n t e r r u p t S T P i n s t r u c t i o n WIT instruction I n t e r r u p t M I S R G 1← 02 CPUM 3← 12 CPUM 3← 02 C P U M 7 6← 1 C P U M 7 6← 0 N o t e CPUM 4← 02 M I S R G 1← 12 M I S R G 1← 02 Reset released S t a t e 1 O p e r a t i o n c l o c k s o u r c e f (XI N ) N o t e f (XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r s t o p S t a t e 2 O p e r a t i o n c l o c k s o u r c e f (XI N ) N o t e f (XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r e n a b l e d State 3 Operation clock source: On-chip oscillator (Note 3) f(X IN) oscillation enabled On-chip oscillator enalbed S t a t e 4 O p e r a t i o n c l o c k s o u r c e O n c h i p o s c i l l a t o r N o t e f (XI N ) o s c i l l a t i o n s t o p O n c h i p o s c i l l a t o r e n a l b e d Notes on switch of clock (1) In operation clock source = f(XIN), the following can be selected for the CPU clock division ratio. G f(X IN)/2 (high-speed mode) G f(XIN)/8 (middle-speed mode) G f(XIN) (double-speed mode, only at a ceramic oscillation) (2) Execute the state transition state 3 to state 2 or state 3’ to state 2’ after stabilizing XIN oscillation. (3) In operation clock source = on-chip oscillator, the middle- speed mode is selected for the CPU clock division ratio. (4) When the state transition state 2 → state 3 → state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock.
• CPUM76 → 10 2 (State 2 → state 3)
• NOP instruction
• CPUM4 → 12 (State 3 → state 4) Double-speed mode at on-chip oscillator: NOP ✕ 3 High-speed mode at on-chip oscillator: NOP ✕ 1 Middle-speed mode at on-chip oscillator: NOP ✕ 0 R e s e t s t a t e C P U M 7 6← 1 C P U M 7 6← 0 N o t e S t a t e 2 ’ O p e r a t i o n c l o c k s o u r c e f (XI N ) N o t e f (XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r e n a b l e d S t a t e 3 ’ O p e r a t i o n c l o c k s o u r c e O n c h i p o s c i l l a t o r N o t e f XI N ) o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r e n a l b e d

Rev.2.00 Jun 21, 2004

3.3.12 Notes on CPU mode register

(1) Switching method of CPU mode register after releasing reset Switch the CPU mode register (CPUM) at the head of program after releasing reset in the following method. Fig. 3.3.4 Switching method of CPU mode register (2) CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program run- away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The emulator MCU “M37540RSS” is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. A f t e r r e l e a s i n g r e s e t S w i t c h t h e o s c i l l a t i o n m o d e s e l e c t i o n b i t b i t o f C P U M S w i t c h t h e c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b i t s a n d o f C P U M M a i n r o u t i n e S t a r t w i t h a n o n c h i p o s c i l l a t o r o t A n i n i t i a l v a l u e i s s e t a s a c e r a m i c o s c i l l a t i o n m o d e W h e n i t i s s w i t c h e d t o a n R C o s c i l l a t i o n i t s o s c i l l a t i o n s t a r t s Select 1/1, 1/2, 1/8 or on-chip oscillator. W a i t b y o n c h i p o s c i l l a t o r o p e r a t i o n u n t i l e s t a b l i s h m e n t o f o s c i l l a t o r c l o c k When using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. When using an RC oscillation, wait time is not required basically (time to execute the instruction to switch from an on-chip oscillator meets the requirement). N o t A f t e r r e l e a s i n g r e s e t t h e o p e r a t i o n s t a r t s b y s t a r t i n g a n o n c h i p o s c i l l a t o r a u t o m a t i c a l l y D o n o t u s e a n o n c h i p o s c i l l a t o r a t o r d i n a r y o p e r a t i o n

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.3 Notes on use

3.3.13 Notes on interrupts

(1) Switching external interrupt detection edge For the products able to switch the external interrupt detection edge, switch it as the following sequence. Clear an interrupt enable bit to “0” (interrupt disabled) Switch the detection edge NOP (one or more instructions) Clear an interrupt request bit to “0” (no interrupt request issued) Set the interrupt enable bit to “1” (interrupt enabled) (2) Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to “0” by using a data transfer instruction, execute one or more instructions before executing the BBC or BBS instruction. G Reason If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0” is read. Clear the interrupt request bit to “0” (no interrupt issued) NOP (one or more instructions) Execute the BBC or BBS instruction Data transfer instruction: LDM, LDA, STA, STX, and STY instructions Fig. 3.3.6 Sequence of check of interrupt request bit Fig. 3.3.5 Sequence of switch the detection edge G Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals. This may cause an unnecessary interrupt.

Rev.2.00 Jun 21, 2004 (3) Structure of interrupt control register 2 Fix the bit 7 of the interrupt control register 1 to “0”. Figure 3.3.7 shows the structure of the interrupt control register 2. Fig. 3.3.7 Structure of interrupt control register 2 b7 b0 Interrupt control register 2 (address: 003F16) Interrupt enable bit Not used (fix this bit to “0”) (4) Interrupt When setting the followings, the interrupt request bit may be set to “1”.

• When switching external interrupt active edge Related register: Interrupt edge selection register (address 003A 16) Timer X mode register (address 002B16) Timer A mode register (address 001D16) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit (active edge switch bit). ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled).

3.3.14 Notes on RESET pin

(1) Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following :

• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side. G Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.3 Notes on use

3.3.15 Notes on programming

(1) Processor status register ➀ Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. G Reason After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “1”. Reset Initializing of flags Main program Fig. 3.3.10 Stack memory contents after PHP instruction execution PLP instruction execution NOP ➁ How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. A NOP instruction should be executed after every PLP instruction. Fig. 3.3.8 Initialization of processor status register Fig. 3.3.9 Sequence of PLP instruction execution (S) (S)+1 Stored PS

Rev.2.00 Jun 21, 2004 (2) Decimal calculations ➀ Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC , CLC , or CLD instruction. ➁ Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialized to “1” before each calculation. (3) JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. (4) Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction. (5) Ports

• The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. (6) A/D Conversion Do not execute the STP instruction during A/D conversion. Set D flag to “1” ADC or SBC instruction NOP instruction SEC , CLC , or CLD instruction Fig. 3.3.11 Status flag at decimal calculations

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.3 Notes on use (7) Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock f by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock f is the same as that of the XIN in double-speed mode, twice the X IN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode. (8) CPU Mode Register The oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit. (Emulator MCU is excluded.) When a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. Do not use it when an RC oscillation is selected. Fig. 3.3.12 Programming and testing of One Time PROM version (1) One Time PROM Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 kΩ resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor.

3.3.17 Handling of Power Source Pin

In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF to 0.1 µF is recommended.

3.3.16 Programming and test of built-in PROM version

As for in the One Time PROM version (shipped in blank), its built-in PROM can be read or programmed with a general-purpose PROM programmer using a special programming adapter. The programming test and screening for PROM of the One Time PROM version (shipped in blank) are not performed in the assembly process and the following processes. To ensure reliability after programming, performing programming and test according to the Figure 3.3.12 before actual use are recommended. Programming with PROM programmer Screening (Caution) (150 °C for 40 hours) Verification with PROM programmer Functional check in target device The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Caution:

Rev.2.00 Jun 21, 2004

3.3.18 Notes on built-in PROM version

(1) Programming adapter Use a special programming adapter shown in Table 3.3.1 and a general-purpose PROM programmer when reading from or programming to the built-in PROM in the built-in PROM version. Table 3.3.1 Programming adapters M37540E8GP (One Time PROM version shipped in blank) M37540E8SP (One Time PROM version shipped in blank) M37540E8FP (One Time PROM version shipped in blank) PCA7435GPG03 PCA7435SPG02 PCA7435FPG02 Programming adapterPart Number (2) Programming/reading In PROM mode, operation is the same as that of the M5M27C101AK, but programming conditions of PROM programmer are not set automatically because there are no internal device ID codes. Accurately set the following conditions for data programming /reading. Take care not to apply 21 V to VPP pin (is also used as the CNVSS pin), or the product may be permanently damaged.

• Programming voltage: 12.5 V
• Setting of PROM programmer switch: refer to Table 3.3.2. Part Number PROM programmer start address PROM programmer end address M37540E8GP M37540E8SP M37540E8FP Table 3.3.2 PROM programmer address setting Note: Addersses 808016 to FFFD16 in the built-in PROM corresponds to addresses 0808016 to 0FFFD16 in the PROM programmer. Address 0808016 (Note) Address 0FFFD 16 (Note)

3.3.19 Note on Power Source Voltage

When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.

3.3.20 Electric Characteristic Differences Among Mask ROM and One TIme PROM Version MCUs

There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM and One Time PROM version MCUs due to the differences in the manufacturing processes. When manufacturing an application system with One Time PROM version and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.4 Countermeasures against noise Fig. 3.4.2 Wiring for the RESET pin

3.4 Countermeasures against noise

3.4.1 Shortest wiring length

(1) Package Select the smallest possible package to make the total wiring length short. G Reason The wiring length depends on a microcomputer package. Use of a small package, for example QFP and not DIP, makes the total wiring length short to reduce influence of noise. Fig. 3.4.1 Selection of packages (2) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). G Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. DIP SDIP SOP QFP RESETReset circuit Noise VSSVSS Reset circuit VSS RESET VSS N.G. O.K.

Rev.2.00 Jun 21, 2004 (3) Wiring for clock input/output pins

• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns. G Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. Fig. 3.4.3 Wiring for clock I/O pins (4) Wiring to CNVSS pin Connect the CNV SS pin to the VSS pin with the shortest possible wiring. G Reason The processor mode of a microcomputer is influenced by a potential at the CNVSS pin. If a potential difference is caused by the noise between pins CNVSS and VSS , the processor mode may become unstable. This may cause a microcomputer malfunction or a program runaway. Fig. 3.4.4 Wiring for CNVSS pin Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. Noise CNV SS VSS CNV SS VSS N.G. O.K.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.4 Countermeasures against noise (5) Wiring to VPP pin of One Time PROM version Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the V SS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the V SS pin the shortest possible. Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM version, the microcomputer operates correctly. G Reason The VPP pin of the One Time PROM is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway. Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM

3.4.2 Connection of bypass capacitor across VSS line and VCC line

Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows:

• Connect a bypass capacitor across the VSS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line CNV SS /VPP VSS In the shortest distance Approximately 5kΩ VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines N.G. O.K.

Rev.2.00 Jun 21, 2004

3.4.3 Wiring to analog input pins

• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. G Reason Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. Fig. 3.4.7 Analog signal line and a resistor and a capacitor

3.4.4 Oscillator concerns

Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. G Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. Fig. 3.4.8 Wiring for a large current signal line Analog input pin VSS Noise Thermistor Microcomputer N.G. O.K. (Note) Note : The resistor is used for dividing resistance with a thermistor. XIN XOUT VSS M Microcomputer Mutual inductance Large current GND

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.4 Countermeasures against noise (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. G Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. 3) Oscillator protection using VSS pattern As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns. XIN XOUT VSS CNTRDo not cross N.G. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines XIN XOUT VSS An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the V SS line for oscillation from other VSS lines

3.4.5 Setup for I/O ports

Setup I/O ports using hardware and software as follows: <Hardware>

• Connect a resistor of 100 Ω or more to an I/O port in series. <Software>
• As for an input port, read data several times by a program for checking whether input levels are equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods.
• Rewrite data to direction registers and pull- up control registers at fixed periods. Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse. Fig. 3.4.10 V SS pattern on the underside of an oscillator Fig. 3.4.9 Wiring of signal lines where potential levels change frequently Fig. 3.4.11 Setup for I/O ports Direction register Port latch Data bus I/O port pins Noise Noise N.G. O.K.

Rev.2.00 Jun 21, 2004

3.4.6 Providing of watchdog timer function by software

If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. <The main routine>

• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥≥ (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. <The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. Fig. 3.4.12 Watchdog timer by software Main routine (SWDT) ← N CLI Main processing (SWDT) Interrupt processing routine errors N Interrupt processing routine (SWDT) ← (SWDT)—1 Interrupt processing (SWDT) Main routine errors ≤0 RTI Return =N? ≤0?

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.5 List of registers Fig. 3.5.1 Structure of Port Pi (i = 0, 2, 3) Fig. 3.5.2 Structure of Port P1 Port Pi b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port Pi0 Port Pi1 Port Pi2 Port Pi3 Port Pi4 Port Pi5 Port Pi6 Port Pi7 In output mode Write Read G Port latch In input mode Write : Port latch Read : Value of pins G Port Pi (Pi) (i = 0, 2, 3) [Address : 0016, 0416, 0616] Note: The 32-pin package versions have nothing to be allocated for the following:

• Bits 6 and 7 of port P2
• Bits 5 and 6 of port P3. Port P1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port P10 Port P11 Port P12 Port P13 Port P14 In output mode Write Read G Port latch In input mode Write : Port latch Read : Value of pins G Port P1 (P1) [Address : 0216] Nothing is allocated for these bits. When these bits are read out, the values are undefined.

Rev.2.00 Jun 21, 2004 Fig. 3.5.3 Structure of Port Pi direction register (i = 0, 2, 3) Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port Pi direction register 0 Port Pi direction register (PiD) (i = 0, 2, 3) [Address : 0116, 0516, 0716] 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode Note: The 32-pin package versions have nothing to be allocated for the following:

• Bits 6 and 7 of P2D
• Bits 5 and 6 of P3D. Fig. 3.5.4 Structure of Port P1 direction register Port P1 direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port P1 direction register 0 Port P1 direction register (P1D) [Address : 0316] 0 : Port P10 input mode 1 : Port P10 output mode 0 : Port P11 input mode 1 : Port P11 output mode 0 : Port P12 input mode 1 : Port P12 output mode 0 : Port P13 input mode 1 : Port P13 output mode 0 : Port P14 input mode 1 : Port P14 output mode Nothing is allocated for these bits. When these bits are read out, the values are undefined.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.5 List of registers Fig. 3.5.5 Structure of Pull-up control register Fig. 3.5.6 Structure of Port P1P3 control register P u l l - u p c o n t r o l r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 B Function A t r e s e t RW Name P 00 p u l l - u p c o n t r o l b i t 0 P u l l - u p c o n t r o l r e g i s t e r ( P U L L ) [ A d d r e s s : 1 61 0 : Pull-up Off 1 : Pull-up On Note: Pins set to output are disconnected from the pull-up control. P 01 p u l l - u p c o n t r o l b i t 0 : Pull-up Off 1 : Pull-up On P 02, P 03 p u l l - u p c o n t r o l b i t 0 : Pull-up Off 1 : Pull-up On P 04 – P 07 p u l l - u p c o n t r o l b i t 0 : Pull-up Off 1 : Pull-up On P 30 – P 33 p u l l - u p c o n t r o l b i t 0 : Pull-up Off 1 : Pull-up On P 34 p u l l - u p c o n t r o l b i t 0 : Pull-up Off 1 : Pull-up On P 35, P 36 p u l l - u p c o n t r o l b i t 0 : Pull-up Off 1 : Pull-up On P 37 p u l l - u p c o n t r o l b i t 0 : Pull-up Off 1 : Pull-up On Port P1P3 control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name P37/INT0 input level selection bit Port P1P3 control register (P1P3C) [Address : 1716] 0 : CMOS level 1 : TTL level P36/INT1 input level selection bit (Note) 0 : CMOS level 1 : TTL level P10, P12,P13 input level selection bit 0 : CMOS level 1 : TTL level Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Note: Keep setting the P36/INT1 input level selection bit to “0” (initial value) for the 32-pin package version.

Rev.2.00 Jun 21, 2004 Fig. 3.5.7 Structure of Transmit/Receive buffer register Fig. 3.5.8 Structure of Serial I/O1 status register Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Transmit/Receive buffer register (TB/RB) [Address : 1816] The transmission data is written to or the receive data is read out from this buffer register.

• At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read out. Note: The contents of transmit buffer register cannot be read out. The data cannot be written to the receive buffer register. Serial I/O1 status register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Serial I/O1 status register (SIO1STS) [Address : 1916] Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is “1”. Transmit buffer empty flag (TBE) Overrun error flag (OE) 0 : Buffer full 1 : Buffer empty Receive buffer full flag (RBF) Transmit shift register shift completion flag (TSC) Parity error flag (PE) Framing error flag (FE) Summing error flag (SE) 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.5 List of registers Fig. 3.5.9 Structure of Serial I/O1 control register Serial I/O1 control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Serial I/O1 control register (SIO1CON) [Address : 1A16] 0 : f(XIN) 1 : f(XIN)/4 BRG count source selection bit (CSS) 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled Transmit interrupt source selection bit (TIC) Transmit enable bit (TE) Receive enable bit (RE) Serial I/O1 enable bit (SIOE) 0 : Interrupt when transmit buffer has emptied 1 : Interrupt when transmit shift operation is completed 0: Serial I/O1 disabled 1: Serial I/O1 enabled Serial I/O1 synchronous clock selection bit (SCS) When clock synchronous serial I/O is selected; 0: BRG output divided by 4 1: External clock input When UART is selected; 0: BRG output divided by 16 External clock input divided by 16 0SRDY1 output enable bit (SRDY) 0: P13 pin 1: SRDY1 output pin Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Fig. 3.5.10 Structure of UART control register b 7b 6b 5b 4b 3b 2b 1b 0 B Function A t r e s e t RW Name U A R T c o n t r o l r e g i s t e r ( U A R T C O N ) [ A d d r e s s : 1 B1 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “1”. U A R T c o n t r o l r e g i s t e r C h a r a c t e r l e n g t h s e l e c t i o n b i t C H A S P a r i t y e n a b l e b i t P A R E S t o p b i t l e n g t h s e l e c t i o n b i t S T P S P a r i t y s e l e c t i o n b i t P A R S In output mode 0 : CMOS output 1 : N-channel open-drain output 0 : 8 b i t s b i t s 0 : P a r i t y c h e c k i n g d i s a b l e d P a r i t y c h e c k i n g e n a b l e d 0 : 1 s t o p b i t s t o p b i t s 0 : E v e n p a r i t y O d d p a r i t y P11/TxD P-channel output disable bit (POFF)

Rev.2.00 Jun 21, 2004 Fig. 3.5.11 Structure of Baud rate generator Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Baud rate generator (BRG) [Address : 1C16] Set a count value of baud rate generator.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.5 List of registers Fig. 3.5.12 Structure of Timer A mode register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRWName Timer A mode register (TAM) [Address : 1D16] Timer A mode register 00 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode b5 b4 5 0 Timer A operating mode bits CNTR 1 active edge switch bitThe function depends on the operating mode. (Refer to Table 3.5.1) Timer A count stop bit 0 : Count start 1 : Count stop Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer A operating modes Timer mode Period measurement mode Event counter mode Pulse width HL continuously measurement mode CNTR 1 active edge switch bit “0” CNTR 1 interrupt request occurrence: Falling edge ; No influence to timer A count “1” CNTR 1 interrupt request occurrence: Rising edge ; No influence to timer A count “0” Pulse output start: Falling edge period measurement CNTR 1 interrupt request occurrence: Falling edge “1” Pulse output start: Rising edge period measurement CNTR 1 interrupt request occurrence: Rising edge “0” Timer A: Rising edge count CNTR 1 interrupt request occurrence: Falling edge “1” Timer A: Falling edge count CNTR 1 interrupt request occurrence: Rising edge “0” CNTR 1 interrupt request occurrence: Falling edge and rising edge ; No influence to timer A count “1” CNTR 1 interrupt request occurrence: Rising edge and falling edge ; No influence to timer A count Table 3.5.1 CNTR1 active edge switch bit function

Rev.2.00 Jun 21, 2004 Fig. 3.5.13 Structure of Timer A register Fig. 3.5.14 Structure of Timer Y, Z mode register Timer A register (low-order, high-order) b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer A register (low-order, high-order) (TAL, TAH) [Address : 1E16, 1F16]

• Set a count value of timer A.
• The value set in this register is written to both timer A and timer A latch at the same time.
• When this register is read out, the timer A’s count value is read out. Notes 1: Be sure to write to/read out both the low-order of timer A (TAL) and the high- order of timer A (TAH). 2: Read the high-order of timer A (TAH) first, and the high-order of timer A (TAL) next. 3: Write to the low-order of timer A (TAL) first, and the high-order of timer A (TAH) next. 4: Do not write to them during read, and do not read out them during write. Timer Y, Z mode register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is “0”. Timer Y, Z mode register (TYZM) [Address : 2016) Timer Y operating mode bit 0 : Timer mode 1 : Programmable waveform generation mode Timer Y write control bit (Note) 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Y count stop bit 0 : Count start 1 : Count stop Timer Z operating mode bitsb5 b4 0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode Timer Z write control bit (Note) 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Z count stop bit 0 : Count start 1 : Count stop Note: When modes other than the timer mode, set these bits to “1”.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.5 List of registers Fig. 3.5.15 Structure of Prescaler Y, Prescaler Z Fig. 3.5.16 Structure of Timer Y secondary, Timer Z secondary Prescaler Y, Prescaler Z b 7b 6b 5b 4b 3b 2b 1b 0 B F u n c t i o n A t r e s e t RW P r e s c a l e r Y ( P R E Y ) [ A d d r e s s : 2 11 P r e s c a l e r Z P R E Z A d d r e s s

• Set a count value of each prescaler.
• While the corresponding timer is stopped, the value set in this register is written to both prescaler and the corresponding prescaler latch at the same time.
• While the corresponding timer is operating, the value set in this register is written to as follows; When the timer write control bit is “0”, the value is written to prescaler latch and prescaler at the same time. When the timer write control bit is “1”, the value is written to prescaler latch only.
• When this register is read out, the count value of the corresponding prescaler is read out. Timer Y secondary, Timer Z secondary b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer Y secondary, Timer Z secondary (TYS, TZS) [Address : 2216, 2616]
• Set a count value of the corresponding timer.
• The value set in this register is written to the corresponding secondary latch at the same time.
• These are read disabled bits. When these bits are read out, the values are undefined.

Rev.2.00 Jun 21, 2004 Fig. 3.5.18 Structure of Timer Y, Z waveform output control register Fig. 3.5.17 Structure of Timer Y primary, Timer Z primary b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer Y primary, Timer Z primary Timer Y primary, Timer Z primary (TYP, TZP) [Address : 2316, 2716]

• Set a count value of the corresponding timer.
• When the corresponding timer is stopped, the value set in this register is written to both the corresponding primary latch and the corresponding timer at the same time.
• When the corresponding timer is operating, the value set in this register is written as follows; timer write control bit = 0: the value is written to both the corresponding primary latch and the corresponding timer at the same time. timer write control bit = 1: the value is written to the corresponding primary latch.
• When these bits are read out, the count value of the corres- ponding timer is read out (Note). Note: The primary count value is read out at the primary interval, the secondary count value is read out at the secondary interval. Timer Y, Z waveform output control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Timer Y primary waveform extension control bit Timer Y secondary waveform extension control bit Timer Z output level latch Timer Z primary waveform extension control bit Timer Z secondary waveform extension control bit Timer Y output level latch 0 : Falling edge trigger 1 : Rising edge trigger Timer Y, Z waveform output control register (PUM) [Address : 2416] INT0 pin one-shot trigger control bit (Note) INT0 pin one-shot trigger active edge selection bit (Note) 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : “L” output 1 : “H” output 0 : “L” output 1 : “H” output 0 : INT0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid Note: Stop timer Z to change the values of these bits.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.5 List of registers Fig. 3.5.19 Structure of Prescaler 1 Prescaler 1 b 7b 6b 5b 4b 3b 2b 1b 0 B F u n c t i o n A t r e s e t RW P r e s c a l e r 1 ( P R E 1 ) [ A d d r e s s : 2 81

• Set a count value of prescaler 1.
• The value set in this register is written to both prescaler 1 and the prescaler 1 latch at the same time.
• When this register is read out, the count value of the prescaler 1 is read out. Fig. 3.5.20 Structure of Timer 1 Timer 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer 1 (T1) [Address : 2916]
• S e t a c o u n t v a l u e o f t i m e r 1 . T h e v a l u e s e t i n t h i s r e g i s t e r i s w r i t t e n t o b o t h t i m e r a n d t i m e r l a t c h a t t h e s a m e t i m e W h e n t h i s r e g i s t e r i s r e a d o u t t h e t i m e r s c o u n t v a l u e i s r e a d o u t

Rev.2.00 Jun 21, 2004 Fig. 3.5.21 Structure of One-shot start register One-shot start register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name One-shot start register (ONS) [Address : 2A16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer Z one-shot start bit 0 : One-shot stop 1 : One-shot start

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.5 List of registers Fig. 3.5.22 Structure of Timer X mode register Timer X operating modes Timer mode Pulse output mode Event counter mode Pulse width measurement mode CNTR 0 active edge switch bit (bit 2 of address 2B16) contents “0” CNTR 0 interrupt request occurrence: Falling edge ; No influence to timer count “1” CNTR 0 interrupt request occurrence: Rising edge ; No influence to timer count “0” Pulse output start: Beginning at “H” level CNTR 0 interrupt request occurrence: Falling edge “1” Pulse output start: Beginning at “L” level CNTR 0 interrupt request occurrence: Rising edge “0” Timer X: Rising edge count CNTR 0 interrupt request occurrence: Falling edge “1” Timer X: Falling edge count CNTR 0 interrupt request occurrence: Rising edge “0” Timer X: “H” level width measurement CNTR 0 interrupt request occurrence: Falling edge “1” Timer X: “L” level width measurement CNTR 0 interrupt request occurrence: Rising edge Table 3.5.2 CNTR0 active edge switch bit function b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Timer X mode register (TXM) [Address : 2B16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer X mode register 00 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode b1 b0 1 0 Timer X operating mode bits CNTR 0 active edge switch bitThe function depends on the operating mode. (Refer to Table 3.5.2) Timer X count stop bit 0 : Count start 1 : Count stop 0 : Output invalid (I/O port) 1 : Output valid (Inverted CNTR0 output) P03/TXOUT output valid bit

Rev.2.00 Jun 21, 2004 Fig. 3.5.23 Structure of Prescaler X Fig. 3.5.24 Structure of Timer X Prescaler X b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Prescaler X (PREX) [Address : 2C16]

• Set a count value of prescaler X.
• The value set in this register is written to both prescaler X and the prescaler X latch at the same time.
• When this register is read out, the count value of the prescaler X is read out. Timer X b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer X (TX) [Address : 2D16]
• Set a count value of timer X.
• The value set in this register is written to both timer X and timer X latch at the same time.
• When this register is read out, the timer X’s count value is read out.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.5 List of registers Fig. 3.5.25 Structure of Timer count source set register b 7b 6b 5b 4b 3b 2b 1b 0 BF u n c t i o n A t r e s e t RW N a m e Timer count source set register (TCSS) [Address : 2E16] N o t h i n g i s a l l o c a t e d f o r t h i s b i t . T h i s i s a w r i t e d i s a b l e d b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s T i m e r c o u n t s o u r c e s e t r e g i s t e r Timer X count source selection bits 0b 1 b 0 f XI N ) f XI N ) f XI N ) o t e N o t a v a i l a b l e Timer Y count source selection bits Timer Z count source selection bits Notes 1: f(XIN) can be used as timer X count source only when using a ceramic oscillator or on-chip oscillator. Do not use it at RC oscillation. 2: System operates using an on-chip oscillator as a count source by setting the on-chip oscillator to oscillation enabled by bit 3 of CPUM. F i x t h i s b i t t o “ 0 ” . b 5 b 4 f XI N ) f XI N ) T i m e r Y u n d e r f l o w N o t a v a i l a b l e b3 b2 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : On-chip oscillator output (Note 2) 1 1 : Not available

Rev.2.00 Jun 21, 2004 Fig. 3.5.27 Structure of Serial I/O2 register Fig. 3.5.26 Structure of Serial I/O2 control register b 7b 6b 5b 4b 3b 2b 1b 0 B F u n c t i o n A t r e s e t RW Name S e r i a l I / O 2 c o n t r o l r e g i s t e r ( S I O 2 C O N ) [ A d d r e s s : 3 01 N o t h i n g i s a l l o c a t e d f o r t h i s b i t . T h i s i s a w r i t e d i s a b l e d b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s S e r i a l I O c o n t r o l r e g i s t e r N o t e : W h e n u s i n g i t a s a SD A T A i n p u t , s e t t h e p o r t P 13 d i r e c t i o n r e g i s t e r b i t t o “ 0 ” . 0 : L S B f i r s t M S B f i r s t 0 0 0 : f ( XI N ) / 8 f XI N ) f XI N ) f XI N ) f XI N ) f XI N ) I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s Transfer direction selection bit b2 b1 b0 SD A T A 2 p i n s e l e c t i o n b i t o t 0 : I / O p o r t / SD A T A 2 i n p u t SD A T A o u t p u t SCLK2 pin selection bit 0 : External clock (SCLK2 is input) 1 : Internal clock (SCLK2 is output) T r a n s m i t / r e c e i v e s h i f t c o m p l e t i o n f l a g 0 : s h i f t i n p r o g r e s s s h i f t c o m p l e t e d Serial I/O2 register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Serial I/O2 register (SIO2) [Address : 3116] A shift register for serial transmission and reception.

• At transmitting : Set a transmission data.
• At receiving : A reception data is stored.

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.5 List of registers Fig. 3.5.29 Structure of A/D conversion register (low-order) Fig. 3.5.28 Structure of A/D control register b 7b 6b 5b 4b 3b 2b 1b 0 B Function A t r e s e t RW N a m e A / D c o n t r o l r e g i s t e r ( A D C O N ) [ A d d r e s s : 3 41 N o t h i n g i s a l l o c a t e d f o r t h i s b i t . T h i s i s a w r i t e d i s a b l e d b i t . W h e n t h i s b i t i s r e a d o u t t h e v a l u e i s A / D c o n t r o l r e g i s t e r Note: These can be used only for the 36-pin package versions. 0 0 0 : P20/AN0 0 0 1 : P21/AN1 0 1 0 : P22/AN2 0 1 1 : P23/AN3 1 0 0 : P24/AN4 1 0 1 : P25/AN5 1 1 0 : P26/AN6 (Note) 1 1 1 : P27/AN7 (Note) A n a l o g i n p u t p i n s e l e c t i o n b i t s b 2 b 1 b 0 A D c o n v e r s i o n c o m p l e t i o n b i t 0 : C o n v e r s i o n i n p r o g r e s s C o n v e r s i o n c o m p l e t e d N o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . T h e s e a r e w r i t e d i s a b l e d b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e ✽: T h i s b i t c a n b e c l e a r e d t o “ 0 ” b y p r o g r a m , b u t c a n n o t b e s e t t o “ 1 ” . A / D c o n v e r s i o n r e g i s t e r ( l o w - o r d e r ) b7 b6 b5 b4 b3 b2 b1 b0 B F u n c t i o n At resetRW A/D conversion register (low-order) (ADL) [Address : 3516] T h e r e a d - o n l y r e g i s t e r i n w h i c h t h e A / D c o n v e r s i o n ’ s r e s u l t s a r e s t o r e d < 8-bit read> b 7 b8 b 7b 6b 5b 4b 3 b 0 b 2b 9 < 10-bit read> b 7 b6 b5 b4 b3 b2 b1 b 0 b0b7

Rev.2.00 Jun 21, 2004 Fig. 3.5.31 Structure of MISRG Fig. 3.5.30 Structure of A/D conversion register (high-order) A D c o n v e r s i o n r e g i s t e r h i g h o r d e r b 7b 6b 5b 4b 3b 2b 1b 0 B Function At resetRW A/D conversion register (high-order) (ADH) [Address : 3616] The read-only register in which the A/D conversion’s results are stored. < 10-bit read> b 7 N o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . T h e s e a r e w r i t e d i s a b l e d b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e b7 b6 b5 b4 b3 b2 b1 b0 B Function A t r e s e t RW Name MISRG [Address : 3816] N o t h i n g i s a l l o c a t e d f o r t h e s e b i t s . T h e s e a r e w r i t e d i s a b l e d b i t s . W h e n t h e s e b i t s a r e r e a d o u t t h e v a l u e s a r e M I S R G O s c i l l a t i o n s t a b i l i z a t i o n t i m e s e t b i t a f t e r r e l e a s e o f t h e S T P i n s t r u c t i o n 00 : S e t “ 0 11 6” i n t i m e r 1 , a n d F i n p r e s c a l e r a u t o m a t i c a l l y N o t s e t a u t o m a t i c a l l y T h e s e a r e r e s e r v e d b i t s . D o n o t w r i t e t o t h e s e b i t s (Note) ✕0 : O s c i l l a t i o n s t o p n o t d e t e c t e d O s c i l l a t i o n s t o p d e t e c t e d C e r a m i c o r R C o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n a c t i v e b i t 0 : D e t e c t i o n f u n c t i o n i n a c t i v e D e t e c t i o n f u n c t i o n a c t i v e Oscillation stop detection status bit N o t e : “ 0 ” a t n o r m a l r e s e t a t r e s e t b y d e t e c t i n g t h e o s c i l l a t i o n s t o p

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.5 List of registers Fig. 3.5.33 Structure of Interrupt edge selection register Fig. 3.5.32 Structure of Watchdog timer control register Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Watchdog timer control register (WDTCON) [Address : 3916] Watchdog timer H (The high-order 6 bits are read-only bits.) STP instruction disable bit0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(XIN)/16 Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt edge selection register (INTEDGE) [Address : 3A16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. INT0 interrupt edge selection bit INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled

Rev.2.00 Jun 21, 2004 Fig. 3.5.34 Structure of CPU mode register b 7b 6b 5b 4b 3b 2b 1b 0 B F u n c t i o n A t r e s e t RW Name CPU mode register (CPUM) [Address : 3B16] C P U m o d e r e g i s t e r 00 0 : Single-chip mode 0 1 : Not available 1 0 : Not available 1 1 : Not available b1 b0 1 0 Processor mode bits (Note 1) 0 : Ceramic oscillation 1 : RC oscillation 0 : 0 p a g e p a g e S t a c k p a g e s e l e c t i o n b i t O s c i l l a t i o n m o d e s e l e c t i o n b i t o t e C l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s 0 0 : φ = f ( XI N ) / 2 h i g h s p e e d m o d e φ f XI N ) m i d d l e s p e e d m o d e A p p l i e d f r o m o n c h i p o s c i l l a t o r φ f XI N ) d o u b l e s p e e d m o d e o t e b7 b6 0 : C e r a m i c o r R C o s c i l l a t i o n e n a b l e d C e r a m i c o r R C o s c i l l a t i o n s t o p Notes 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU “M37540RSS”.) 2: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected. O n - c h i p o s c i l l a t o r o s c i l l a t i o n c o n t r o l b i t 0 : O n c h i p o s c i l l a t o r o s c i l l a t i o n e n a b l e d O n c h i p o s c i l l a t o r o s c i l l a t i o n s t o p XIN oscillation control bit

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.5 List of registers Fig. 3.5.36 Structure of Interrupt request register 2 Fig. 3.5.35 Structure of Interrupt request register 1 Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 1 (IREQ1) [Address : 3C16] Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued CNTR 0 interrupt request bit CNTR 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued INT0 interrupt request bit INT1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Key-on wake up interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Timer X interrupt request bit0 : No interrupt request issued 1 : Interrupt request issued Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt request register 2 (IREQ2) [Address : 3D16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer Y interrupt request bit Timer Z interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Timer 1 interrupt request bit ✽ : These bits can be cleared to “0” by program, but cannot be set to “1”. 0 : No interrupt request issued 1 : Interrupt request issued Timer A interrupt request bit Serial I/O2 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued AD converter interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued

Rev.2.00 Jun 21, 2004 Fig. 3.5.38 Structure of Interrupt control register 2 Fig. 3.5.37 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 2 (ICON2) [Address : 3F16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. Timer Y interrupt enable bit Timer Z interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Timer 1 interrupt enable bit Timer A interrupt enable bit Serial I/O2 interrupt enable bit AD conversion interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Interrupt control register 1 (ICON1) [Address : 3E16] Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Timer X interrupt enable bit0 : Interrupt disabled 1 : Interrupt enabled

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.6 Package outline SDIP32-P-400-1.78 Weight(g) – 2.2 JEDEC CodeEIAJ Package Code Lead Material Alloy 42/Cu Alloy 32P4B Plastic 32pin 400mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.51 – – –3 . 8– 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 – 1.778 – – 10.16 – 3.0 – – 0° –1 5 ° – – 5.08 e 32 17 161 E ce1 A2A1 b2bb1e LA SEATING PLANE D Recommended LQFP32-P-0707-0.80 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 32P6U-A Plastic 32pin 7✕ 7mm body LQFP 0.1 – – 0.2 – – Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D ––I2 1.0 ––M D ––M E 10°0° 0.1 1.0 0.7 0.2 0.50.3 0.8 6.9 7.0 7.1 6.9 7.0 7.1 8.8 9.0 9.2 8.8 9.0 9.2 0.1750.1250.105 0.450.370.32 1.4 1.7 e Lp 0.45 0.6 0.5 7.4 7.4 0.25 0.75 x Recommended Mount Pad Detail F A E H E H D D 2532 169 M D M E e Fe y b x M A1 A2 L Lp c Recommended

Rev.2.00 Jun 21, 2004 SSOP36-P-450-0.80 Weight(g) JEDEC Code 0.53 Alloy 42 36P2R-A Plastic 36pin 450mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .350 .050 .130 .814 .28 .6311 .30 .271 .02 .40 .150 .015 .48 .80 .9311 .50 .7651 .4311 .42 .50 .20 .215 .68 .2312 .70 .150 b2 – .50 – 0° – 10° e 36 19 181 H E E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F z Z1 Detail G –Z1 0.7 0.85 z b G Recommended

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP O P n# O P n# O P n# O P n# O P n#OP n # 3-122 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.7 Machine instructions When T = 0, this instruction adds the contents M, C, and A; and stores the results in A and C. When T = 1, this instruction adds the contents of M(X), M and C; and stores the results in M(X) and C. When T=1, the contents of A re- main unchanged, but the contents of status flags are changed. M(X) represents the contents of memory where is indicated by X. When T = 0, this instruction transfers the con- tents of A and M to the ALU which performs a bit-wise AND operation and stores the result back in A. When T = 1, this instruction transfers the con- tents M(X) and M to the ALU which performs a bit-wise AND operation and stores the results back in M(X). When T = 1, the contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction shifts the content of A or M by one bit to the left, with bit 0 always being set to 0 and bit 7 of A or M always being contained in This instruction tests the designated bit i of M or A and takes a branch if the bit is 0. The branch address is specified by a relative ad- dress. If the bit is 1, next instruction is executed. This instruction tests the designated bit i of the M or A and takes a branch if the bit is 1. The branch address is specified by a relative ad- dress. If the bit is 0, next instruction is executed. This instruction takes a branch to the ap- pointed address if C is 0. The branch address is specified by a relative address. If C is 1, the next instruction is executed. This instruction takes a branch to the ap- pointed address if C is 1. The branch address is specified by a relative address. If C is 0, the next instruction is executed. This instruction takes a branch to the ap- pointed address when Z is 1. The branch address is specified by a relative address. If Z is 0, the next instruction is executed. This instruction takes a bit-wise logical AND of A and M contents; however, the contents of A and M are not modified. The contents of N, V, Z are changed, but the contents of A, M remain unchanged. This instruction takes a branch to the ap- pointed address when N is 1. The branch address is specified by a relative address. If N is 0, the next instruction is executed. This instruction takes a branch to the ap- pointed address if Z is 0. The branch address is specified by a relative address. If Z is 1, the next instruction is executed. ADC (Note 1) (Note 5) AND (Note 1) ASL BBC (Note 4) BBS (Note 4) BCC (Note 4) BCS (Note 4) BEQ (Note 4) BIT BMI (Note 4) BNE (Note 4) 7 0 C ← ← 0 29 2 2 0A 2 1 03+20i 17+20i 07+20i 06 5 2 25 3 2 65 3 269 2 2 13+20i When T = 0 A ← A + M + C When T = 1 M(X) ← M(X) + M + C When T = 0 A ← A M When T = 1 M(X) ← M(X) M Ai or Mi = 0? Ai or Mi = 1? C = 0? C = 1? Z = 1? A M N = 1? Z = 0? V V V

3.7 Machine instructions

BIT, A, R BIT, ZP, R

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-123 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 N N N M V M Z Z Z Z C C

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP O P n# O P n# O P n# O P n# O P n#OP n # 3-124 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.7 Machine instructions This instruction takes a branch to the ap- pointed address if N is 0. The branch address is specified by a relative address. If N is 1, the next instruction is executed. This instruction branches to the appointed ad- dress. The branch address is specified by a relative address. When the BRK instruction is executed, the CPU pushes the current PC contents onto the stack. The BADRS designated in the interrupt vector table is stored into the PC. This instruction takes a branch to the ap- pointed address if V is 0. The branch address is specified by a relative address. If V is 1, the next instruction is executed. This instruction takes a branch to the ap- pointed address when V is 1. The branch address is specified by a relative address. When V is 0, the next instruction is executed. This instruction clears the designated bit i of A or M. This instruction clears C. This instruction clears D. This instruction clears I. This instruction clears T. This instruction clears V. When T = 0, this instruction subtracts the con- tents of M from the contents of A. The result is not stored and the contents of A or M are not modified. When T = 1, the CMP subtracts the contents of M from the contents of M(X). The result is not stored and the contents of X, M, and A are not modified. M(X) represents the contents of memory where is indicated by X. This instruction takes the one’s complement of the contents of M and stores the result in M. This instruction subtracts the contents of M from the contents of X. The result is not stored and the contents of X and M are not modified. This instruction subtracts the contents of M from the contents of Y. The result is not stored and the contents of Y and M are not modified. This instruction subtracts 1 from the contents of A or M. BPL (Note 4) BRA BRK BVC (Note 4) BVS (Note 4) CLB CLC CLD CLI CLT CLV CMP (Note 3) COM CPX CPY DEC N = 0? PC ← PC ± offset B ← 1 (PC) ← (PC) + 2 M(S) ← PC H S ← S – 1 M(S) ← PCL S ← S – 1 M(S) ← PS S ← S – 1 I← 1 PC L ← ADL PC H ← ADH V = 0? V = 1? Ai or Mi ← 0 C ← 0 D ← 0 I ← 0 T ← 0 V ← 0 When T = 0 A – M When T = 1 M(X) – M M ← M X – M Y – M A ← A – 1 or M ← M – 1 1A 2 1 1B+20i 1F+20i 21 52 00 7 1

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-125 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 N N N N N DD DE D9 5 3 C1 6 2 D1 6 2 Z Z Z Z Z C C C

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP O P n# O P n# O P n# O P n# O P n#OP n # 3-126 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.7 Machine instructions This instruction subtracts one from the current contents of X. This instruction subtracts one from the current contents of Y. This instruction divides the 16-bit data in M(zz+(X)) (low-order byte) and M(zz+(X)+1) (high-order byte) by the contents of A. The quotient is stored in A and the one's comple- ment of the remainder is pushed onto the stack. When T = 0, this instruction transfers the con- tents of the M and A to the ALU which performs a bit-wise Exclusive OR, and stores the result in A. When T = 1, the contents of M(X) and M are transferred to the ALU, which performs a bit- wise Exclusive OR and stores the results in M(X). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction adds one to the contents of A or M. This instruction adds one to the contents of X. This instruction adds one to the contents of Y. This instruction jumps to the address desig- nated by the following three addressing modes: Absolute Indirect Absolute Zero Page Indirect Absolute This instruction stores the contents of the PC in the stack, then jumps to the address desig- nated by the following addressing modes: Absolute Special Page Zero Page Indirect Absolute When T = 0, this instruction transfers the con- tents of M to A. When T = 1, this instruction transfers the con- tents of M to (M(X)). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction loads the immediate value in This instruction loads the contents of M in X. This instruction loads the contents of M in Y. DEX DEY DIV EOR (Note 1) INC INX INY JMP JSR LDA (Note 2) LDM LDX LDY X ← X – 1 Y ← Y – 1 A ← (M(zz + X + 1), M(zz + X )) / A M(S) ← one's comple- ment of Remainder S ← S – 1 When T = 0 A ← A V– M When T = 1 M(X) ← M(X) V– M A ← A + 1 or M ← M + 1 X ← X + 1 Y ← Y + 1 If addressing mode is ABS PC L ← ADL PC H ← ADH If addressing mode is IND PC L ← M (ADH , ADL) PC H ← M (ADH , ADL + 1) If addressing mode is ZP, IND PC L ← M(00, ADL) PC H ← M(00, ADL + 1) M(S) ← PCH S ← S – 1 M(S) ← PCL S ← S – 1 After executing the above, if addressing mode is ABS, PC L ← ADL PC H ← ADH if addressing mode is SP, PC L ← ADL PC H ← FF If addressing mode is ZP, IND, PC L ← M(00, ADL) PC H ← M(00, ADL + 1) When T = 0 A ← M When T = 1 M(X) ← M M ← nn X ← M Y ← M 3A 21 CA 49 22

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-127 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 N N N N N N N N N Z Z Z Z Z Z Z Z Z 41 6 2 51 6 2 AD AE AC A14 B6 4 2 BD BC BE

53 B 2

62 B 1 62

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP O P n# O P n# O P n# O P n# O P n#OP n # 3-128 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.7 Machine instructions This instruction shifts either A or M one bit to the right such that bit 7 of the result always is set to 0, and the bit 0 is stored in C. This instruction multiply Accumulator with the memory specified by the Zero Page X address mode and stores the high-order byte of the re- sult on the Stack and the low-order byte in A. This instruction adds one to the PC but does no otheroperation. When T = 0, this instruction transfers the con- tents of A and M to the ALU which performs a bit-wise “OR”, and stores the result in A. When T = 1, this instruction transfers the con- tents of M(X) and the M to the ALU which performs a bit-wise OR, and stores the result in M(X). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction pushes the contents of A to the memory location designated by S, and decrements the contents of S by one. This instruction pushes the contents of PS to the memory location designated by S and dec- rements the contents of S by one. This instruction increments S by one and stores the contents of the memory designated by S in A. This instruction increments S by one and stores the contents of the memory location designated by S in PS. This instruction shifts either A or M one bit left through C. C is stored in bit 0 and bit 7 is stored in C. This instruction shifts either A or M one bit right through C. C is stored in bit 7 and bit 0 is stored in C. This instruction rotates 4 bits of the M content to the right. This instruction increments S by one, and stores the contents of the memory location designated by S in PS. S is again incremented by one and stores the contents of the memory location designated by S in PC L. S is again incremented by one and stores the contents of memory location designated by S in PCH . This instruction increments S by one and stores the contents of the memory location designated by S in PC L. S is again incremented by one and the contents of the memory location is stored in PCH . PC is incremented by 1. LSR MUL NOP ORA (Note 1) PHA PHP PLA PLP ROL ROR RRF RTI RTS M(S) • A ← A ✽ M(zz + X) S ← S – 1 PC ← PC + 1 When T = 0 A ← A V M When T = 1 M(X) ← M(X) V M M(S) ← A S ← S – 1 M(S) ← PS S ← S – 1 S ← S + 1 A ← M(S) S ← S + 1 PS ← M(S) S ← S + 1 PS ← M(S) S ← S + 1 PC L ← M(S) S ← S + 1 PC H ← M(S) S ← S + 1 PC L ← M(S) S ← S + 1 PC H ← M(S) (PC) ← (PC) + 1 7 0 ← ← C ← 7 0 → → 7 0 C → → 7 0 0→ → C 4A 2 1 EA 2 1 09 2 2

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-129 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 N N N N Z Z Z Z Z C C C 3 19 53 01 6 2 11 6 2 (Value saved in stack) (Value saved in stack)

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP O P n# O P n# O P n# O P n# O P n#OP n # 3-130 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.7 Machine instructions When T = 0, this instruction subtracts the value of M and the complement of C from A, and stores the results in A and C. When T = 1, the instruction subtracts the con- tents of M and the complement of C from the contents of M(X), and stores the results in M(X) and C. A remain unchanged, but status flag are changed. M(X) represents the contents of memory where is indicated by X. This instruction sets the designated bit i of A or M. This instruction sets C. This instruction set D. This instruction set I. This instruction set T. This instruction stores the contents of A in M. The contents of A does not change. This instruction resets the oscillation control F/ F and the oscillation stops. Reset or interrupt input is needed to wake up from this mode. This instruction stores the contents of X in M. The contents of X does not change. This instruction stores the contents of Y in M. The contents of Y does not change. This instruction stores the contents of A in X. The contents of A does not change. This instruction stores the contents of A in Y. The contents of A does not change. This instruction tests whether the contents of M are “0” or not and modifies the N and Z. This instruction transfers the contents of S in This instruction stores the contents of X in A. This instruction stores the contents of X in S. This instruction stores the contents of Y in A. The WIT instruction stops the internal clock but not the oscillation of the oscillation circuit is not stopped. CPU starts its function after the Timer X over flows (comes to the terminal count). All regis- ters or internal memory contents except Timer X will not change during this mode. (Of course needs VDD). SBC (Note 1) (Note 5) SEB SEC SED SEI SET STA STP STX STY TAX TAY TST TSX TXA TXS TYA WIT When T = 0 A ← A – M – C When T = 1 _ M(X) ← M(X) – M – C Ai or Mi ← 1 C ← 1 D ← 1 I ← 1 T ← 1 M ← A M ← X M ← Y X ← A Y ← A M = 0? X ← S A ← X S ← X A ← Y Notes 1 : The number of cycles “n” is increased by 3 when T is 1. 2 : The number of cycles “n” is increased by 2 when T is 1. 3 : The number of cycles “n” is increased by 1 when T is 1. 4 : The number of cycles “n” is increased by 2 when branching has occurred. 5 : N, V, and Z flags are invalid in decimal operation mode. E9 2 2 0B+20i 0F+20i 21 52 E5 3 2 AA BA

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-131 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 N N N N N N Z Z Z Z Z Z

335 FD4ED24F5 F9 5 3 E1 6 2 F1 6 2

9D 6 3 99 6 3 81 7 2 91 7 2 N V Z C

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.7 Machine instructions Addition Subtraction Multiplication Division Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Zero page address Memory specified by address designation of any ad- dressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by AD H and AD L, in ADH is 8 high-order bits and ADL is 8 low-or- der bits. Contents of address indicated by zero page AD L Bit i (i = 0 to 7) of accumulator Bit i (i = 0 to 7) of memory Opcode Number of cycles Number of bytes Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag IMP IMM A BIT, A BIT, A, R ZP BIT, ZP BIT, ZP, R ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N Symbol Contents Symbol Contents V X Y S PC PS PC H PC L AD H AD L FF nn zz M M(X) M(S) M(AD H , ADL) M(00, ADL) Ai Mi OP n V

Rev.2.00 Jun 21, 2004

3.8 List of instruction code

D 7 – D4 D 3 – D0 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F 0000 BRK BPL JSR ABS BMI RTI BVC RTS BVS BRA BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ 0001 ORA IND, X ORA IND, Y AND IND, X AND IND, Y EOR IND, X EOR IND, Y ADC IND, X ADC IND, Y STA IND, X STA IND, Y LDA IND, X LDA IND, Y CMP IND, X CMP IND, Y SBC IND, X SBC IND, Y 0010 JSR ZP, IND CLT JSR SP SET STP MUL ZP, X RRF ZP LDX IMM JMP ZP, IND WIT DIV ZP, X 0011 BBS 0, A BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A BBC 5, A BBS 6, A BBC 6, A BBS 7, A BBC 7, A 0100 BIT ZP COM ZP TST ZP STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP CPX ZP 0101 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X 0110 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X 0111 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP 1000 PHP CLC PLP SEC PHA CLI PLA SEI DEY TYA TAY CLV INY CLD INX SED 1001 ORA IMM ORA ABS, Y AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y STA ABS, Y LDA IMM LDA ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y 1010 A ASL A DEC A ROL A INC A LSR A ROR A TXA TXS TAX TSX DEX NOP 1011 B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A 1100 C BIT ABS LDM ZP JMP ABS JMP IND STY ABS LDY ABS LDY ABS, X CPY ABS CPX ABS 1101 D ORA ABS ORA ABS, X AND ABS AND ABS, X EOR ABS EOR ABS, X ADC ABS ADC ABS, X STA ABS STA ABS, X LDA ABS LDA ABS, X CMP ABS CMP ABS, X SBC ABS SBC ABS, X 1110 E ASL ABS ASL ABS, X ROL ABS ROL ABS, X LSR ABS LSR ABS, X ROR ABS ROR ABS, X STX ABS LDX ABS LDX ABS, Y DEC ABS DEC ABS, X INC ABS INC ABS, X 1111 F SEB 0, ZP CLB 0, ZP SEB 1, ZP CLB 1, ZP SEB 2, ZP CLB 2, ZP SEB 3, ZP CLB 3, ZP SEB 4, ZP CLB 4, ZP SEB 5, ZP CLB 5, ZP SEB 6, ZP CLB 6, ZP SEB 7, ZP CLB 7, ZP : 3-byte instruction : 2-byte instruction : 1-byte instruction

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.9 SFR memory map P o r t P 0 ( P 0 ) P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D ) P o r t P 1 ( P 1 ) P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D ) P o r t P 2 ( P 2 ) P o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D ) P o r t P 3 ( P 3 ) P o r t P 3 d i r e c t i o n r e g i s t e r ( P 3 D ) Pull-up control register (PULL) T r a n s m i t / R e c e i v e b u f f e r r e g i s t e r ( T B / R B ) Serial I/O1 status register (SIO1STS) S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O 1 C O N ) UART control register (UARTCON) B a u d r a t e g e n e r a t o r ( B R G ) P o r t P 1 P 3 c o n t r o l r e g i s t e r ( P 1 P 3 C ) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 Timer count source set register (TCSS) A/D conversion register (low-order) (ADL) Prescaler 1 (PRE1) Timer 1 (T1) One-shot start register (ONS) Timer X mode register (TXM) Prescaler X (PREX) Timer X (TX) Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2) A/D control register (ADCON) A/D conversion register (high-order) (ADH) MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt control register 1 (ICON1) T i m e r A m o d e r e g i s t e r ( T A M ) T i m e r A ( l o w - o r d e r ) ( T A L ) Timer A (high-order) (TAH) Timer Y, Z mode register (TYZM) Prescaler Y (PREY) Timer Y secondary (TYS) Timer Y primary (TYP) Timer Y, Z waveform output control register (PUM) Prescaler Z (PREZ) Timer Z secondary (TZS) Timer Z primary (TZP) Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2)

Rev.2.00 Jun 21, 2004 Fig. 3.10.1 32P6U-A package pin configuration (Top view) Package type: 32P6U-A P07 P10/RXD 1 P11/TXD 1 P12/SCLK1 /SCLK2 P13/SRDY1 /SDATA2 P14/CNTR 0 P20/AN 0 P21/AN 1 32 P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) VSS XOUT XIN9 2 876531 4 V CC CNV SS RESETP2 2/AN 20 1718192124 2/TZ OUT 3/TX OUT 23 22 1/TY OUT 0/CNTR 7/INT M37540Mx-XXXGP M37540MxT-XXXGP M37540MxV-XXXGP M37540ExGP M37540E8T-XXXGP M37540E8V-XXXGP 3/AN 4/AN 5/AN V REF

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.10 Pin configurations Fig. 3.10.2 36P2R-A package pin configuration (Top view) Package type: 36P2R-A P00/CNTR 1 CNV SS XOUT XIN VSS P01/TYOUT P02/TZOUT P03/TXOUT P04 P30(LED0) Vcc VREF P05 P10/RXD 1 P26/AN6 P27/AN7 P11/TXD 1P12/SCLK1 /SCLK2 P13/SRDY1 /SDATA2 P23/AN3 P22/AN2 P21/AN1 P20/AN0 P31(LED1) P36(LED6)/INT1 P24/AN4 P25/AN5 P06 P07 P37/INT0 RESET M37540Mx-XXXFPM37540MxT-XXXFPM37540MxV-XXXFPM37540E8FPM37540E8T-XXXFPM37540E8V-XXXFP P14/CNTR 0 P35(LED5) P34(LED4) P33(LED3) P32(LED2)

Rev.2.00 Jun 21, 2004 Fig. 3.10.3 32P4B package pin configuration (Top view) CNV SS P12/SCLK1 /SCLK2 P13/SRDY1 /SDATA2 P14/CNTR 0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 VCC XIN XOUT VSS P11/TXD 1 P10/RXD 1 P07 P06 P05 P04 P30(LED0) P25/AN5 VREF RESET P00/CNTR 1 P33(LED3) P32(LED2) P31(LED1) M37540Mx-XXXSPM37540ExSP P01/TYOUT P02/TZOUT P03/TXOUT P37/INT0 P34(LED4) Package type: 32P4B

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.10 Pin configurations Fig. 3.10.4 42S1M package pin configuration (Top view) Outline 42S1M P00/CNTR 1 CNV SS XOUT XIN VSS P01/TYOUT P02/TZOUT P03/TXOUT P04 P30(LED0) Vcc VREF P05 P12/SCLK1 /SCLK2 P25/AN5 P26/AN6 P13/SRDY1 /SDATA2P14/CNTR 0 NC P22/AN2 NC P21/AN1 P20/AN0 P31(LED1) P36(LED6)/INT1 P23/AN3 P24/AN4 P06 P07 P37/INT0 RESET M37540RSS NC P35(LED5) P34(LED4) P33(LED3) P32(LED2) NC P10/RXD 1 P11/TXD 1 NC NC P27/AN7

Rev.2.00 Jun 21, 2004

3.11 Differences between 7540 Group and 7531 Group

Table 3.11.1 shows the differences between 7540 Group and 7531 Group. Table 3.11.1 Differences between 7540 Group and 7531 Group (Performance overview)

7531 Group

Initial value: FF (Ports P0 and P3 pull-up On) 11 sources, 8 vector (3 for external) 12 sources, 8 vector (4 for external) 3 (Timer 1, 2, X) UART only Cecamic oscillator/ Quartz-crystal oscillator/ RC oscillation Parameter Number of basic instructions Memory sizes Input/Output ports Interrupt sources 16-bit timer 8-bit timer Serial I/O1 Clock generation circuit Oscillation stop detection circuit ROM RAM 32-pin version 36-pin version 71 (DIV, MUL instruction added) 16 to 32 K bytes 512 to 768 bytes Initial value: 00 (Ports P0 and P3 pull-up Off) 14 sources, 14 vector (4 for external) 15 sources, 15 vector (5 for external) 1 (Timer A) 3 (Timer 1, X, Y, Z) Clock synchronous/UART Cecamic oscillator/ Quartz-crystal oscillator/ RC oscillation/ On-chip oscillator oscillation

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.11 Differences between 7540 Group and 7531 Group Figure 3.11.1 shows the memory map of 7540 Group and 7531 Group. Fig. 3.11.1 Memory map of 7540 Group and 7531 Group 000016 0 0 4 01 0 0 F F1 PPPP 16 FF0016 F F F E1 FFFF 16 010016 ROM RAM (512/768 bytes) Z e r o p a g e Special page 7 5 4 0 G r o u p 044016 QQQQ 16 RRRR 16 F F D C 1 Address PPPP 16 5 1 2 023F 16 7 6 8 033F 16 Address QQQQ 16 Address RRRR 16

16384 C 0 0 01

6 C080 16

b y t e s N o t u s e d R e s e r v e d a r e a 044016 Reserved ROM area (Common ROM area 128 bytes) Y Y Y Y1 ZZZZ 16 R e s e r v e d R O M a r e a F F E C 1 I n t e r r u p t v e c t o r a r e a ROM R A M a r e a RAM capacity ( b y t e s ) A d d r e s s X X X 256 013F 16 3 8 40 1 B F1 ROM area R O M c a p a c i t y ( b y t e s ) A d d r e s s Y Y Y Address ZZZZ 16 8 1 9 2E 0 0 01

6 E 0 8 01

6 C 0 8 01

(bytes) ROM area R O M c a p a c i t y (bytes) SFR area Not used Reserved area R e s e r v e d R O M a r e a Interrupt vector area Reserved ROM area (Common ROM area 128 bytes)

Rev.2.00 Jun 21, 2004 Figure 3.11.2 shows the memory map of interrupt vector area of 7540 Group and 7531 Group. Fig. 3.11.2 Memory map of interrupt vector area of 7540 Group and 7531 Group FFEB 16 FFEC 16 FFED 16 FFEE 16 FFEA 16 FFEF 16 FFF0 16 FFF1 16 FFF2 16 FFF3 16 FFF4 16 FFF5 16 FFF6 16 FFF7 16 FFF8 16 FFF9 16 FFFA 16 FFFB 16 FFFC 16 FFFD 16 FFE9 16 FFE8 16 F F E C 1 F F E D 1 F F E E1 F F E F1 FFF0 16 FFF1 16 FFF2 16 FFF3 16 FFF4 16 FFF5 16 FFF6 16 F F F 71 F F F 81 F F F 91 F F F A1 F F F B1 F F F C 1 F F F D 1 C N T R 0/ A / D c o n v e r s i o n i n t e r r u p t Timer X/Key-on wakeup interrupt T i m e r 2 / S e r i a l I / O 2 i n t e r r u p t Timer 1 interrupt I N T0 i n t e r r u p t B R K i n s t r u c t i o n i n t e r r u p t R e s e t

7531 Group7540 Group

Serial I/O1 receive interrupt Serial I/O1 transmit/ INT1 (Note) interrupt Note: The interrupt can be used only for the 36-pin version. FFDC 16 FFDD 16 FFDE 16 FFDF 16 FFE0 16 FFE1 16 FFE2 16 FFE3 16 FFE4 16 FFE5 16 FFE6 16 FFE7 16 : Interrupts added in 7540 Group B R K i n s t r u c t i o n i n t e r r u p t Timer 1 interrupt A/D conversion interrupt S e r i a l I / O 2 i n t e r r u p t R e s e t Serial I/O1 receive interrupt Serial I/O1 transmit interrupt INT0 interrupt INT1 interrupt (Note) Key-on wakeup interrupt CNTR 0 interrupt CNTR 1 interrupt Timer X interrupt Timer Y interrupt Timer Z interrupt Timer A interrupt R e s e r v e d a r e a

Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.11 Differences between 7540 Group and 7531 Group Figure 3.11.3 shows the timer function of 7540 Group and 7531 Group. Fig. 3.11.3 Timer function of 7540 Group and 7531 Group T i m e r Y c a n b e u s e d f o r t h e t i m e r Z c o u n t s o u r c e 7 5 4 0 G r o u p7 5 3 1 G r o u p G T i m e r b i t t i m e r T i m e r m o d e T h e n u m b e r o f t i m e r i n c r e a s e d F u n c t i o n e x p a n d e d G T i m e r b i t t i m e r T i m e r m o d e G T i m e r X b i t t i m e r T i m e r m o d e P u l s e o u t p u t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e G Timer 1 (8-bit timer)

• Timer mode G Timer X (8-bit timer)
• Timer mode
• Pulse output mode (inverted output port added)
• Event counter mode
• Pulse width measurement mode G Timer Y (8-bit timer)
• Timer mode
• Programmable waveform generation mode G Timer Z (8-bit timer)
• Timer mode
• Programmable waveform generation mode
• Programmable one-shot generation mode
• Programmable wait one-shot generation mode G Timer A (16-bit timer)
• Timer mode
• Period measurement mode
• Event counter mode
• Pulse width HL continuously measurement mode

RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER USER’S MANUAL Publication Data : Rev.1.00 Jan 01, 2002 Rev.2.00 Jun 21, 2004 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.

User's Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan