74VHC4066_05 FAIRCHILD

Document overview

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Technical content

Features

I Typical switch enable time: 15 ns I Wide analog input voltage range: 0–12V I Low “on” resistance: 30 typ. ('4066) I Low quiescent current: 80 /c80 A maximum (74VHC) I Matched switch characteristics I Individual switch controls I Pin and function compatible with the 74HC4066 Ordering Code: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 1: “_NL ” indicates Pb-Free package (per JEDEC S-STD-020B). Device available in Tape and Reel only. Connection Diagram Top View Schematic Diagram Truth Table Order Number Package Package Description Number 74VHC4066M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC4066MX_NL (Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC4066MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC4066MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC4066N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Input Switch CTL I/O–O/I L “OFF ” H “ON ”

www.fairchildsemi.com 2 74VHC4066 Absolute Maximum Ratings(Note 2) (Note 3) Recommended Operating Conditions Note 2: Absolute Maximum Ratings are those values beyond which dam- age to the device may occur. Note 3: Unless otherwise specified all voltages are referenced to ground. Note 4: Power Dissipation temperature derating — plastic “N ” package: /c16 12 mW/ /c113 C from 65/c113 C to 85/c113 C. Note 5: For a power supply of 5V /c114 10% the worst case on resistance (RON ) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing for CMOS at the higher voltage and so the 5.5V values should be used. Note 6: At supply voltages (VCC – GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital only when using these supply voltages. Supply Voltage (VCC ) /c16 0.5 to /c14 15V DC Control Input Voltage (VIN) /c16 1.5 to VCC /c14 1.5V DC Switch I/O Voltage (VIO)V EE /c16 0.5 to VCC /c14 0.5V Clamp Diode Current (IIK, IOK ) /c114 20 mA DC Output Current, per pin (IOUT ) /c114 25 mA DC V CC or GND Current, per pin (ICC ) /c114 50 mA Storage Temperature Range (TSTG ) /c16 65/c113 C to /c14 150/c113 C Power Dissipation (PD ) (Note 4) 600 mW S.O. Package only 500 mW Lead Temperature (TL) (Soldering 10 seconds) 260 /c113 C Min Max Units Supply Voltage (VCC )2 1 2 V DC Input or Output Voltage 0 V CC V (VIN, VOUT ) Operating Temperature Range (TA) /c16 40 /c14 85 /c113 C Input Rise or Fall Times (tr, tf) VCC /c32 2.0V 1000 ns VCC /c32 4.5V 500 ns VCC /c32 9.0V 400 ns Symbol Parameter Conditions VCC TA /c32 25/c113 CT A /c32/c16 40 to 85/c113 C Units Typ Guaranteed Limits VIH Minimum HIGH Level 2.0V 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 V 9.0V 6.3 5.3 V 12.0V 8.4 8.4 V VIL Maximum LOW Level 2.0V 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 V 9.0V 2.7 2.7 V 12.0V 3.6 3.6 V R ON Maximum “ON ” Resistance V CTL /c32 VIH, IS /c32 2.0 mA 4.5V 100 170 200 /c58 See (Note 6) V IS /c32 VCC to GND 9.0V 50 85 105 /c58 (Figure 1) 12.0V 30 70 85 /c58 2.0V 120 180 215 /c58 VCTL /c32 VIH, IS /c32 2.0 mA 4.5V 50 80 100 /c58 VIS /c32 VCC or GND 9.0V 35 60 75 /c58 (Figure 1) 12.0V 20 40 60 /c58 R ON Maximum “ON ” Resistance V CTL /c32 VIH 4.5V 10 15 20 /c58 Matching V IS /c32 VCC to GND 9.0V 5 10 15 /c58 12.0V 5 10 15 /c58 IIN Maximum Control V IN /c32 VCC or GND /c114 0.05 /c114 0.5 /c80 A Input Current V CC /c32 2 /c16 6V IIZ Maximum Switch “OFF ” VOS /c32 VCC or GND 6.0V 10 /c114 60 /c114 600 nA Leakage Current V IS /c32 GND or VCC 9.0V 15 /c114 80 /c114 800 nA VCTL /c32 VIL (Figure 2) 12.0V 20 /c114 100 /c114 1000 nA IIZ Maximum Switch “ON ” VIS /c32 VCC to GND 6.0V 10 /c114 40 /c114 150 nA Leakage Current V CTL /c32 VIH 9.0V 15 /c114 50 /c114 200 nA VOS /c32 OPEN (Figure 3) 12.0V 20 /c114 60 /c114 300 nA ICC Maximum Quiescent V IN /c32 VCC or GND 6.0V 1.0 10 /c80 A Supply Current I OUT /c32 0 /c80 A 9.0V 2.0 20 /c80 A 12.0V 4.0 40 /c80 A

3 www.fairchildsemi.com 74VHC4066 VCC /c32 2.0V/c16 6.0V VEE /c32 0V/c16 12V, CL /c32 50 pF (unless otherwise specified) Note 7: Adjust 0 dBm for F /c32 1 kHz (Null RL/RON Attenuation). Note 8: VIS is centered at VCC /2. Note 9: Adjust input for 0 dBm. Symbol Parameter Conditions VCC TA /c32 25/c113 CT A /c32/c16 40 to 85/c113 C Units Typ Guaranteed Limits tPHL , tPLH Maximum Propagation 3.3V 25 30 20 ns Delay Switch In to Out 4.5V 5 10 13 ns 9.0V 4 8 10 ns 12.0V 3 7 11 ns t PZL , tPZH Maximum Switch Turn R L /c32 1 k/c58 3.3V 30 58 73 ns “ON ” Delay 4.5V 12 20 25 ns 9.0V 6 12 15 ns 12.0V 5 10 13 ns tPHZ , tPLZ Maximum Switch Turn R L /c32 1 k/c58 3.3V 60 100 125 ns “OFF ” Delay 4.5V 25 36 45 ns 9.0V 20 32 40 ns 12.0V 15 30 38 Minimum Frequency R L /c32 600/c58 4.5V 40 MHz Response (Figure 7)V IS /c32 2 VPP at (VCC /2) 9.0V 100 MHz 20 log (VO /VI) /c32 /c16 3 dB (Note 7)(Note 8) Crosstalk Between R L /c32 600/c58 , F /c32 1 MHz any Two Switches (Note 8)(Note 9) 4.5V /c16 52 dB (Figure 8)9 . 0 V /c16 50 dB Peak Control to Switch R L /c32 600/c58 , F /c32 1 MHz 4.5V 100 mV Feedthrough Noise C L /c32 50 pF 9.0V 250 mV (Figure 9) Switch OFF Signal R L /c32 600/c58 , F /c32 1 MHz Feedthrough V (CT) VIL Isolation (Note 8)(Note 9) 4.5V /c16 42 dB (Figure 10)9 . 0 V /c16 44 dB THD Total Harmonic R L /c32 10 k/c58 , CL /c32 50 pF, Distortion F /c32 1 kHz (Figure 11)V IS /c32 4 VPP 4.5V .013 % VIS /c32 8 VPP 9.0V .008 % C IN Maximum Control 5 10 10 pF Input Capacitance C IN Maximum Switch 20 pF Input Capacitance C IN Maximum Feedthrough V CTL /c32 GND 0.5 pF Capacitance C PD Power Dissipation 15 pF Capacitance

7 www.fairchildsemi.com 74VHC4066 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A

www.fairchildsemi.com 8 74VHC4066 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

9 www.fairchildsemi.com 74VHC4066 Quad Analog Switch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com