74LVT16500A Datasheet PDF & Specifications

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74LVT16500A NEXPERIA

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Manufacturer or author: Provided By digicamel.com
PDF pages: 20

Technical content

Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. use http://www.nexperia.com salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e -mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia

General description The 74LVT16500A is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data ﬂow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CP AB and CPBA) inputs. For A-to-B data ﬂow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched ifCP AB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/ﬂip-ﬂop on the HIGH-to-LOW transition of CP AB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data ﬂow for B-to-A is similar to that of A-to-B but usesOEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH, andOEBA is active LOW). Active bus-hold circuitry is provided to hold unused or ﬂoating data inputs at a valid logic level. 2. Features n 18-bit bidirectional bus interface n 3-state buffers n Output capability: +64 mA and−32 mA n TTL input and output switching levels n Input and output interface capability to systems at 5 V supply n Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs n Live insertion/extraction permitted n Power-up reset n Power-up 3-state n No bus current loading when output is tied to 5 V bus n Negative edge-triggered clock inputs n Latch-up protection: u JESD78: exceeds 500 mA n ESD protection: u MIL STD 883 Method 3015: exceeds 2000 V u CDM JESD22-C101-C exceeds 1000 V 74LVT16500A

3.3 V 18-bit universal bus transceiver; 3-state

Rev. 03 — 29 May 2006 Product data sheet

651 B2 A2

849 B3 A3

948 B4 A4

1047 B5 A5

1245 B6 A6

1344 B7 A7

1443 B8 A8

1542 B9 A9

1641 B10 A10

1740 B11 A11

1938 B12 A12

2037 B13 A13

2136 B14 A14

2334 B15 A15

2433 B16 A16

2631 B17 A17

74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 3 of 19 Philips Semiconductors 74LVT16500A Fig 3. Logic diagram 001aaf035 54A0 to 17 other channels CLK 1D B0 OEBA 27 CPBA 30 LEBA 28 LEAB 2 CPAB 55 OEAB 1 CLK

5.1 Pinning

5.2 Pin description

Table 2. Pin description

Recommended operating conditions

Table 4. Limiting values Table 5. Recommended operating conditions

74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. [1] Typical values are at VCC = 3.3 V and Tamb = 25°C. [2] For valid test results, data must not be loaded into the ﬂip-ﬂops (or latches) after applying power. [4] This is the bus hold overdrive current required to force the input to the opposite logic state. a transition time of 100µs is permitted. This parameter is valid for Tamb = 25°C only. [6] ICC is measured with outputs pulled to VCC or GND. [7] This is the increase in supply current for each input at the speciﬁed voltage level other than VCC or GND. Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit seeFigure11.

74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit seeFigure11.

74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. [1] All typical values are measured at VCC = 3.3 V and Tamb = 25°C. Voltages are referenced to GND (ground = 0 V); for test circuit seeFigure11. Measurements points are given inTable8. VOL and VOH are typical voltage output drop that occur with the output load.

74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 12 of 19 Philips Semiconductors 74LVT16500A Measurements points are given inTable8. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Propagation delay clock (CP AB, CPB A) to output (An, Bn), clock (CP AB, CPB A) pulse width and maximum clock frequency (CP AB, CPB A) Measurements points are given inTable8. VOL and VOH are typical voltage output drop that occur with the output load. Fig 7. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) and latch enable (LEAB, LEBA) pulse width Measurements points are given inTable8. VOH is typical voltage output drop that occur with the output load. Fig 8. 3-state output enable time to HIGH-level and output disable time from HIGH-level 001aaf037 input CPBA or CPAB tPHL tPLH tWHtWL VOH VI 0 V VOL VM VM VM VM 1/fmax output An or Bn 001aad310 VM VMVM VM VM tPLHtPHL tWH input LEAB or LEBA output An or Bn VOH VOL VI 0 V 001aad344 output An or Bn VM VY VM tPHZtPZH VM VOH VI 0 V 0 V OEBA input OEAB

74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Measurements points are given inTable8. VOL is typical voltage output drop that occur with the output load. Measurements points are given inTable8. Table 8. Measurement points

3.0 V or VCC

74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Test data is given inTable9. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Table 9. Test data

Package outline Fig 12. Package outline SOT364-1 (TSSOP56) UNIT A 1 A 2 A 3 bp cD (1) E (2) eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.2 0.1 o o0.1 DIMENSIONS (mm are the original dimensions). Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. SOT364-1 99-12-27 03-02-19 w M q AA 1 A 2 D Lp Q detail X E Z e c L X (A )3 0.25 12 8 56 29 y pin 1 index b H 1.05 0.85 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 1 8.3 7.9 0.50 0.35 0.5 0.10.080.250.8 0.4 p E v M A A TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 A max. 1.2 0 2.5 5 mm scale MO-153

74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 16 of 19 Philips Semiconductors 74LVT16500A Fig 13. Package outline SOT371-1 (SSOP56) UNIT A 1 A 2 A 3 bp cD (1) E (1) eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 18.55 18.30 7.6 7.4 0.635 10.4 10.1 1.0 0.6 1.2 1.0 0.85 0.40 o o0.180.251.4 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. SOT371-1 99-12-27 03-02-18 (1) w M bp D H E E Z e c v M A X A y 56 29 MO-118 281 q AA 1 A 2 Lp Q detail X L (A )3 pin 1 index 0 5 10 mm scale SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 A max. 2.8

The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors
Section 2 “Features”: replaced JEDEC JC40.2 Std 17 with JESD78
Figure 3 “Logic diagram”: corrected clock names and pin names
Table 7 “Dynamic characteristics”: splitting up tsu(H) and tsu(L) parameter ‘An to LEAB or Bn to LEBA’ in 2 parameters with clock conditions and new values 74LVT16500A_2 (9397 750 03556)

19980219 Product speciﬁcation - 74LVT16500A_1

Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com.

15.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

Philips Semiconductors 74LVT16500A © Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. Date of release: 29 May 2006 Document identifier: 74LVT16500A_3 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 17. Contents

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Overview

74LVT16500A is listed in the Logic IC category. Available datasheets include documents from NXP Semiconductors. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

3.3 V 18-bit universal bus transceiver; 3-state Rev. 03 - 29 May 2006

Description

3.3 V 18-bit universal bus transceiver; 3-state Rev. 03 - 29 May 2006

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