74LVT162245 FAIRCHILD

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Features

I Input and output interface capability to systems at 5V V CC I Bushold data inputs eliminate the need for external pull- up resistors to hold unused inputs (74LVTH162245), also available without bushold feature (74LVT162245). I Live insertion/extraction permitted I Power Up/Down high impedance provides glitch-free bus loading I A Port outputs include equivalent series resistance of /c58 making external termination resistors unnecessary and reducing overshoot and undershoot I A Port outputs source/sink /c114 12 mA. B Port outputs source/sink /c16 32 mA//c14 64 mA I Functionally compatible with the 74 series 162245 I Latch-up performance exceeds 500 mA I ESD performance: Human-body model /c33 2000V Machine model /c33 200V Charged-device model /c33 1000V I Also packaged in plastic Fine Pitch Ball Grid Array (FBGA) Ordering Code: Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Order Number Package Number Package Description 74LVT162245G (Note 1)(Note 2) BGA54A (Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVT162245MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT162245MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH162245G (Note 1)(Note 2) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVTH162245MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE] 74LVTH162245MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LVTH162245MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 74LVTH162245MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL]

www.fairchildsemi.com 2 74LVT162245  74LVTH162245 Logic Symbol Connection Diagrams Pin Assignments for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) Pin Descriptions FBGA Pin Assignments Truth Tables H /c32 HIGH Voltage Level L /c32 LOW Voltage Level X /c32 Immaterial Z /c32 High Impedance Pin Names Description OE n Output Enable Input (Active LOW) T/Rn Transmit/Receive Input A0–A15 Side A Inputs/3-STATE Outputs B0–B15 Side B Inputs/3-STATE Outputs NC No Connect 123456 A B0 NC T/R 1 OE 1 NC A 0 B B2 B1 NC NC A 1 A2 C B4 B3 VCC VCC A3 A4 D B6 B5 GND GND A 5 A6 E B8 B7 GND GND A 7 A8 F B10 B9 GND GND A 9 A10 G B12 B11 VCC VCC A11 A12 H B14 B13 NC NC A 13 A14 J B15 NC T/R 2 OE 2 NC A 15 Inputs Outputs OE 1 T/R1 LL B u s B 0–B7 Data to Bus A0–A7 LH B u s A 0–A7 Data to Bus B0–B7 H X HIGH-Z State on A 0–A7, B0–B7 Inputs Outputs OE 2 T/R2 LL B u s B 8–B15 Data to Bus A8–A15 LH B u s A 8–A15 Data to Bus B8–B15 H X HIGH-Z State on A 8–A15, B8–B15

3 www.fairchildsemi.com 74LVT162245  74LVTH162245 Functional Description The LVT162245 and LVTH162245 contain sixteen non- inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identi- cally, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

www.fairchildsemi.com 4 74LVT162245  74LVTH162245 Absolute Maximum Ratings(Note 3) Recommended Operating Conditions Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed. Symbol Parameter Value Conditions Units VCC Supply Voltage /c16 0.5 to /c14 4.6 V VI DC Input Voltage /c16 0.5 to /c14 7.0 V VO Output Voltage /c16 0.5 to /c14 7.0 Output in 3-STATE V/c16 0.5 to /c14 7.0 Output in HIGH or LOW State (Note 4) IIK DC Input Diode Current /c16 50 V I /c31 GND mA IOK DC Output Diode Current /c16 50 V O /c31 GND mA IO DC Output Current 64 V O /c33 VCC Output at HIGH State mA128 V O /c33 VCC Output at LOW State ICC DC Supply Current per Supply Pin /c114 64 mA IGND DC Ground Current per Ground Pin /c114 128 mA TSTG Storage Temperature /c16 65 to /c14 150 /c113 C Symbol Parameter Min Max Units VCC Supply Voltage 2.7 3.6 V VI Input Voltage 0 5.5 V IOH HIGH-Level Output Current B Port /c16 32 mAA Port /c16 12 IOL LOW-Level Output Current B Port 64 mAA Port 12 TA Free Air Operating Temperature /c16 40 /c14 85 /c113 C /c39 t//c39 V Input Edge Rate, V IN /c32 0.8V–2.0V, VCC /c32 3.0V 0 10 ns/V Symbol Parameter VCC TA /c32 /c16 40/c113 C to /c14 85/c113 C Units Conditions (V) Min Max VIK Input Clamp Diode Voltage 2.7 /c16 1.2 V I I /c32 /c16 18 mA VIH Input HIGH Voltage 2.7 –3.6 2.0 V V O /c100 0.1V or VIL Input LOW Voltage 2.7 –3.6 0.8 V V O /c116 VCC /c16 0.1V VOH Output HIGH Voltage A Port 3.0 2.0 V I OH /c32 /c16 12 mA 2.7–3.6 VCC /c16 0.2 VI OH /c32 /c16 100 /c80 A B Port 2.7 2.4 V IOH /c32 /c16 8 mA 3.0 2.0 I OH /c32 /c16 32 mA VOL Output LOW Voltage A Port 3.0 0.8 V I OL /c32 12 mA 2.7 0.2 V I OL /c32 100 /c80 A B Port 2.7 0.5 V IOL /c32 24 mA 3.0 0.4 I OL /c32 16 mA 3.0 0.5 I OL /c32 32 mA 3.0 0.55 I OL /c32 64 mA II(HOLD) Bushold Input Minimum Drive 3.0 /c80 A VI /c32 0.8V (Note 5) /c16 75 V I /c32 2.0V II(OD) Bushold Input Over-Drive 3.0 500 /c80 A (Note 6) (Note 5) Current to Change State /c16 500 (Note 7) II Input Current 3.6 10 /c80 A VI /c32 5.5V Control Pins 3.6 /c114 1V I /c32 0V or VCC Data Pins 3.6 /c16 5V I /c32 0V 1V I /c32 VCC IOFF Power Off Leakage Current 0 /c114 100 /c80 A0 V /c100 VI or VO /c100 5.5V

5 www.fairchildsemi.com 74LVT162245  74LVTH162245 Note 5: Applies to Bushold versions only (74LVTH162245). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics (Note 9) Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n/c16 1 data inputs are driven 0V to 3V. Output under test held LOW. Symbol Parameter VCC TA /c32 /c16 40/c113 C to /c14 85/c113 C Units Conditions (V) Min Max IPU/PD Power Up/Down 0–1.5V /c114 100 /c80 A VO /c32 0.5V to 3.0V 3-STATE Current VI /c32 GND to VCC IOZL 3-STATE Output Leakage Current 3.6 /c16 5 /c80 AV O /c32 0.5V IOZL 3-STATE Output Leakage Current 3.6 /c16 5 /c80 AV O /c32 0.0V (Note 5) IOZH 3-STATE Output Leakage Current 3.6 5 /c80 AV O /c32 3.0V IOZH 3-STATE Output Leakage Current 3.6 5 /c80 AV O /c32 3.6V (Note 5) IOZH /c14 3-STATE Output Leakage Current 3.6 10 /c80 AV CC /c31 VO /c100 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ /c14 Power Supply Current 3.6 0.19 mA VCC /c100 VO /c100 5.5V, Outputs Disabled /c39 ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC /c16 0.6V (Note 8) Other Inputs at VCC or GND Symbol Parameter VCC TA /c32 25/c113 C Units Conditions (V) Min Typ Max C L /c32 50 pF, RL /c32 500/c58 VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10) VOLV Quiet Output Minimum Dynamic VOL 3.3 /c16 0.8 V (Note 10)

www.fairchildsemi.com 6 74LVT162245  74LVTH162245 Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL ) or LOW-to-HIGH (tOSLH ). Capacitance (Note 12) Note 12: Capacitance is measured at frequency f /c32 1 MHz, per MIL-STD-883, Method 3012. Symbol Parameter TA /c32 /c16 40/c113 C to /c14 85/c113 C Units C L /c32 50 pF, RL /c32 500/c58 VCC /c32 3.3V /c114 0.3V V CC /c32 2.7V M i nM a xM i nM a x tPLH Propagation Delay Data to A Port Output 1.0 4.0 1.0 4.6 ns tPHL 1.0 3.7 1.0 4.1 tPLH Propagation Delay Data to B Port Output 1.0 3.5 1.0 3.9 ns tPHL 1.0 3.5 1.0 3.9 tPZH Output Enable Time for A Port Output 1.0 5.3 1.0 6.3 ns tPZL 1.0 5.6 1.0 7.2 tPZH Output Enable Time for B Port Output 1.0 4.6 1.0 5.4 ns tPZL 1.0 5.3 1.0 6.9 tPHZ Output Disable Time for A Port Output 1.5 5.6 1.5 6.3 ns tPLZ 1.5 5.5 1.5 5.5 tPHZ Output Disable Time for B Port Output 1.5 5.4 1.5 6.1 ns tPLZ 1.5 5.1 1.5 5.4 tOSHL A Port Output to Output Skew 1.0 1.0 ns tOSLH (Note 11) tOSHL B Port Output to Output Skew 1.0 1.0 ns tOSLH (Note 11) Symbol Parameter Conditions Typical Units C IN Input Capacitance V CC /c32 0V, VI /c32 0V or VCC 4p F C I/O Input/Output Capacitance V CC /c32 3.0V, VO /c32 0V or VCC 8p F

7 www.fairchildsemi.com 74LVT162245  74LVTH162245 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

www.fairchildsemi.com 8 74LVT162245  74LVTH162245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

9 www.fairchildsemi.com 74LVT162245  74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25/G58 Series Resistors in A Port Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com