74LVC16373A NEXPERIA

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74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 10 — 1 October 2021 Product data sheet 1. General description The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs. The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits

  • Overvoltage tolerant inputs to 5.5 V
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power dissipation
  • MULTIBYTE flow-through standard pinout architecture
  • Multiple low inductance supply pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • All data inputs have bus hold (74LVCH16373A only)
  • IOFF circuitry provides partial Power-down mode operation
  • Complies with JEDEC standards:
  • JESD8-7A (1.65 V to 1.95 V)
  • JESD8-5A (2.3 V to 2.7 V)
  • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
  • HBM JESD22-A114F exceeds 2000 V
  • MM JESD22-A115-B exceeds 200 V
  • CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Table 1. Ordering information

Nexperia 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state to internal circuit mgu771 VCC data input Fig. 4. Bus hold circuit 5. Pinning information 5.1. Pinning 16373A 001aad112 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 GND 1Q6 1Q7 2Q0 2Q1 GND 2Q2 2Q3 VCC 2Q4 2Q5 GND 2Q6 2Q7 2OE 1D0 1D1 GND 1D2 1D3 VCC 1D4 1D5 GND 1D6 1D7 2D0 2D1 GND 2D2 2D3 VCC 2D4 2D5 GND 2D6 2D7 2LE 1OE 1LE Fig. 5. Pin configuration SOT362-1 (TSSOP48) and SOT480-1 (TSSOP48) 74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 — 1 October 2021 3 / 15

Table 2. Pin description Table 3. Function table

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SOT362-1 (TSSOP48) packages: Ptot derates linearly with 12.2 mW/K above 109 °C. For SOT480-1 (TVSOP48) packages: Ptot derates linearly with 5.5 mW/K above 60 °C.

  1. Recommended operating conditions

Table 5. Recommended operating conditions

Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. [2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. [3] Valid for data inputs (74LVCH16373A) only; control inputs do not have a bus hold circuit. [4] The specified sustaining current at the data inputs holds the input below the specified VI level. [5] The specified overdrive current at the data input forces the data input to the opposite logic input state. Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 10.

Nexperia 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions Min Typ [1] Max Min Max Unit OE to Qn; see Fig. 8 [2] VCC = 1.2 V - 11 - - - ns tdis disable time LE HIGH; see Fig. 7 VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.0 - - 3.0 - ns tW pulse width Dn to LE; see Fig. 9 VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns VCC = 2.7 V 2.0 - - 2.0 - ns tsu set-up time Dn to LE; see Fig. 9 VCC = 1.65 V to 1.95 V 2.5 - - 2.5 - ns VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns VCC = 2.7 V 0.9 - - 0.9 - ns th hold time tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns per input; VI = GND to VCC [4] VCC = 1.65 V to 1.95 V - 10.8 - - - pF VCC = 2.3 V to 2.7 V - 13.0 - - - pF CPD power dissipation capacitance VCC = 3.0 V to 3.6 V - 15.0 - - - pF [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC 2 × fo) = sum of the outputs 74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 — 1 October 2021 8 / 15

Nexperia 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 10.1. Waveforms and test circuit mgu772 Dn input Qn output tPHL tPLH GND VI VM VM VM VOH VOL Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. Input (Dn) to output (Qn) propagation delays mgu773 LE input Qn output tPHL tPLH tW VM VM VOH VI GND VOL VM VM VM Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 7. Latch enable input (LE) pulse width, and the latch enable input to output (Qn) propagation delays mgu775 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH OE input VI VOL VOH VCC VM VM GND GND tPZL tPZH VM VM Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 8. 3-state enable and disable times mgu774 th th tsutsu VM VM VI GND VI GND LE input Dn input Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 9. Data set-up and hold times for the Dn input to the LE input 74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 — 1 October 2021 9 / 15

Table 8. Measurement points Test data is given in Table 9. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Table 9. Test data

1.2 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND

Nexperia 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 11. Package outline ReferencesOutline version European projection Issue date IEC JEDEC JEITA SOT362-1 MO-153 sot362-1_po 03-02-19 13-08-05 Unit mm max nom min 0.15 0.28 0.2 12.6 0.5 0.8 A Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 A1 A2 1.05 A3 bp c D(1) θE(2) e HE L Lp Q v w y Z 8.3 0.86.2 0.50 pin 1 index v A θ A D Lp Q E Z c L 1 24 48 25 e w y X A HE bp detail X (A3) 0 5 mm scale 2.5 Fig. 11. Package outline SOT362-1 (TSSOP48) 74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 — 1 October 2021 11 / 15

Nexperia 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state UNIT A1 A2 A3 bp D (1) E (2) HE Lpc e L Q Z (1)ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE 03-02-18 19-12-11 IEC JEDEC JEITA mm 0.15 0.05 0.95 0.85 0.23 0.13 0.20 0.09 9.8 9.6 4.5 4.3 6.6 6.20.4 0.4 0.3 o o0.07 0.080.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.7 0.5 SOT480-1 MO-153 0.25 0.4 0.1 w M bpe 1 24 48 25 Z pin 1 index θ A Lp Q detail X L (A )3 HE E c v M A X AD y 0 2.5 5 mm scale TVSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm SOT480-1 A max. 1.1 Fig. 12. Package outline SOT480-1 (TVSOP48) 74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 — 1 October 2021 12 / 15

Table 10. Abbreviations Table 11. Revision history Modifications: • Type number 74LVC16373ADL (SOT370-1/SSOP48) removed.

  • Package outline drawing SOT480-1 updated.
  • Section 1 and Section 2 updated. 74LVC_LVCH16373A v.9 20190215 Product data sheet - 74LVC_LVCH16373A v.8 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia.
  • Legal texts have been adapted to the new company name where appropriate.
  • Type numbers 74LVCH16373ADL (SOT370-1) removed.
  • Type numbers 74LVC16373ADGV and 74LVCH16373ADGV (SOT480-1) added. 74LVC_LVCH16373A v.8 20140106 Product data sheet - 74LVC_LVCH16373A v.7 Modifications: • General description corrected (errata). 74LVC_LVCH16373A v.7 20130118 Product data sheet - 74LVC_LVCH16373A v.6 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.
  • Legal texts have been adapted to the new company name where appropriate.
  • Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges. 74LVC_LVCH16373A v.6 20031208 Product specification - 74LVC_LVCH16373A v.5 74LVC_LVCH16373A v.5 20021002 Product specification - 74LVC_H16373A v.4 74LVC_H16373A v.4 19980317 Product specification - 74LVC16373A_ 74LVCH16373A v.3 74LVC16373A_ 74LVCH16373A v.3 19980317 Product specification - 74LVC16373A v.2 74LVC16373A v.2 19970822 Product specification - 74LVC16373A v.1 74LVC16373A v.1 19960108 - - - 74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 — 1 October 2021 13 / 15

Nexperia 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 14. Legal information Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 74LVC_LVCH16373A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 — 1 October 2021 14 / 15