74LVCH162374A NEXPERIA
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 14
Technical content
Datasheet sections
OFF-state. Operation of the OE input does not affect the state of the flip-flops. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.
- 5 V tolerant inputs/outputs for interfacing with 5 V logic
- Wide supply voltage range from 1.2 V to 3.6 V
- CMOS low power consumption
- Multibyte flow-through standard pinout architecture
- Multiple low inductance supply pins for minimum noise and ground bounce
- Direct interface with TTL levels
- All data inputs have bus hold
- High-impedance outputs when VCC = 0 V
- Complies with JEDEC standard:
- JESD8-7A (1.65 V to 1.95 V)
- JESD8-5A (2.3 V to 2.7 V)
- JESD8-C/JESD36 (2.7 V to 3.6 V)
- ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-B exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
- Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information
Table 1. Ordering information
16-bit edge-triggered D-type flip-flop with 30 Ω series termination resistors; 5 V input/output tolerant; 3-state 4. Functional diagram 001aaa253 1Q0 1Q1 1CP 2CP 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1OE 48 25 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2OE Fig. 1. Logic symbol 001aaa254 37 12 1D7 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1Q7 1Q6 1Q5 1Q4 1Q3 1Q2 1Q0 1Q1 2D5 2D0 2D1 2D2 2D3 2D4 2Q5 2Q4 2Q3 2Q2 2Q1 2Q0 EN2 1OE 1 EN1 1CP 2OE 2CP 48 C3 3D 1 2D7 2D6 2Q7 2Q6 Fig. 2. IEC logic symbol 001aaa255 1CP 1OE to 7 other channels D CP Q FF1 1Q01D0 2CP 2OE to 7 other channels D CP Q FF2 2Q02D0 Fig. 3. Logic diagram to internal circuit mgu771 VCC data input Fig. 4. Bus hold circuit 74LVCH162374A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 — 20 April 2021 2 / 14
Table 2. Pin description
Table 3. Function selection Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SOT362-1 (TSSOP48) packages: Ptot derates linearly with 12.2 mW/K above 109 °C.
- Recommended operating conditions
Table 5. Operating conditions
Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. [2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. [3] For data inputs only; control inputs do not have a bus hold circuit. [4] The specified sustaining current at the data inputs do not have a bus hold circuit. [5] The specified overdrive current at the data input forces the data input to the opposite logic input state. Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 9.
16-bit edge-triggered D-type flip-flop with 30 Ω series termination resistors; 5 V input/output tolerant; 3-state Tamb = -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions Min Typ [1] Max Min Max Unit nCP HIGH; see Fig. 6 VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.0 - 3.0 - ns tW pulse width nDn to nCP; see Fig. 7 VCC = 1.65 V to 1.95 V 4.0 - - 4.0 - ns VCC = 2.3 V to 2.7 V 3.0 - - 3.0 - ns VCC = 2.7 V 1.9 - - 1.9 - ns tsu set-up time nDn to nCP; see Fig. 7 VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns VCC = 2.7 V 1.5 - - 1.5 - ns th hold time see Fig. 6 VCC = 1.65 V to 1.95 V 100 - - 80 - MHz VCC = 2.3 V to 2.7 V 125 - - 100 - MHz VCC = 2.7 V 150 - - 120 - MHz fmax maximum frequency VCC = 3.0 V to 3.6 V 150 330 - 120 - MHz tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns per input; VI = GND to VCC [4] VCC = 1.65 V to 1.95 V - 9.6 - - - pF VCC = 2.3 V to 2.7 V - 11.7 - - - pF CPD power dissipation capacitance VCC = 3.0 V to 3.6 V - 13.5 - - - pF [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC 2 × fo) = sum of the outputs 74LVCH162374A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 — 20 April 2021 7 / 14
16-bit edge-triggered D-type flip-flop with 30 Ω series termination resistors; 5 V input/output tolerant; 3-state 10.1. Waveforms and test circuit 001aaa256 nCP input nQn output tPHL tPLH tW VOH VI GND VOL VM VM VM 1/fmax Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. Clock input (nCP) to output (nQn) propagation delay, the clock pulse width, and the maximum frequency 001aaa257 GND GND th tsu th tsu VM VM VM VI VOH VOL VI nQn output nCP input nDn input Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 7. Data set-up and hold times for the nDn input to the nCP input 74LVCH162374A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 — 20 April 2021 8 / 14
Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Table 8. Measurement points
Test data is given in Table 9. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Table 9. Test data
1.2 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND
16-bit edge-triggered D-type flip-flop with 30 Ω series termination resistors; 5 V input/output tolerant; 3-state 11. Package outline ReferencesOutline version European projection Issue date IEC JEDEC JEITA SOT362-1 MO-153 sot362-1_po 03-02-19 13-08-05 Unit mm max nom min 0.15 0.28 0.2 12.6 0.5 0.8 A Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 A1 A2 1.05 A3 bp c D(1) θE(2) e HE L Lp Q v w y Z 8.3 0.86.2 0.50 pin 1 index v A θ A D Lp Q E Z c L 1 24 48 25 e w y X A HE bp detail X (A3) 0 5 mm scale 2.5 Fig. 10. Package outline SOT362-1 (TSSOP48) 74LVCH162374A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 — 20 April 2021 11 / 14
Table 10. Abbreviations Table 11. Revision history
- Legal texts have been adapted to the new company name where appropriate.
- Type number 74LVCH162374ADL (SOT370-1 / SSOP48) removed.
- Section 7: Derating values for Ptot total power dissipation updated.
- Fig. 10: Package outline drawing SOT362-1 (TSSOP48) updated. 74LVCH162374A v.4 20130122 Product data sheet - 74LVCH162374A v.3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.
- Legal texts have been adapted to the new company name where appropriate.
- Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges. 74LVCH162374A v.3 20040519 Product specification - 74LVC_LVCH162374A v.2 74LVC_LVCH162374A v.2 20040325 Product specification - 74LVC_LVCH162374A v.1 74LVC_LVCH162374A v.1 19990805 Product specification - - 74LVCH162374A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 — 20 April 2021 12 / 14
16-bit edge-triggered D-type flip-flop with 30 Ω series termination resistors; 5 V input/output tolerant; 3-state 14. Legal information Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. 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Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 74LVCH162374A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 — 20 April 2021 13 / 14