74LVC2G02GM Datasheet PDF & Specifications

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74LVC2G02 PANASONIC

Document overview

Manufacturer or author: Provided By digicamel.com
PDF pages: 16

Technical content

Product speciﬁcation Supersedes data of 2003 Oct 15

2004 Sep 15

2004 Sep 15 2

Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02

FEATURES

Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V).
± 24 mA output drive (V CC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V.
Specified from−40 °C to +85°C and−40 °C to +125°C.

DESCRIPTION

The 74LVC2G02 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I off. The Ioffcircuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC2G02 provides the 2-input NOR gate function. QUICK REFERENCE DATA GND = 0 V; T amb =2 5°C; tr =tf≤ 2.5 ns. Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW). PD =C PD × VCC 2 × fi× N+ Σ(CL × VCC 2 × fo) where: fi= input frequency in MHz; fo = output frequency in MHz; C L = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(C L × VCC 2 × fo) = sum of the outputs. 2. The condition is VI= GND to VCC . SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL /tPLH propagation delay inputs nA, nB to output nY VCC = 1.8 V; CL = 30 pF; RL =1k Ω 3.8 ns VCC = 2.5 V; CL = 30 pF; RL = 500Ω 2.4 ns VCC = 2.7 V; CL = 50 pF; RL = 500Ω 3.2 ns VCC = 3.3 V; CL = 50 pF; RL = 500Ω 2.4 ns VCC = 5.0 V; CL = 50 pF; RL = 500Ω 1.8 ns C I input capacitance 2.5 pF C PD power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 14 pF

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 FUNCTION TABLE See note 1. Note 1. H = HIGH voltage level; L = LOW voltage level.

ORDERING INFORMATION

RANGE PINS PACKAGE MATERIAL CODE MARKING 74LVC2G02DP −40 °C to +125°C 8 TSSOP8 plastic SOT505-2 V02 74LVC2G02DC −40 °C to +125°C 8 VSSOP8 plastic SOT765-1 V02 74LVC2G02GM −40 °C to +125°C 8 XSON8 plastic SOT833-1 V02 PIN SYMBOL DESCRIPTION 1 1A data input 2 1B data input 3 2Y data output

4 GND ground (0 V)

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 1A V CC 1B 1Y 2Y 2B GND 2A 001aab642 Fig.1 Pin configuration TSSOP8 and VSSOP8. V CC GND 001aab643 Transparent top view Fig.2 Pin configuration XSON8. handbook, halfpage MNA716 1B 1Y2 1 7 5 3 Fig.3 Logic symbol. handbook, halfpage MNA717 7‡ 1 ‡ 1 Fig.4 IEC logic symbol.

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 handbook, halfpage MNA105 B A Y Fig.5 Logic diagram (one gate).

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 RECOMMENDED OPERATING CONDITIONS LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When V CC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage active mode 0 V CC V VCC = 0 V; Power-down mode 0 5.5 V Tamb operating ambient temperature −40 +125 °C tr,tf input rise and fall times V CC = 1.65 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 5.5 V 0 10 ns/V SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage −0.5 +6.5 V IIK input diode current V I<0 V −− 50 mA VI input voltage note 1 −0.5 +6.5 V IOK output diode current V O >V CC or VO <0 V −± 50 mA VO output voltage active mode; notes 1 and 2 −0.5 V CC + 0.5 V Power-down mode; notes 1 and 2−0.5 +6.5 V IO output source or sink current VO =0 Vt oVCC −± 50 mA ICC , IGND VCC or GND current −± 100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation T amb = −40 °C to +125°C − 300 mW

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNIT OTHER V CC (V) Tamb = −40 °C to +85°C VIH HIGH-level input voltage 1.65 to 1.95 0.65 × VCC −− V 4.5 to 5.5 0.7 × VCC −− V VIL LOW-level input voltage 1.65 to 1.95 −− 0.35× VCC V 4.5 to 5.5 −− 0.3× VCC V VOH HIGH-level output voltage VI=V IH or VIL IO = −100 µA 1.65 to 5.5 V CC − 0.1 −− V IO = −4 mA 1.65 1.2 1.53 − V IO = −8 mA 2.3 1.9 2.13 − V IO = −12 mA 2.7 2.2 2.50 − V IO = −24 mA 3.0 2.3 2.60 − V IO = −32 mA 4.5 3.8 4.10 − V VOL LOW-level output voltage VI=V IH or VIL IO = 100µA 1.65 to 5.5 −− 0.1 V IO = 4 mA 1.65 − 0.08 0.45 V IO = 8 mA 2.3 − 0.14 0.3 V IO = 12 mA 2.7 − 0.19 0.4 V IO = 24 mA 3.0 − 0.37 0.55 V IO = 32 mA 4.5 − 0.43 0.55 V ILI input leakage current VI= 5.5 V or GND 5.5 −± 0.1 ±5 µA Ioff power OFF leakage current VIor VO = 5.5 V 0 −± 0.1 ±10 µA ICC quiescent supply current VI=V CC or GND; IO =0 A 5.5 − 0.1 10 µA ΔICC additional quiescent supply current per pin VI=V CC − 0.6 V; IO =0 A 2.3 to 5.5 − 5 500 µA

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 Note 1. All typical values are measured at Tamb =2 5°C. Tamb = −40 °C to +125°C VIH HIGH-level input voltage 1.65 to 1.95 0.65 × VCC −− V 4.5 to 5.5 0.7 × VCC −− V VIL LOW-level input voltage 1.65 to 1.95 −− 0.35× VCC V 4.5 to 5.5 −− 0.3× VCC V VOH HIGH-level output voltage VI=V IH or VIL IO = −100 µA 1.65 to 5.5 V CC − 0.1 −− V IO = −4 mA 1.65 0.95 −− V IO = −12 mA 2.7 1.9 −− V IO = −24 mA 3.0 2.0 −− V IO = −32 mA 4.5 3.4 −− V VOL LOW-level output voltage VI=V IH or VIL IO = 100µA 1.65 to 5.5 −− 0.1 V IO = 4 mA 1.65 −− 0.70 V IO = 8 mA 2.3 −− 0.45 V IO = 12 mA 2.7 −− 0.60 V IO = 24 mA 3.0 −− 0.80 V IO = 32 mA 4.5 −− 0.80 V ILI input leakage current VI= 5.5 V or GND 5.5 −− ± 20 µA Ioff power OFF leakage current VIor VO = 5.5 V 0 −− ± 20 µA ICC quiescent supply current VI=V CC or GND; IO =0 A 5.5 −− 40 µA ΔICC additional quiescent supply current per pin VI=V CC − 0.6 V; IO =0 A 2.3 to 5.5 −− 5000 µA SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNIT OTHER V CC (V)

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 AC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Note 1. All typical values are measured at Tamb =2 5°C. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNIT OTHER V CC (V) Tamb = −40 °C to +85°C tPHL /tPLH propagation delay nA, nB to nY 2.7 0.8 3.2 6.0 ns T amb = −40 °C to +125°C tPHL /tPLH propagation delay nA, nB to nY see Figs 6 and 7 1.65 to 1.95 1.2 − 11.2 ns 2.3 to 2.7 0.8 − 6.8 ns 2.7 0.8 − 7.5 ns 3.0 to 3.6 0.6 − 6.2 ns 4.5 to 5.5 0.6 − 5.5 ns

2004 Sep 15 10

Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 AC WAVEFORMS handbook, halfpage MNA218 tPHL tTHL tTLH tPLH VM VMnA, nB input nY output GND VI VOH VOL Fig.6 The input (nA, nB) to output (nY) propagation delays. VOL and VOH are typical output voltage drop that occur with the output load. VCC VM INPUT VI tr =tf 1.65 V to 1.95 V 0.5× VCC VCC ≤ 2.0 ns 2.3 V to 2.7 V 0.5× VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 4.5 V to 5.5 V 0.5× VCC VCC ≤ 2.5 ns

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 VEXT VCC VI VO mna616 D.U.T. C LR T R L R L PULSE GENERATOR Fig.7 Load circuitry for switching times. Definitions for test circuit: R L = Load resistor. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to the output impedance Zo of the pulse generator. VCC VI C L R L VEXT tPLH /tPHL tPZH /tPHZ tPZL /tPLZ 1.65 V to 1.95 V VCC 30 pF 1 k Ω open GND 2 × VCC 2.3 V to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6 V 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω open GND 6 V 4.5 V to 5.5 V VCC 50 pF 500 Ω open GND 2 × VCC

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 PACKAGE OUTLINES UNIT A 1 A max. A 2 A 3 bp LH E Lp wyvce D (1) E(1) Z(1) q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.00 0.95 0.75 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.70 0.35 0°0.13 0.10.20.5 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 0.47 0.33 w Mbp D Z e 0.25 8 5 q Lp (A3) detail X A L H E E c v M A XA y 2.5 5 mm0 scale TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mmSOT505-2 1.1 pin 1 index

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 UNIT A 1 A max. A 2 A 3 bp LH E Lp wyvce D (1) E(2) Z(1) θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.00 0.85 0.60 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.1 0°0.13 0.10.20.4 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.40 0.15 Q 0.21 0.19 SOT765-1 MO-187 02-06-07 w Mbp D Z e 0.12 8 5 θ Q Lp (A3) detail X A L H E E c v M A X A y 2.5 5 mm0 scale VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 pin 1 index

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 terminal 1 index area REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT833-1 04-07-15 04-07-22 DIMENSIONS (mm are the original dimensions) XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 0.95 x 1.95 x 0.5 mm D E e A 1 b LL1 e1 e1 0 1 2 mm scale Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. UNIT mm 0.25 0.17 2.0 1.9 0.35 0.27 A max b E 1.0 0.9 D ee 1 L 0.40 0.32 0.50.6 A (1) max 0.5 0.04 (2) (2) A

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Philips Semiconductors Product speciﬁcation Dual 2-input NOR gate 74LVC2G02 DATA SHEET STATUS Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. LEVEL DATA SHEET STATUS (1) PRODUCT STATUS (2)(3) DEFINITION I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips Semiconductors reserves the right to change the speciﬁcation in any manner without notice. II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN). DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

© Koninklijke Philips Electronics N.V. 2004 SCA76 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Printed in The Netherlands R20/02/pp16 Date of release:2004 Sep 15 Document order number: 9397 750 13772

Selected Specification

Panasonic Semiconductor 74LVC2G02GM overview.

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Overview

74LVC2G02GM is listed in the Logic IC category. Available datasheets include documents from NXP Semiconductors, Panasonic Semiconductor. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

Dual 2-input NOR gate

Description

Dual 2-input NOR gate

Source title 74LVC2G02GM Datasheet(PDF) - Panasonic Semiconductor

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