74LV259D

74LV259 NXP

Document overview

• PDF pages: 19

Technical content

Page 1

1. General description

The 74LV259 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The 74LV259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. The 74LV259 is multifunctional device capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. The 74LV259 also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW enable input (LE).

The 74LV259 has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the (D) input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and data (D) input. When operating the 74LV259 as an address latch, changing more than

one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode.

2. Features

I Optimized for low voltage applications: 1.0 V to 3.6 V I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C I Combines demultiplexer and 8-bit latch I Serial-to-parallel capability I Output from each storage bit available I Random (addressable) data entry I Easily expandable I Common reset input I Useful as a 3-to-8 active HIGH decoder I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C

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3. Ordering information

Table 1. Ordering information

74LV259N

−40 °C to +125 °C DIP16

74LV259D

−40 °C to +125 °C SO16

74LV259DB

−40 °C to +125 °C SSOP16

plastic dual in-line package; 16 leads (300 mil)

SOT38-4

plastic small outline package; 16 leads;

SOT109-1

body width 3.9 mm plastic shrink small outline package; 16 leads;

SOT338-1

body width 5.3 mm

−40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;

74LV259PW

SOT403-1

body width 4.4 mm

−40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very

SOT763-1

74LV259BQ

thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm

4. Functional diagram

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5. Pinning information

5.1 Pinning

5.2 Pin description

Table 2. Pin description Symbol

Pin

A0

1

A1

2

A2

3

GND

8

Q[0:7]

4, 5, 6, 7, 9, 10, 11, 12

Description

address input address input address input ground (0 V) latch output

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Table 2. Pin description …continued Symbol

Pin

D

13

LE

14

MR

15 16

VCC

6. Functional description

Table 3. Mode select table H = HIGH voltage level; L = LOW voltage level LE

MR

L

H

H

H

L

L

H

L

Table 4. Function table

Description

data input latch enable input (active LOW) conditional reset input (active LOW) supply voltage

Mode addressable latch memory active HIGH 8-channel demultiplexer reset

H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = High or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q<n> = state of the output established during the last cycle in which it was addressed or cleared

master reset

L H X X X

X L L L L L L L L

demultiplex (active L

L d L L

L Q = d L

L L L L L L

HIGH) decoder

L L d H L

L L Q = d L

L L L L L

(when D = H)

L L d L H

L L L Q = d L

L L L L

L L d H H

L L L L Q = d L

L L L

L L d L L

H L L L L Q = d L

L L

L L d H L

H L L L L L Q = d

L

L L d L H

H L L L L L L Q = d L

L L d H H

H L L L L L L L Q = d

store (do nothing) H

H X X X

X q0 q1 q2 q3 q4 q5 q6 q7

addressable latch H

L d L L

L Q = d q1

q2 q3 q4 q5 q6 q7

H L d H L

L q0 Q = d q2

q3 q4 q5 q6 q7

H L d L H

L q0 q1 Q = d q3

q4 q5 q6 q7

H L d H H

L q0 q1 q2 Q = d q4

q5 q6 q7

H L d L L

H q0 q1 q2 q3 Q = d q5

q6 q7

H L d H L

H q0 q1 q2 q3 q4 Q = d q6

q7

H L d L H

H q0 q1 q2 q3 q4 q5 Q = d q7

H L H H H

H q0 q1 q2 q3 q4 q5 q6 Q = d

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7. Limiting values

Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Max Unit

supply voltage

−0.5 +4.6 V

VCC

[1] -

input clamping current

VI < −0.5 V or VI > VCC + 0.5 V

±20 mA

IIK

[1] -

output clamping current

VO < −0.5 V or VO > VCC + 0.5 V

±50 mA

IOK

output current

VO = −0.5 V to (VCC + 0.5 V)

• ±25 mA

IO

supply current

• 50 mA

ICC

ground current

−50 - mA

IGND

storage temperature

−65 +150 °C

Tstg

total power dissipation

Tamb = −40 °C to +125 °C

Ptot

[2] -

750 mW

DIP16 package

[3] -

500 mW

SO16 package

[4] -

500 mW

(T)SSOP16 package

[5] -

500 mW

DHVQFN16 package

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 °C. [3] Ptot derates linearly with 8 mW/K above 70 °C. [4] Ptot derates linearly with 5.5 mW/K above 60 °C. [5] Ptot derates linearly with 4.5 mW/K above 60 °C.

8. Recommended operating conditions

Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Typ Max Unit

[1] 1.0

supply voltage

3.3

3.6

V

VCC

input voltage

0

-

VCC V

VI

output voltage

0

-

VCC V

VO

ambient temperature

−40

+25

+125 °C

Tamb

VCC = 1.0 V to 2.0 V

-

-

500

ns/V

∆t/∆V

input transition rise and fall rate

VCC = 2.0 V to 2.7 V

-

-

200

ns/V

VCC = 2.7 V to 3.6 V

-

-

100

ns/V

[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC).

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9. Static characteristics

Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V).

HIGH-level input voltage

VCC = 1.2 V

0.9 - - 0.9 - V

VIH

VCC = 2.0 V

1.4 - - 1.4 - V

VCC = 2.7 V to 3.6 V

2.0 - - 2.0 - V

LOW-level input voltage

VCC = 1.2 V

• - 0.3 - 0.3 V

VIL

VCC = 2.0 V

• - 0.6 - 0.6 V

VCC = 2.7 V to 3.6 V

• - 0.8 - 0.8 V

HIGH-level output voltage

VI = VIH or VIL

VOH

IO = −100 µA; VCC = 1.2 V

• 1.2 - - - V

IO = −100 µA; VCC = 2.0 V

1.8 2.0 - 1.8 - V

IO = −100 µA; VCC = 2.7 V

2.5 2.7 - 2.5 - V

IO = −100 µA; VCC = 3.0 V

2.8 3.0 - 2.8 - V

IO = −6 mA; VCC = 3.0 V

2.4 2.82 - 2.2 - V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 100 µA; VCC = 1.2 V

• 0 - - - V

IO = 100 µA; VCC = 2.0 V

• 0 0.2 - 0.2 V

IO = 100 µA; VCC = 2.7 V

• 0 0.2 - 0.2 V

IO = 100 µA; VCC = 3.0 V

• 0 0.2 - 0.2 V

IO = 6 mA; VCC = 3.0 V

• 0.25 0.40
• 0.50 V

input leakage current

VI = VCC or GND;

• - 1.0 - 1.0 µA

II

VCC = 5.5 V

supply current

VI = VCC or GND; IO = 0 A;

• - 20.0 - 160 µA

ICC

VCC = 5.5 V

additional supply current

per input; VI = VCC − 0.6 V;

• - 500 - 850 µA

∆ICC

VCC = 2.7 V to 3.6 V

input capacitance

• 3.5 - - - pF

CI

[1] Typical values are measured at Tamb = 25 °C.

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Page 7

10. Dynamic characteristics

Table 8. Dynamic characteristics GND = 0 V; For test circuit see Figure 12.

[2]

propagation delay D to Qn; see Figure 8 tpd

VCC = 1.2 V

• 105 - - - ns

VCC = 2.0 V

• 36 49 - 61 ns

VCC = 2.7 V

• 26 36 - 45 ns

[3]

VCC = 3.0 V to 3.6 V; CL = 15 pF

• 17 - - - ns

[3]

VCC = 3.0 V to 3.6 V

• 20 29 - 36 ns

[2]

propagation delay An to Qn; see Figure 7 tpd

VCC = 1.2 V

• 105 - - - ns

VCC = 2.0 V

• 36 49 - 61 ns

VCC = 2.7 V

• 26 36 - 45 ns

[3]

VCC = 3.0 V to 3.6 V; CL = 15 pF

• 17 - - - ns

[3]

VCC = 3.0 V to 3.6 V

• 20 29 - 36 ns

[2]

propagation delay LE to Qn; Figure 6 tpd

VCC = 1.2 V

• 100 - - - ns

VCC = 2.0 V

• 34 48 - 60 ns

VCC = 2.7 V

• 25 35 - 44 ns

[3]

VCC = 3.0 V to 3.6 V; CL = 15 pF

• 16 - - - ns

[3]

VCC = 3.0 V to 3.6 V

• 19 28 - 35 ns

HIGH to LOW

MR to Qn; Figure 9

tPHL propagation delay

VCC = 1.2 V

• 90 - - - ns

VCC = 2.0 V

• 31 43 - 53 ns

VCC = 2.7 V

• 23 31 - 39 ns

[3]

VCC = 3.0 V to 3.6 V; CL = 15 pF

• 14 - - - ns

[3]

VCC = 3.0 V to 3.6 V

• 17 25 - 31 ns

pulse width

LE, HIGH or LOW; see Figure 6

tW

VCC = 2.0 V

34 10 - 41 - ns

VCC = 2.7 V

25 8 - 30 - ns

[3]

VCC = 3.0 V to 3.6 V

20 6 - 24 - ns

pulse width

MR, LOW; see Figure 9

tW

VCC = 2.0 V

34 10 - 41 - ns

VCC = 2.7 V

25 8 - 30 - ns

[3]

VCC = 3.0 V to 3.6 V

20 6 - 24 - ns

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Page 8

Table 8. Dynamic characteristics …continued GND = 0 V; For test circuit see Figure 12.

tsu set-up time

D, An to LE; see Figure 10 and Figure 11 VCC = 1.2 V

• 35 - - - ns

VCC = 2.0 V

24 12 - 29 - ns

VCC = 2.7 V

18 9 - 21 - ns

[3]

VCC = 3.0 V to 3.6 V

14 7 - 17 - ns

hold time

D to LE; see Figure 10

th

VCC = 1.2 V

• −30 - - - ns

VCC = 2.0 V

5 −10 - 5 - ns

VCC = 2.7 V

5 −8 - 5 - ns

[3]

VCC = 3.0 V to 3.6 V

5 −6 - 5 - ns

hold time

An to LE; see Figure 11

th

VCC = 1.2 V

• −20 - - - ns

VCC = 2.0 V

5 −7 - 5 - ns

VCC = 2.7 V

5 −5 - 5 - ns

[3]

VCC = 3.0 V to 3.6 V

5 −4 - 5 - ns

[4]

power dissipation

CL = 50 pF; fi = 1 MHz;

19

pF

CPD capacitance

VI = GND to VCC

[1] Typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL. [3] Typical value measured at VCC = 3.3 V. [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs.

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11. Waveforms

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Page 10

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Table 9. Measurement points Supply voltage

Input

Output

VCC

VM

VM

< 2.7 V

0.5VCC

0.5VCC

2.7 V to 3.6 V

1.5 V

1.5 V

Table 10. Test data

< 2.7 V

VCC

≤ 2.5 ns

2.7 V to 3.6 V

2.7 V

≤ 2.5 ns

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Page 12

12. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

Fig 13. Package outline SOT38-4 (DIP16)

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Page 13

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

Fig 14. Package outline SOT109-1 (SO16)

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Page 14

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

Fig 15. Package outline SOT338-1 (SSOP16)

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TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

Fig 16. Package outline SOT403-1 (TSSOP16)

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Page 16

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT763-1

16 terminals; body 2.5 x 3.5 x 0.85 mm

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Fig 17. Package outline SOT763-1 (DHVQFN16)

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13. Abbreviations

Table 11. Abbreviations Acronym

Description

CMOS

Complementary Metal Oxide Semiconductor

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 12. Revision history Document ID

Release date

Data sheet status

Change notice

Supersedes

20080102

-

74LV259_2

• The format of this data sheet has been redesigned to comply with the new identity guidelines

Modifications:

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.
• Section 3: DHVQFN16 package added.
• Section 7: derating values added for DHVQFN16 package.
• Section 12: outline drawing added for DHVQFN16 package.

74LV259_2

19980520

Product specification -

74LV259_1

74LV259_1

19970606

Product specification -

-

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15. Legal information

15.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or

16. Contact information

For additional information, please visit: http://www.nxp.com

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, send an email to: salesaddresses@nxp.com

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17. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 Contact information. . . . . . . . . . . . . . . . . . . . . 18 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2008.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 January 2008 Document identifier: 74LV259_3