74LV164

74LV164_15 PHILIPS

Document overview

• PDF pages: 21

Technical content

Page 1

1. General description

The 74LV164 is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164.

The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB) and either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP) and enters into Q0, which is the logical AND-function of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge.

A LOW on the master reset input (MR) overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.

2. Features

I Wide operating voltage: 1.0 V to 5.5 V I Optimized for low-voltage applications: 1.0 V to 3.6 V I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V I Typical VOLP (output ground bounce): < 0.8 V at VCC = 3.3 V and Tamb = 25 °C I Typical VOHV (output VOH undershoot): > 2 V at VCC = 3.3 V and Tamb = 25 °C I Gated serial data inputs I Asynchronous master reset I ESD protection: N HBM EIA/JESD22-A114-B exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V. I Specified from −40 °C to +80 °C and from −40 °C to +125 °C.

3. Quick reference data

Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. Symbol Parameter

Conditions

Min Typ Max Unit

tPHL, propagation delay

VCC = 3.3 V; CL = 15 pF

tPLH CP to Qn

• 12 - ns

MR to Qn

• 12 - ns

Page 2

Table 1: Quick reference data …continued GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. Symbol Parameter

Conditions

Min Typ Max Unit

fmax maximum clock

VCC = 3.3 V; CL = 15 pF

• 78 - MHz

frequency input capacitance

• 3.5 -

pF

CI

[1] [2] -

power dissipation

VCC = 3.3 V

40 - pF

CPD capacitance per gate

[1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [2] The condition is VI = GND to VCC.

4. Ordering information

Table 2: Ordering information

74LV164N

−40 °C to +125 °C DIP14

plastic dual in-line package; 14 leads (300 mil)

SOT27-1

74LV164D

−40 °C to +125 °C SO14

plastic small outline package; 14 leads;

SOT108-1

body width 3.9 mm

74LV164DB −40 °C to +125 °C SSOP14

plastic shrink small outline package; 14 leads;

SOT337-1

body width 5.3 mm plastic thin shrink small outline package; 14 leads;

74LV164PW −40 °C to +125 °C TSSOP14

SOT402-1

body width 4.4 mm

74LV164BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very

SOT762-1

thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm

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5. Functional diagram

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Page 4

6. Pinning information

6.1 Pinning

6.2 Pin description

Table 3: Pin description Symbol Pin

Description

DSA

1

data input SA

DSB

2

data input SB

Q0

3

output 0

Q1

4

output 1

Q2

5

output 2

Q3

6

output 3

GND

7

ground (0 V) clock input (edge triggered LOW-to-HIGH)

CP

8

master reset input (active LOW)

MR

9

Q4

10

output 4

Q5

11

output 5

Q6

12

output 6

Q7

13

output 7

14

supply voltage

VCC

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Page 5

7. Functional description

7.1 Function table

Table 4: Function table [1]

Reset (clear)

L

X

X

X

L

L to L

Shift

H

l

l

L

q0 to q6

↑

H

l

h

L

q0 to q6

↑

H

h

l

L

q0 to q6

↑

H

h

h

H

q0 to q6

↑

[1] H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH clock transition; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; q = lower case letter indicates the state of referenced input one set-up time prior to the LOW-to-HIGH CP transition.

8. Limiting values

Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Max Unit

supply voltage

−0.5 +7.0 V

VCC input diode current

VI < −0.5 V or VI > VCC + 0.5 V

• ±20 mA

IIK output diode current

VO < −0.5 V or VO > VCC + 0.5 V

• ±50 mA

IOK

[1] -

output source or sink

VO = −0.5 V to (VCC + 0.5 V)

±25 mA

IO current ICC, VCC or GND current

• ±50 mA

IGND storage temperature

−65 +150 °C

Tstg total power dissipation

Tamb = −40 °C to +125 °C

Ptot

[2] - 750 mW

DIP14 package

[3] - 500 mW

SO14, (T)SSOP14 and DHVQFN14 packages

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C. [3] SO14 package: Ptot derates linearly with 8 mW/K above 70 °C. (T)SSOP14 package: Ptot derates linearly with 5.5 mW/K above 60 °C. DHVQFN14 package: Ptot derates linearly with 4.5 mW/K above 60 °C.

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Page 6

9. Recommended operating conditions

Table 6: Recommended operating conditions Symbol Parameter supply voltage VCC input voltage VI output voltage VO ambient temperature Tamb tr, tf input rise and fall times

Conditions

Min Typ Max Unit

[1] 1.0 3.3 5.5 V

0 - VCC V

0 - VCC V

in free air

−40 - +125 °C

VCC = 1.0 V to 2.0 V

• - 500 ns/V

VCC = 2.0 V to 2.7 V

• - 200 ns/V

VCC = 2.7 V to 3.6 V

• - 100 ns/V

VCC = 3.6 V to 5.5 V

• - 50 ns/V

[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC).

10. Static characteristics

Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = −40 °C to +85 °C [1] VIH HIGH-level input voltage

VCC = 1.2 V

0.9 - - V

VCC = 2.0 V

1.4 - - V

VCC = 2.7 V to 3.6 V

2.0 - - V

VCC = 4.5 V to 5.5 V

0.7 × VCC -

• V

LOW-level input voltage

VCC = 1.2 V

• - 0.3 V

VIL

VCC = 2.0 V

• - 0.6 V

VCC = 2.7 V to 3.6 V

• - 0.8 V

VCC = 4.5 V to 5.5 V

• - 0.3 × VCC V

HIGH-level output voltage

VI = VIH or VIL

VOH

lO = −100 µA; VCC = 1.2 V

• 1.2 - V

lO = −100 µA; VCC = 2.0 V

1.8 2.0 - V

lO = −100 µA; VCC = 2.7 V

2.5 2.7 - V

lO = −100 µA; VCC = 3.0 V

2.8 3.0 - V

lO = −6 mA; VCC = 3.0 V

2.40 2.82 -

V

lO = −100 µA; VCC = 4.5 V

4.3 4.5 - V

lO = −12 mA; VCC = 4.5 V

3.60 4.20 -

V

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Page 7

Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Typ Max Unit

VOL LOW-level output voltage

VI = VIH or VIL IO = 100 µA; VCC = 1.2 V

• 0 - V

IO = 100 µA; VCC = 2.0 V

• 0 0.2 V

IO = 100 µA; VCC = 2.7 V

• 0 0.2 V

IO = 100 µA; VCC = 3.0 V

• 0 0.2 V

IO = 6 mA; VCC = 3.0 V

• 0.25 0.40

V

IO = 100 µA; VCC = 4.5 V

• 0 0.2 V

IO = 12 mA; VCC = 4.5 V

• 0.35 0.55

V

input leakage current

VI = VCC or GND; VCC = 5.5 V

• - 1.0 µA

ILI quiescent supply current

VI = VCC or GND; IO = 0 A;

• - 20.0 µA

ICC

VCC = 5.5 V

additional quiescent supply

VI = VCC − 0.6 V; VCC = 2.7 V

• - 500 µA

∆ICC current per input

to 3.6 V

input capacitance

• 3.5 - pF

CI Tamb = −40 °C to +125 °C HIGH-level input voltage

VCC = 1.2 V

0.9 - - V

VIH

VCC = 2.0 V

1.4 - - V

VCC = 2.7 V to 3.6 V

2.0 - - V

VCC = 4.5 V to 5.5 V

0.7 × VCC -

• V

LOW-level input voltage

VCC = 1.2 V

• - 0.3 V

VIL

VCC = 2.0 V

• - 0.6 V

VCC = 2.7 V to 3.6 V

• - 0.8 V

VCC = 4.5 V to 5.5 V

• - 0.3 × VCC V

HIGH-level output voltage

VI = VIH or VIL

VOH

lO = −100 µA; VCC = 1.2 V

• - - V

lO = −100 µA; VCC = 2.0 V

1.8 - - V

lO = −100 µA; VCC = 2.7 V

2.5 - - V

lO = −100 µA; VCC = 3.0 V

2.8 - - V

lO = −6 mA; VCC = 3.0 V

2.20 - - V

lO = −100 µA; VCC = 4.5 V

4.3 - - V

lO = −12 mA; VCC = 4.5 V

3.50 - - V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 100 µA; VCC = 1.2 V

• - - V

IO = 100 µA; VCC = 2.0 V

• - 0.2 V

IO = 100 µA; VCC = 2.7 V

• - 0.2 V

IO = 100 µA; VCC = 3.0 V

• - 0.2 V

IO = 6 mA; VCC = 3.0 V

• - 0.50 V

IO = 100 µA; VCC = 4.5 V

• - 0.2 V

IO = 12 mA; VCC = 4.5 V

• - 0.65 V

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Page 8

Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Typ Max Unit

ILI input leakage current

VI = VCC or GND; VCC = 5.5 V

• - 1.0 µA

quiescent supply current

VI = VCC or GND; IO = 0 A;

• - 160 µA

ICC

VCC = 5.5 V

additional quiescent supply

VI = VCC − 0.6 V; VCC = 2.7 V

• - 850 µA

∆ICC current per input

to 3.6 V

[1] All typical values are measured at Tamb = 25 °C.

11. Dynamic characteristics

Table 8: Dynamic characteristics GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 kΩ; for test circuit see Figure 9. Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = −40 °C to +85 °C [1] tPHL, propagation delay CP to Qn

see Figure 6

tPLH

VCC = 1.2 V

• 75 - ns

VCC = 2.0 V

• 26 39 ns

VCC = 2.7 V

• 19 29 ns

VCC = 3.0 V to 3.6 V

• 14 23 ns

VCC = 4.5 V to 5.5 V

• 12 19 ns

VCC = 3.3 V; CL = 15 pF

• 12 - ns

propagation delay MR to Qn see Figure 7 tPHL

VCC = 1.2 V

• 75 - ns

VCC = 2.0 V

• 26 39 ns

VCC = 2.7 V

• 19 29 ns

VCC = 3.0 V to 3.6 V

• 14 23 ns

VCC = 4.5 V to 5.5 V

• 12 19 ns

VCC = 3.3 V; CL = 15 pF

• 12 - ns

pulse width CP

see Figure 6

tW

VCC = 2.0 V

34 9 - ns

VCC = 2.7 V

25 6 - ns

VCC = 3.0 V to 3.6 V

20 5 - ns

VCC = 4.5 V to 5.5 V

13 4 - ns

pulse width MR

see Figure 7

tW

VCC = 2.0 V

34 10 - ns

VCC = 2.7 V

25 8 - ns

VCC = 3.0 V to 3.6 V

20 6 - ns

VCC = 4.5 V to 5.5 V

13 5 - ns

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Page 9

Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 kΩ; for test circuit see Figure 9. Symbol Parameter

Conditions

Min Typ Max Unit

trem removal time MR to CP

see Figure 7 VCC = 1.2 V

• 30 - ns

VCC = 2.0 V

19 10 - ns

VCC = 2.7 V

14 8 - ns

VCC = 3.0 V to 3.6 V

11 6 - ns

VCC = 4.5 V to 5.5 V

8 5 - ns

set-up time Dn to CP

see Figure 8

tsu

VCC = 1.2 V

• 15 - ns

VCC = 2.0 V

22 5 - ns

VCC = 2.7 V

16 4 - ns

VCC = 3.0 V to 3.6 V

13 3 - ns

VCC = 4.5 V to 5.5 V

9 2 - ns

hold time Dn to CP

see Figure 8

th

VCC = 1.2 V

• −10 - ns

VCC = 2.0 V

5 −3 - ns

VCC = 2.7 V

5 −2 - ns

VCC = 3.0 V to 3.6 V

5 −2 - ns

VCC = 4.5 V to 5.5 V

5 −1 - ns

maximum clock frequency

see Figure 6

fmax

VCC = 2.0 V

14 40 - MHz

VCC = 2.7 V

19 58 - MHz

VCC = 3.0 V to 3.6 V

24 70 - MHz

VCC = 4.5 V to 5.5 V

36 100 - MHz

VCC = 3.3 V; CL = 15 pF

• 78 - MHz

[2] [3] -

power dissipation capacitance

VCC = 3.3 V

40 - pF

CPD per gate Tamb = −40 °C to +125 °C tPHL, propagation delay CP to Qn

see Figure 6

tPLH

VCC = 1.2 V

• - - ns

VCC = 2.0 V

• - 49 ns

VCC = 2.7 V

• - 36 ns

VCC = 3.0 V to 3.6 V

• - 29 ns

VCC = 4.5 V to 5.5 V

• - 24 ns

propagation delay MR to Qn see Figure 7 tPHL

VCC = 1.2 V

• - - ns

VCC = 2.0 V

• - 49 ns

VCC = 2.7 V

• - 36 ns

VCC = 3.0 V to 3.6 V

• - 29 ns

VCC = 4.5 V to 5.5 V

• - 24 ns

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Page 10

Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 kΩ; for test circuit see Figure 9. Symbol Parameter

Conditions

Min Typ Max Unit

tW pulse width CP

see Figure 6 VCC = 2.0 V

41 - - ns

VCC = 2.7 V

30 - - ns

VCC = 3.0 V to 3.6 V

24 - - ns

VCC = 4.5 V to 5.5 V

16 - - ns

pulse width MR

see Figure 7

tW

VCC = 2.0 V

41 - - ns

VCC = 2.7 V

30 - - ns

VCC = 3.0 V to 3.6 V

24 - - ns

VCC = 4.5 V to 5.5 V

16 - - ns

removal time MR to CP

see Figure 7

trem

VCC = 1.2 V

• - - ns

VCC = 2.0 V

24 - - ns

VCC = 2.7 V

18 - - ns

VCC = 3.0 V to 3.6 V

14 - - ns

VCC = 4.5 V to 5.5 V

10 - - ns

set-up time Dn to CP

see Figure 8

tsu

VCC = 1.2 V

• - - ns

VCC = 2.0 V

26 - - ns

VCC = 2.7 V

19 - - ns

VCC = 3.0 V to 3.6 V

15 - - ns

VCC = 4.5 V to 5.5 V

10 - - ns

hold time Dn to CP

see Figure 8

th

VCC = 1.2 V

• - - ns

VCC = 2.0 V

5 - - ns

VCC = 2.7 V

5 - - ns

VCC = 3.0 V to 3.6 V

5 - - ns

VCC = 4.5 V to 5.5 V

5 - - ns

maximum clock frequency

see Figure 6

fmax

VCC = 2.0 V

12 - - MHz

VCC = 2.7 V

16 - - MHz

VCC = 3.0 V to 3.6 V

20 - - MHz

VCC = 4.5 V to 5.5 V

30 - - MHz

[1] Typical values are measured at nominal VCC and Tamb = 25 °C.

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[2] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [3] The condition is VI = GND to VCC.

12. Waveforms

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Table 9: Measurement points

1.2 V

0.5 × VCC

0.5 × VCC

2.0 V

0.5 × VCC

0.5 × VCC

2.7 V

1.5 V

1.5 V

3.0 V to 3.6 V

1.5 V

1.5 V 0.5 × VCC

4.5 V to 5.5 V

0.5 × VCC

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Page 13

Table 10: Test data

1.2 V

VCC

≤ 2.5 ns

50 pF

1 kΩ

tPHL, tPLH

2.0 V

VCC

≤ 2.5 ns

50 pF

1 kΩ

tPHL, tPLH

2.7 V

2.7 V

≤ 2.5 ns

50 pF

1 kΩ

tPHL, tPLH

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF, 15 pF 1 kΩ

tPHL, tPLH

4.5 V to 5.5 V

VCC

≤ 2.5 ns

50 pF

1 kΩ

tPHL, tPLH

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Page 14

13. Package outline

DIP14: plastic dual in-line package; 14 leads (300 mil)

SOT27-1

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

Fig 10. Package outline SOT27-1 (DIP14)

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SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

Fig 11. Package outline SOT108-1 (SO14)

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SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm

SOT337-1

Fig 12. Package outline SOT337-1 (SSOP14)

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TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

Fig 13. Package outline SOT402-1 (TSSOP14)

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DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT762-1

14 terminals; body 2.5 x 3 x 0.85 mm

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Fig 14. Package outline SOT762-1 (DHVQFN14)

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14. Revision history

Table 11: Revision history Document ID

Release date Data sheet status

Change notice Doc. number

Supersedes

74LV164_3

20050204

-

74LV164_2

• The format of this data sheet has been redesigned to comply with the current presentation and

Modifications:

information standard of Philips Semiconductors

• Added: type number 74LV164BQ (DHVQFN14 package).

74LV164_2

19980507

Product specification -

9397 750 04431

74LV164_1

74LV164_1

19970328

Product specification

-

-

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15. Data sheet status

Level Data sheet status [1] Product status [2] [3] Definition

This data sheet contains data from the objective specification for product development. Philips

I Objective data

Development

Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published

II Preliminary data

Qualification

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the

III Product data

Production

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

18. Contact information

17. Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

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19. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Recommended operating conditions. . . . . . . . 6 10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 17 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

18 Contact information . . . . . . . . . . . . . . . . . . . . 20

© Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Date of release: 4 February 2005 Document number: 9397 750 14501

Published in The Netherlands