74LV132D

74LV132_09 NXP

Document overview

• PDF pages: 17

Technical content

Page 1

1. General description

The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132 and 74HCT132.

The 74LV132 contains four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

The gate switches at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the input hysteresis voltage VH.

2. Features

I Wide operating voltage: 1.0 V to 5.5 V I Optimized for low voltage applications: 1.0 V to 3.6 V I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C

3. Applications

I Wave and pulse shapers for highly noisy environments I Astable multivibrators I Monostable multivibrators

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4. Ordering information

Table 1. Ordering information

74LV132N

−40 °C to +125 °C DIP14

74LV132D

−40 °C to +125 °C SO14

74LV132DB

−40 °C to +125 °C SSOP14

plastic dual in-line package; 14 leads (300 mil)

SOT27-1

plastic small outline package; 14 leads;

SOT108-1

body width 3.9 mm plastic shrink small outline package; 14 leads;

SOT337-1

body width 5.3 mm

−40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

74LV132PW

SOT402-1

body width 4.4 mm

−40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very

SOT762-1

74LV132BQ

thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm

5. Functional diagram

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6. Pinning information

6.1 Pinning

6.2 Pin description

Table 2. Pin description Symbol

Pin

Description

1A

1

data input

1B

2

data input

1Y

3

data output

2A

4

data input

2B

5

data input

2Y

6

data output

GND

7

ground (0 V)

3Y

8

data output

3A

9

data input

3B

10

data input

4Y

11

data output

4A

12

data input

4B

13

data input

14

supply voltage

VCC

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7. Functional description

Table 3. Function table H = HIGH voltage level; L = LOW voltage level.

L

L

H

L

H

H

H

L

H

H

H

L

8. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Max Unit

supply voltage

−0.5 +7.0 V

VCC

[1] -

VI < −0.5 V or VI > VCC + 0.5 V

input clamping current

±20 mA

IIK

[1] -

VO < −0.5 V or VO > VCC + 0.5 V

output clamping current

±50 mA

IOK

VO = −0.5 V to (VCC + 0.5 V)

output current

• ±25 mA

IO

supply current

• 50 mA

ICC

ground current

−50 - mA

IGND

storage temperature

−65 +150 °C

Tstg

total power dissipation

Tamb = −40 °C to +125 °C

Ptot

[2] -

750 mW

DIP14 package

[3] -

500 mW

SO14 package

[4] -

500 mW

(T)SSOP14 package

[5] -

500 mW

DHVQFN14 package

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 °C. [3] Ptot derates linearly with 8 mW/K above 70 °C. [4] Ptot derates linearly with 5.5 mW/K above 60 °C. [5] Ptot derates linearly with 4.5 mW/K above 60 °C.

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9. Recommended operating conditions

Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Typ Max Unit

supply voltage[1]

1.0

3.3

5.5

V

VCC

input voltage

0

-

VCC V

VI

output voltage

0

-

VCC V

VO

ambient temperature

−40

+25

+125 °C

Tamb

[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC).

10. Static characteristics

Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V).

HIGH-level output voltage

VI = VT+ or VT−

VOH

lO = −100 µA; VCC = 1.2 V

• 1.2 - - - V

lO = −100 µA; VCC = 2.0 V

1.8 2.0 - 1.8 - V

lO = −100 µA; VCC = 2.7 V

2.5 2.7 - 2.5 - V

lO = −100 µA; VCC = 3.0 V

2.8 3.0 - 2.8 - V

lO = −100 µA; VCC = 4.5 V

4.3 4.5 - 4.3 - V

lO = −6 mA; VCC = 3.0 V

2.4 2.82 - 2.2 - V

lO = −12 mA; VCC = 4.5 V

3.6 4.2 - 3.5 - V

LOW-level output voltage

VI = VT+ or VT−

VOL

IO = 100 µA; VCC = 1.2 V

• 0 - - - V

IO = 100 µA; VCC = 2.0 V

• 0 0.2 - 0.2 V

IO = 100 µA; VCC = 2.7 V

• 0 0.2 - 0.2 V

IO = 100 µA; VCC = 3.0 V

• 0 0.2 - 0.2 V

IO = 100 µA; VCC = 4.5 V

• 0 0.2 - 0.2 V

IO = 6 mA; VCC = 3.0 V

• 0.25 0.40
• 0.50 V

IO = 12 mA; VCC = 4.5 V

• 0.35 0.55
• 0.65 V

input leakage current

VI = VCC or GND;

• - 1.0 - 1.0 µA

II

VCC = 5.5 V

supply current

VI = VCC or GND; IO = 0 A;

• - 20.0 - 40 µA

ICC

VCC = 5.5 V

additional supply current

per input; VI = VCC − 0.6 V;

• - 500 - 850 µA

∆ICC

VCC = 2.7 V to 3.6 V

input capacitance

• 3.5 - - - pF

CI

[1] Typical values are measured at Tamb = 25 °C.

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11. Dynamic characteristics

Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 7.

[2]

propagation delay nA, nB to nY; see Figure 6 tpd

VCC = 1.2 V

• 65 - - - ns

VCC = 2.0 V

• 18 34 - 43 ns

VCC = 2.7 V

• 15 24 - 30 ns

[3]

VCC = 3.0 V to 3.6 V; CL = 15 pF

• 10 - - - ns

[3]

VCC = 3.0 V to 3.6 V

• 12 20 - 25 ns

[3]

VCC = 4.5 V to 5.5 V

• 9.0 14 - 17 ns

[4]

power dissipation

CL = 50 pF; fi = 1 MHz;

• 24 - - - pF

CPD capacitance

VI = GND to VCC

[1] All typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL. [3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz, fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs.

12. Waveforms

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Page 7

Table 8. Measurement points Supply voltage

Input

Output

VCC

VM

VM

< 2.7 V

0.5VCC

0.5VCC

2.7 V to 3.6 V

1.5 V

1.5 V 0.5VCC

≥ 4.5 V

0.5VCC

Table 9. Test data

< 2.7 V

VCC

≤ 2.5 ns

2.7 V to 3.6 V

2.7 V

≤ 2.5 ns ≤ 2.5 ns

≥ 4.5 V

VCC

13. Transfer characteristics

Table 10. Transfer characteristics GND = 0 V; For test circuit see Figure 7.

positive-going

see Figure 6

VT+ threshold voltage

VCC = 1.2 V

• 0.70 - - - V

VCC = 2.0 V

0.8 1.10 1.4 0.8 1.4 V

VCC = 2.7 V

1.0 1.45 2.0 1.0 2.0 V

VCC = 3.0 V

1.2 1.60 2.2 1.2 2.2 V

VCC = 3.6 V

1.5 1.95 2.4 1.5 2.4 V

VCC = 4.5 V

1.7 2.50 3.2 1.7 3.2 V

VCC = 5.5 V

2.1 3.00 3.9 2.1 3.9 V

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Table 10. Transfer characteristics …continued GND = 0 V; For test circuit see Figure 7.

VT− negative-going

see Figure 6

threshold voltage

VCC = 1.2 V

• 0.34 - - - V

VCC = 2.0 V

0.3 0.65 0.9 0.3 0.9 V

VCC = 2.7 V

0.4 0.90 1.4 0.4 1.4 V

VCC = 3.0 V

0.6 1.05 1.5 0.6 1.5 V

VCC = 3.6 V

0.8 1.30 1.8 0.8 1.8 V

VCC = 4.5 V

0.9 1.60 2.0 0.9 2.0 V

VCC = 5.5 V

1.2 2.00 2.6 1.2 2.6 V

hysteresis voltage

(VT+ − VT−); see Figure 6

VH

VCC = 1.2 V

• 0.3 - - - V

VCC = 2.0 V

0.2 0.55 0.8 0.2 0.8 V

VCC = 2.7 V

0.3 0.60 1.1 0.3 1.1 V

VCC = 3.0 V

0.4 0.65 1.2 0.4 1.2 V

VCC = 3.6 V

0.4 0.70 1.2 0.4 1.2 V

VCC = 4.5 V

0.4 0.80 1.4 0.4 1.4 V

VCC = 5.5 V

0.6 1.00 1.5 0.6 1.5 V

[1] All typical values are measured at Tamb = 25 °C.

14. Waveforms transfer characteristics

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15. Package outline

DIP14: plastic dual in-line package; 14 leads (300 mil)

SOT27-1

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

Fig 13. Package outline SOT27-1 (DIP14)

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SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

Fig 14. Package outline SOT108-1 (SO14)

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SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm

SOT337-1

Fig 15. Package outline SOT337-1 (SSOP14)

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TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

Fig 16. Package outline SOT402-1 (TSSOP14)

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DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT762-1

14 terminals; body 2.5 x 3 x 0.85 mm

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Fig 17. Package outline SOT762-1 (DHVQFN14)

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16. Abbreviations

Table 11. Abbreviations Acronym

Description

CMOS

Complementary Metal Oxide Semiconductor

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

17. Revision history

Table 12. Revision history Document ID

Release date

Data sheet status

Change notice

Supersedes

20090702

-

74LV132_4

• Table 6: the conditions for HIGH-level output voltage and LOW-level output voltage have been

Modifications:

changed.

74LV132_4

20071112

-

74LV132_3

74LV132_3

20040415

Product specification -

74LV132_2

74LV132_2

19980428

Product specification -

74LV132_1

74LV132_1

19970204

Product specification -

-

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18. Legal information

18.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

18.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental

19. Contact information

For more information, please visit: http://www.nxp.com

damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, please send an email to: salesaddresses@nxp.com

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20. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

9 Recommended operating conditions. . . . . . . . 5 10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Transfer characteristics. . . . . . . . . . . . . . . . . . . 7 14 Waveforms transfer characteristics . . . . . . . . . 8 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15 17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16

18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 19 Contact information. . . . . . . . . . . . . . . . . . . . . 16 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2009.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 July 2009 Document identifier: 74LV132_5