74LV123D

74LV123 NXP

Document overview

• PDF pages: 23

Technical content

Page 1

1. General description

The 74LV123 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC123; 74HCT123. It is a dual retriggerable monostable multivibrator which uses three methods to control the output pulse width:

1. The basic pulse time is programmed by the selection of an external resistor (REXT) and capacitor (CEXT). These are normally connected as shown in Figure 9. 2. Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired (see Figure 12). 3. Alternatively, an output delay can be terminated at any time by a LOW-going edge on input nRD, which also inhibits the triggering (see Figure 13).

Schmitt-trigger action in the nA and nB inputs makes the circuit highly tolerant of slower input rise and fall times.

2. Features

I Optimized for low-voltage applications: 1.0 V to 5.5 V I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V I Typical output ground bounce: < 0.8 V at VCC = 3.3 V and Tamb = 25 °C I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C I DC triggered from active HIGH or active LOW inputs I Retriggerable for very long pulses up to 100 % duty factor I Direct reset terminates output pulses I Schmitt-trigger action on all inputs except for the reset input

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3. Ordering information

Table 1. Ordering information

plastic dual in-line package; 16 leads (300 mil)

74LV123N

−40 °C to +125 °C DIP16

SOT38-4

plastic small outline package; 16 leads; body width

74LV123D

−40 °C to +125 °C SO16

SOT109-1

3.9 mm plastic shrink small outline package; 16 leads; body width

74LV123DB −40 °C to +125 °C SSOP16

SOT338-1

5.3 mm

74LV123PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body

SOT403-1

width 4.4 mm

74LV123BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin

SOT763-1

quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm

4. Functional diagram

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Page 5

5. Pinning information

5.1 Pinning

5.2 Pin description

Table 2. Pin description Symbol

Pin

1A

1

1B

2

1RD

3

1Q

4

2Q

5

2CEXT

6

2REXT/CEXT

7

GND

8

2A

9

2B

10

2RD

11

2Q

12

1Q

13

1CEXT

14

1REXT/CEXT

15 16

VCC

Description

negative-edge triggered input 1 positive-edge triggered input 1 direct reset LOW and positive-edge triggered input 1 active LOW output 1 active HIGH output 2 external capacitor connection 2 external resistor and capacitor connection 2 ground (0 V) negative-edge triggered input 2 positive-edge triggered input 2 direct reset LOW and positive-edge triggered input 2 active LOW output 2 active HIGH output 1 external capacitor connection 1 external resistor and capacitor connection 1 supply voltage

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Page 6

6. Functional description

Table 3. Function table[1]

L

X

X

L

H

L[2]

H[2]

X

H

X

L[2]

H[2]

X

X

L

[2] If the monostable multivibrator was triggered before this condition was established, the pulse will continue as programmed.

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Page 7

7. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Max Unit

supply voltage

−0.5 +7 V

VCC

[1] -

input clamping current

VI < −0.5 V or VI > VCC + 0.5 V

±20 mA

IIK

[1] -

output clamping current

VO < −0.5 V or VO > VCC + 0.5 V

±50 mA

IOK

[1] -

output current

except for pins nREXT/CEXT;

±25 mA

IO

VO = −0.5 V to (VCC + 0.5 V)

supply current

• +50 mA

ICC

ground current

• −50 mA

IGND

storage temperature

−65 +150 °C

Tstg

total power dissipation

Tamb = −40 °C to +125 °C

Ptot

[2] -

750 mW

DIP16 package

[3] -

500 mW

SO16 package

[4] -

500 mW

SSOP16 package

[4] -

500 mW

TSSOP16 package

[5] -

500 mW

DHVQFN16 package

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. [3] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. [4] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. [5] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 °C.

8. Recommended operating conditions

Table 5. Recommended operating conditions Symbol Parameter

Conditions

Min Typ Max Unit

[1] 1.0

supply voltage

3.3 5.5 V

VCC input voltage

0 - VCC V

VI output voltage

0 - VCC V

VO ambient temperature

in free air

−40 +25 +125 °C

Tamb input transition rise and fall rate[2]

VCC = 1.0 V to 2.0 V

• - 500 ns/V

∆t/∆V

VCC = 2.0 V to 2.7 V

• - 200 ns/V

VCC = 2.7 V to 3.6 V

• - 100 ns/V

VCC = 3.6 V to 5.5 V

• - 50 ns/V

[1] The 74LV123 is guaranteed to function down to VCC = 1.0 V (input levels GND or VCC); Section 9 “Static characteristics” are guaranteed from VCC = 1.2 V to VCC = 5.5 V. [2] Except for Schmitt-trigger inputs nA and nB.

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9. Static characteristics

Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Typ[1] Max

Symbol Parameter

Conditions

Min

Unit

Tamb = −40 °C to +85 °C HIGH-level input voltage

VCC = 1.2 V

0.9 - -

V

VIH

VCC = 2.0 V

1.4 - -

V

VCC = 2.7 V to 3.6 V

2.0 - -

V

VCC = 4.5 V to 5.5 V

0.7 × VCC - -

V

LOW-level input voltage

VCC = 1.2 V

• - 0.3

V

VIL

VCC = 2.0 V

• - 0.6

V

VCC = 2.7 V to 3.6 V

• - 0.8

V

VCC = 4.5 V to 5.5 V

• - 0.3 × VCC

V

HIGH-level output voltage

VI = VIH or VIL

VOH

lO = −100 µA; VCC = 1.2 V

• 1.2 -

V

lO = −100 µA; VCC = 2.0 V

1.8 2.0 -

V

lO = −100 µA; VCC = 2.7 V

2.5 2.7 -

V

lO = −100 µA; VCC = 3.0 V

2.8 3.0 -

V

lO = −100 µA; VCC = 4.5 V

4.3 4.5 -

V

lO = −6 mA; VCC = 3.0 V

2.40 2.82 -

V

lO = −12 mA; VCC = 4.5 V

3.60 4.20 -

V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 100 µA; VCC = 1.2 V

• 0 -

V

IO = 100 µA; VCC = 2.0 V

• 0 0.2

V

IO = 100 µA; VCC = 2.7 V

• 0 0.2

V

IO = 100 µA; VCC = 3.0 V

• 0 0.2

V

IO = 100 µA; VCC = 4.5 V

• 0 0.2

V

IO = 6 mA; VCC = 3.0 V

• 0.25 0.40

V

IO = 12 mA; VCC = 4.5 V

• 0.35 0.55

V

input leakage current

VI = VCC or GND; VCC = 5.5 V

• - 1.0

µA

II supply current

VI = VCC or GND; IO = 0 A; VCC = 5.5 V

• - 20.0

µA

ICC additional supply current

VI = VCC − 0.6 V; VCC = 2.7 V to 3.6 V

• - 500

µA

∆ICC input capacitance

• 3.5 -

pF

CI Tamb = −40 °C to +125 °C HIGH-level input voltage

VCC = 1.2 V

0.9 - -

V

VIH

VCC = 2.0 V

1.4 - -

V

VCC = 2.7 V to 3.6 V

2.0 - -

V

VCC = 4.5 V to 5.5 V

0.7 × VCC - -

V

LOW-level input voltage

VCC = 1.2 V

• - 0.3

V

VIL

VCC = 2.0 V

• - 0.6

V

VCC = 2.7 V to 3.6 V

• - 0.8

V

VCC = 4.5 V to 5.5 V

• - 0.3 × VCC

V

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Page 9

Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Typ[1] Max

Symbol Parameter

Conditions

Min

Unit

VOH HIGH-level output voltage

VI = VIH or VIL lO = −100 µA; VCC = 1.2 V

• - -

V

lO = −100 µA; VCC = 2.0 V

1.8 - -

V

lO = −100 µA; VCC = 2.7 V

2.5 - -

V

lO = −100 µA; VCC = 3.0 V

2.8 - -

V

lO = −100 µA; VCC = 4.5 V

4.3 - -

V

lO = −6 mA; VCC = 3.0 V

2.2 - -

V

lO = −12 mA; VCC = 4.5 V

3.5 - -

V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 100 µA; VCC = 1.2 V

• - -

V

IO = 100 µA; VCC = 2.0 V

• - 0.2

V

IO = 100 µA; VCC = 2.7 V

• - 0.2

V

IO = 100 µA; VCC = 3.0 V

• - 0.2

V

IO = 100 µA; VCC = 4.5 V

• - 0.2

V

IO = 6 mA; VCC = 3.0 V

• - 0.5

V

IO = 12 mA; VCC = 4.5 V

• - 0.65

V

input leakage current

VI = VCC or GND; VCC = 5.5 V

• - 1.0

µA

II supply current

VI = VCC or GND; IO = 0 A; VCC = 5.5 V

• - 160

µA

ICC additional supply current

VI = VCC − 0.6 V; VCC = 2.7 V to 3.6 V

• - 850

µA

∆ICC

[1] All typical values are measured at Tamb = 25 °C.

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Page 10

10. Dynamic characteristics

Table 7. Dynamic characteristics GND = 0 V; tr = tf ≤ 2.5 ns; for test circuit see Figure 8.

Propagation delay; see Figure 7

[2]

propagation delay nRD, nA and nB to nQ tpd

VCC = 1.2 V

• 120 - - - ns

VCC = 2.0 V

• 40 76 - 92 ns

VCC = 2.7 V

• 30 56 - 68 ns

VCC = 3.0 V to 3.6 V

• 25 48 - 57 ns

VCC = 4.5 V to 5.5 V

• 18 40 - 46 ns

[2]

nRD to nQ (reset) VCC = 1.2 V

• 100 - - - ns

VCC = 2.0 V

• 30 57 - 68 ns

VCC = 2.7 V

• 23 43 - 51 ns

VCC = 3.0 V to 3.6 V

• 20 38 - 45 ns

VCC = 4.5 V to 5.5 V

• 14 31 - 36 ns

Inputs nA, nB and nRD; see Figure 7 pulse width

nA = LOW

tW

VCC = 2.0 V

30 5 - 40 - ns

VCC = 2.7 V

25 3.5

• 30 - ns

VCC = 3.0 V to 3.6 V

20 3.0

• 25 - ns

VCC = 4.5 V to 5.5 V

15 2.5

• 20 - ns

nB = HIGH VCC = 2.0 V

30 13 - 40 - ns

VCC = 2.7 V

25 8 - 30 - ns

VCC = 3.0 V to 3.6 V

20 7 - 25 - ns

VCC = 4.5 V to 5.5 V

15 5 - 20 - ns

nRD = LOW; see Figure 13 VCC = 2.0 V

35 6 - 45 - ns

VCC = 2.7 V

30 5 - 40 - ns

VCC = 3.0 V to 3.6 V

25 4 - 30 - ns

VCC = 4.5 V to 5.5 V

20 3 - 25 - ns

retrigger time

nB to nA; see Figure 12

trtrig

VCC = 2.0 V

• 70 - - - ns

VCC = 2.7 V

• 55 - - - ns

VCC = 3.0 V to 3.6 V

• 45 - - - ns

VCC = 4.5 V to 5.5 V

• 40 - - - ns

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Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf ≤ 2.5 ns; for test circuit see Figure 8.

Outputs; nQ = LOW and nQ = HIGH, see Figure 7 pulse width

CEXT = 100 nF; REXT = 10 kΩ

tW

VCC = 2.0 V

• 470 - - - ns

VCC = 2.7 V

• 460 - - - ns

VCC = 3.0 V to 3.6 V

• 450 - - - ns

VCC = 4.5 V to 5.5 V

• 430 - - - ns

CEXT = 0 pF; REXT = 5 kΩ VCC = 2.0 V

• 100 - - - ns

VCC = 2.7 V

• 90 - - - ns

VCC = 3.0 V to 3.6 V

• 80 - - - ns

VCC = 4.5 V to 5.5 V

• 70 - - - ns

External components

[3]

external

see Figure 11

REXT resistance

VCC = 1.2 V

10 - 1000

• - kΩ

VCC = 2.0 V

5 - 1000

• - kΩ

VCC = 2.7 V

3 - 1000

• - kΩ

VCC = 3.0 V to 3.6 V

2 - 1000

• - kΩ

VCC = 4.5 V to 5.5 V

2 - 1000

• - kΩ

[3][4]

external

see Figure 11

CEXT capacitance

VCC = 1.2 V

• - - - - pF

VCC = 2.0 V

• - - - - pF

VCC = 2.7 V

• - - - - pF

VCC = 3.0 V to 3.6 V

• - - - - pF

VCC = 4.5 V to 5.5 V

• - - - - pF

Dynamic power dissipation

[5]

power dissipation

VCC = 3.3 V; VI = GND to VCC

• 60 - - - pF

CPD capacitance

[1] All typical values are measured at Tamb = 25 °C and nominal supply values (VCC = 3.3 V and 5.0 V). [2] tpd is the same as tPLH and tPHL; CEXT = 0 pF; REXT = 5 kΩ. [3] For other REXT and CEXT combinations see Figure 11 and Section 12.1.1 “Basic timing”. [4] CEXT has no limits. [5] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs.

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11. Waveforms

Table 8. Measurement points VCC

VM

≥ 2.7 V

1.5 V

< 2.7 V

0.5 × VCC

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Table 9. Test data

< 2.7 V

VCC

≤ 2.5 ns

50 pF

1 kΩ

tPHL, tPLH

2.7 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

1 kΩ

tPHL, tPLH

≥ 4.5 V

VCC

≤ 2.5 ns

50 pF

1 kΩ

tPHL, tPLH

12. Application information

12.1 Timing components

12.1.1 Basic timing The basic output pulse width is essentially determined by the values of the external timing components REXT and CEXT.

If CEXT > 10 nF, the following formula is valid: tW = K × REXT × CEXT (typ.) where:

tW = output pulse width in ns REXT = external resistor in kΩ CEXT = external capacitor in pF K = constant: this is 0.45 for VCC = 5.0 V and 0.48 for VCC = 2.0 V (see Figure 10)

The inherent test jig and pin capacitance at pin 15 and pin 7 (nREXT/CEXT) is approximately 7 pF.

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Page 14

12.1.2 Retrigger timing

The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width will only be extended when the time between the active going edges of the trigger pulses meets the minimum retrigger time. If CEXT > 10 pF, the next formula for the set-up time of a retrigger pulse is valid:

at VCC = 5.0 V: trtrig = 30 + 0.19REXT × CEXT0.9 + 13 × REXT1.05 (typ.) at VCC = 3.0 V: trtrig = 41 + 0.15REXT × CEXT0.9 × 1 × REXT (typ.)

where:

trtrig = retrigger time in ns CEXT = external capacitor in pF REXT = external resistor in kΩ

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12.1.3 Reset timing

12.2 Power considerations

12.2.1 Power-up When the monostable multivibrator is powered-up, it may produce an output pulse with a pulse width defined by the values of REXT and CEXT. This output pulse can be eliminated using the RC circuit on pin nRD shown in Figure 14.

12.2.2 Power-down A large capacitor (CEXT) may cause problems when powering-down the monostable due to the energy stored in this capacitor. When a system containing this device is powered-down or a rapid decrease of VCC to zero occurs, the monostable may sustain damage, due to the capacitor discharging through the input protection diodes. To avoid this possibility, connect a damping diode DEXT (preferably a germanium or Schottky type diode) able to withstand large current surges - see Figure 14.

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13. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

Fig 15. Package outline SOT38-4 (DIP16)

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SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

Fig 16. Package outline SOT109-1 (SO16)

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SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

Fig 17. Package outline SOT338-1 (SSOP16)

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TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

Fig 18. Package outline SOT403-1 (TSSOP16)

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DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT763-1

16 terminals; body 2.5 x 3.5 x 0.85 mm

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Fig 19. Package outline SOT736-1 (DHVQFN16)

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14. Revision history

Table 10. Revision history Document ID

Release date

Data sheet status

Change notice

Supersedes

20071108

-

74LV123_4

• Changed: SOT38-1 changed into SOT38-4

Modifications: 74LV123_4

20070919

Product specification

-

74LV123_3

74LV123_3

20030313

Product specification

-

74LV123_2

74LV123_2

19980420

Product specification

-

74LV123_1

74LV123_1

19970204

Product specification

-

-

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15. Legal information

15.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or

16. Contact information

For additional information, please visit: http://www.nxp.com

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, send an email to: salesaddresses@nxp.com

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17. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 Recommended operating conditions. . . . . . . . 7

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 Application information. . . . . . . . . . . . . . . . . . 13 12.1 Timing components . . . . . . . . . . . . . . . . . . . . 13 12.1.1 Basic timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12.1.2 Retrigger timing . . . . . . . . . . . . . . . . . . . . . . . 14 12.1.3 Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15 12.2 Power considerations . . . . . . . . . . . . . . . . . . . 15 12.2.1 Power-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

12.2.2 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 15 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 16 Contact information. . . . . . . . . . . . . . . . . . . . . 22 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2007.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 November 2007 Document identifier: 74LV123_5