74LS161

DM74LS161A FAIRCHILD

Document overview

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Technical content

Features

■ Synchronously programmable ■ Internal look-ahead for fast counting ■ Carry output for n-bit cascading ■ Synchronous counting ■ Load control line ■ Diode-clamped inputs ■ Typical propagation time, clock to Q output 14 ns ■ Typical clock frequency 32 MHz ■ Typical power dissipation 93 mW Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Order Number Package Number Package Description DM74LS161AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS161AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74LS163AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS163AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 DM74LS161A • DM74LS163A Connection Diagram Logic Diagram DM74LS163A The DM74LS161A is similar, however, the clear buffer is connected directly to the flip-flops.

3 www.fairchildsemi.com DM74LS161A • DM74LS163A Parameter Measurement Information Switching Time Waveforms The input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, ZOUT ≈ 50Ω , tR ≤ 10 ns, tF ≤ 10 ns. Vary PRR to measure fMAX . Outputs QD and carry are tested at tN +16 where tN is the bit time when all outputs are LOW. VREF = 1.5V. Switching Time Waveforms The input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, ZOUT ≈ 50Ω , tR ≤ 6 ns, tF ≤ 6 ns. Vary PRR to measure fMAX . Enable P and enable T setup times are measured at tN +0. VREF = 1.3V.

www.fairchildsemi.com 4 DM74LS161A • DM74LS163A Timing Diagram LS161A, LS163A Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences Sequence: (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one, and two (4) Inhibit

5 www.fairchildsemi.com DM74LS161A • DM74LS163A Absolute Maximum Ratings(Note 1) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DM74LS161A Recommended Operating Conditions Note 2: C L = 15 pF , RL = 2 kΩ , TA = 25°C and VCC = 5.5V. Note 3: C L = 50 pF , RL = 2 kΩ , TA = 25°C and VCC = 5.5V. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Symbol Parameter Min Nom Max Units V CC Supply Voltage 4.75 5 5.25 V VIH HIGH Level Input Voltage 2 V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 2) 0 25 MHz Clock Frequency (Note 3) 0 20 MHz tW Pulse Width Clock 20 6 ns(Note 2) Clear 20 9 Pulse Width Clock 25 ns(Note 3) Clear 25 tSU Setup Time Data 20 8 (Note 2) Enable P 25 17 ns Load 25 15 Setup Time Data 20 (Note 3) Enable P 30 ns Load 30 tH Hold Time Data 0 −3 ns(Note 2) Others 0 −3 Hold Time Data 5 ns(Note 3) Others 5 tREL Clear Release Time (Note 2) 20 ns Clear Release Time (Note 3) 25 ns T A Free Air Operating Temperature 0 70 °C

www.fairchildsemi.com 6 DM74LS161A • DM74LS163A over recommended operating free air temperature range (unless otherwise noted) Note 4: All typicals are at VCC = 5V, TA = 25°C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 6: ICCH is measured with the load HIGH, then again with the load LOW, with all other inputs HIGH and all outputs OPEN. Note 7: ICCL is measured with the clock input HIGH, then again with the clock input LOW, with all other inputs LOW and all outputs OPEN. DM74LS161A Switching Characteristics at VCC = 5V and TA = 25°C Symbol Parameter Conditions Min Typ Max Units (Note 4) VI Input Clamp Voltage V CC = Min, II = −18 mA −1.5 V VOH HIGH Level V CC = Min, IOH = Max 2.7 3.4 V Output Voltage V IL = Max, VIH = Min VOL LOW Level V CC = Min, IOL = Max 0.35 0.5 Output Voltage V IL = Max, VIH = Min V IOL = 4 mA, VCC = Min 0.25 0.4 II Input Current @ Max V CC = Max Enable T 0.2 Input Voltage V I = 7V Clock 0.2 mA Load 0.2 Others 0.1 IIH HIGH Level V CC = Max Enable T 40 Input Current V I = 2.7V Clock 40 µA Load 40 Others 20 IIL LOW Level V CC = Max Enable T −0.8 Input Current V I = 0.4V Clock −0.8 mA Load −0.8 Others −0.4 IOS Short Circuit Output Current VCC = Max (Note 5) −20 −100 mA ICCH Supply Current with Outputs HIGH VCC = Max (Note 6) 18 31 mA ICCL Supply Current with Outputs LOW VCC = Max (Note 7) 19 32 mA From (Input) R L = 2 kΩ Symbol Parameter To (Output) C L = 15 pF C L = 50 pF Units Min Max Min Max fMAX Maximum Clock Frequency 25 20 MHz tPLH Propagation Delay Time Clock to 25 30 ns LOW-to-HIGH Level Output Ripple Carry tPHL Propagation Delay Time Clock to 30 38 ns HIGH-to-LOW Level Output Ripple Carry tPLH Propagation Delay Time Clock to Any Q 22 27 ns LOW-to-HIGH Level Output (Load HIGH) tPHL Propagation Delay Time Clock to Any Q 27 38 ns HIGH-to-LOW Level Output (Load HIGH) tPLH Propagation Delay Time Clock to Any Q 24 30 ns LOW-to-HIGH Level Output (Load LOW) tPHL Propagation Delay Time Clock to Any Q 27 38 ns HIGH-to-LOW Level Output (Load LOW) tPLH Propagation Delay Time Enable T to 14 27 ns LOW-to-HIGH Level Output Ripple Carry tPHL Propagation Delay Time Enable T to 15 27 ns HIGH-to-LOW Level Output Ripple Carry tPHL Propagation Delay Time Clear to 28 45 ns HIGH-to-LOW Level Output Any Q

7 www.fairchildsemi.com DM74LS161A • DM74LS163A DM74LS163A Recommended Operating Conditions Note 8: C L = 15 pF , RL = 2 kΩ , TA = 25°C and VCC = 5V. Note 9: C L = 50 pF , RL = 2 kΩ , TA = 25°C and VCC = 5V. over recommended operating free air temperature range (unless otherwise noted) Note 10: All typicals are at VCC = 5V, TA = 25°C. Note 11: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 12: ICCH is measured with the load HIGH, then again with the load LOW, with all other inputs HIGH and all outputs OPEN. Note 13: ICCL is measured with the clock input HIGH, then again with the clock input LOW, with all other inputs LOW and all outputs OPEN. Symbol Parameter Min Nom Max Units VCC Supply Voltage 4.75 5 5.25 V VIH HIGH Level Input Voltage 2 V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 8) 0 25 MHz Clock Frequency (Note 9) 0 20 MHz tW Pulse Width Clock 20 6 ns (Note 8) Clear 20 9 Pulse Width Clock 25 ns (Note 9) Clear 25 tSU Setup Time Data 20 8 (Note 8) Enable P 25 17 ns Load 25 15 Setup Time Data 20 (Note 9) Enable P 30 ns Load 30 tH Hold Time Data 0 −3 ns (Note 8) Others 0 −3 Hold Time Data 5 ns (Note 9) Others 5 tREL Clear Release Time (Note 8) 20 ns Clear Release Time (Note 9) 25 ns T A Free Air Operating Temperature 0 70 °C Symbol Parameter Conditions Min Typ (Note 10) Max Units VI Input Clamp Voltage V CC = Min, II = −18 mA −1.5 V VOH HIGH Level V CC = Min, IOH = Max 2.7 3.4 V Output Voltage V IL = Max, VIH = Min VOL LOW Level V CC = Min, IOL = Max 0.35 0.5 Output Voltage V IL = Max, VIH = Min V IOL = 4 mA, VCC = Min 0.25 0.4 II Input Current @ Max V CC = Max Enable T 0.2 Input Voltage V I = 7V Clock, Clear 0.2 mA Load 0.2 Others 0.1 IIH HIGH Level V CC = Max Enable T 40 Input Current V I = 2.7V Load 40 µA Clock, Clear 40 Others 20 IIL LOW Level V CC = Max Enable T −0.8 Input Current V I = 0.4V Clock, Clear −0.8 mA Load −0.8 Others −0.4 IOS Short Circuit Output Current VCC = Max (Note 11) −20 −100 mA ICCH Supply Current with Outputs HIGH VCC = Max (Note 12) 18 31 mA ICCL Supply Current with Outputs LOW VCC = Max (Note 13) 18 32 mA

www.fairchildsemi.com 8 DM74LS161A • DM74LS163A DM74LS163A Switching Characteristics at VCC = 5V and TA = 25°C Note 14: The propagation delay clear to output is measured from the clock input transition. From (Input) R L = 2 kΩ Symbol Parameter To (Output) C L = 15 pF C L = 50 pF Units Min Max Min Max fMAX Maximum Clock Frequency 25 20 MHz tPLH Propagation Delay Time Clock to 25 30 ns LOW-to-HIGH Level Output Ripple Carry tPHL Propagation Delay Time Clock to 30 38 ns HIGH-to-LOW Level Output Ripple Carry tPLH Propagation Delay Time Clock to Any Q 22 27 ns LOW-to-HIGH Level Output (Load HIGH) tPHL Propagation Delay Time Clock to Any Q 27 38 ns HIGH-to-LOW Level Output (Load HIGH) tPLH Propagation Delay Time Clock to Any Q 24 30 ns LOW-to-HIGH Level Output (Load LOW) tPHL Propagation Delay Time Clock to Any Q 27 38 ns HIGH-to-LOW Level Output (Load LOW) tPLH Propagation Delay Time Enable T to 14 27 ns LOW-to-HIGH Level Output Ripple Carry tPHL Propagation Delay Time Enable T to 15 27 ns HIGH-to-LOW Level Output Ripple Carry tPHL Propagation Delay Time Clear to Any Q 28 45 ns HIGH-to-LOW Level Output (Note 14)

9 www.fairchildsemi.com DM74LS161A • DM74LS163A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

www.fairchildsemi.com 10 DM74LS161A • DM74LS163A Synchronous 4-Bit Binary Counters Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com