74HCT7403-Q100

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74HC7403-Q100;

74HCT7403-Q100

1. General description

The 74HC7403-Q100; 74HCT7403-Q100 is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 4 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. A higher data-rate can be obtained in applications where the status flags are not used (burst-mode). With separate controls for shift-in (SI) and shift-out (SO), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR), an output enable input (OE) and flags. The data-in-ready (DIR) and data-out-ready (DOR) flags indicate the status of the device. Inputs include clamp diodes that enable the use of

current limiting resistors to interface inputs to voltages in excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Synchronous or asynchronous operation  30 MHz (typical) shift-in and shift-out rates  Readily expandable in word and bit dimensions  Pinning arranged for easy board layout: input pins directly opposite output pins  Input levels:  For 74HC7403-Q100: CMOS level  For 74HCT7403-Q100: TTL level  3-state outputs  Complies with JEDEC standard JESD7A  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  Multiple package options

3. Applications

 High-speed disc or tape controller  Communications buffer

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4. Ordering information

Table 1. Ordering information

74HC7403D-Q100 40 C to +125 C SO16

plastic small outline package; 16 leads;

SOT109-1

body width 3.9 mm

74HCT7403D-Q100

5. Functional diagram

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6. Pinning information

6.1 Pinning

6.2 Pin description

Table 2. Pin description Symbol

Pin

Description

output enable input (active LOW)

1

OE DIR

2

data-in-ready output shift-in input (active HIGH)

SI

3

D0 to D3

4, 5, 6, 7

parallel data input

GND

8

ground (0 V) asynchronous master-reset input (active LOW)

9

MR Q0 to Q3 13, 12, 11, 10

data output

DOR

14

data-out-ready output shift-out input (active LOW)

15

SO

16

supply voltage

VCC

7. Functional description

A DIR flag indicates the input stage status, either empty and ready to receive data (DIR = HIGH) or full and busy (DIR = LOW). When DIR and SI are HIGH, data present at D0 to D3 is shifted into the input stage; once complete DIR goes LOW. When SI is set LOW, data is automatically shifted to the output stage or to the last empty location. DIR set HIGH indicates a FIFO which can receive data.

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A DOR flag indicates the output stage status, either data available (DOR = HIGH) or busy (DOR = LOW). When SO and DOR are HIGH, data is available at the outputs (Q0 to Q3). When SO is set LOW new data may be shifted into the output stage, once complete DOR is set HIGH.

7.1 Expanded format

The DOR and DIR signals are used to allow the 74HC7403-Q100; 74HCT7403-Q100 to be cascaded. Both parallel and serial expansion is possible. (see Figure 18).

Serial expansion is only possible with typical devices.

7.1.1 Parallel expension Parallel expension is accomplished by logically ANDing the DOR and DIR signals to form a composite signal.

7.1.2 Serial expension Parallel expension is accomplished by:

• Tying the data outputs of the first device to the data inputs of the second device.
• Connecting the DOR pin of the first device to the SI pin of the second device.
• Connecting the SO pin of the first device to the DIR pin of the second device.

8. Limiting values

Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Max Unit

supply voltage

0.5 +7 V

VCC

input clamping current

VI < 0.5 V or VI > VCC + 0.5 V

• 20 mA

IIK

output clamping current

VO < 0.5 V or VO > VCC + 0.5 V

• 20 mA

IOK

output current

VO = 0.5 V to (VCC + 0.5 V)

• 35 mA

IO

supply current

• +70 mA

ICC

ground current

• 70 mA

IGND

storage temperature

65 +150 C

Tstg

[1] -

total power dissipation

500 mW

Ptot

[1] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.

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9. Recommended operating conditions

Table 4. Recommended operating conditions Voltages are referenced to GND (ground = 0 V)

supply voltage

2.0 5.0 6.0 4.5 5.0 5.5 V

VCC input voltage

0 - VCC 0 - VCC V

VI output voltage

0 - VCC 0 - VCC V

VO ambient temperature

40 +25 +125 40

+25 +125 C

Tamb

VCC = 2.0 V

• - 625 - - - ns/V

t/V input transition rise and fall rate

VCC = 4.5 V

• 1.67 139
• 1.67 139

ns/V

VCC = 6.0 V

• - 83 - - - ns/V

10. Static characteristics

Table 5. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

74HC7403-Q100 HIGH-level

VCC = 2.0 V

1.5 1.2 - 1.5 - 1.5 - V

VIH input voltage

VCC = 4.5 V

3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V

4.2 3.2 - 4.2 - 4.2 - V

LOW-level

VCC = 2.0 V

• 0.8 0.5
• 0.5 - 0.5 V

VIL input voltage

VCC = 4.5 V

• 2.1 1.35
• 1.35 - 1.35 V

VCC = 6.0 V

• 2.8 1.8
• 1.8 - 1.8 V

HIGH-level

VI = VIH or VIL

VOH output voltage

IO = 20 A; VCC = 2.0 V

1.9 2.0 - 1.9 - 1.9 - V

IO = 20 A; VCC = 4.5 V

4.4 4.5 - 4.4 - 4.4 - V

IO = 20 A; VCC = 6.0 V

5.9 6.0 - 5.9 - 5.9 - V

IO = 8 mA; VCC = 4.5 V

3.98 4.32 - 3.84 - 3.7 - V

IO = 10 mA; VCC = 6.0 V

5.48 5.81 - 5.34 - 5.2 - V

LOW-level

VI = VIH or VIL

VOL output voltage

IO = 20 A; VCC = 2.0 V

• 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 4.5 V

• 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 6.0 V

• 0 0.1 - 0.1 - 0.1 V

IO = 8 mA; VCC = 4.5 V

• 0.15 0.26
• 0.33 - 0.4 V

IO = 10 mA; VCC = 6.0 V

• 0.15 0.26
• 0.33 - 0.4 V
• - 0.1 - 1.0 - 1.0 A

input leakage

VI = VCC or GND;

II

VCC = 6.0 V

current

• - 0.5 - 5.0 - 10.0 A

OFF-state

VI = VIH or VIL;

IOZ output current VO = VCC or GND;

VCC = 6.0 V

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Table 5. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

ICC supply current

VI = VCC or GND; IO = 0 A;

• - 50 - 500 - 1000 A

VCC = 6.0 V

input

• 3.5 -

pF

CI capacitance

74HCT7403-Q100

HIGH-level

VCC = 4.5 V to 5.5 V

2.0 1.6 - 2.0 - 2.0 - V

VIH input voltage VIL LOW-level

VCC = 4.5 V to 5.5 V

• 1.2 0.8
• 0.8 - 0.8 V

input voltage HIGH-level

VI = VIH or VIL; VCC = 4.5 V

VOH output voltage

IO = 20 A

4.4 4.5 - 4.4 - 4.4 - V

IO = 8 mA

3.98 4.32 - 3.84 - 3.7 - V

LOW-level

VI = VIH or VIL; VCC = 4.5 V

VOL output voltage

IO = 20 A

• 0 0.1 - 0.1 - 0.1 V

IO = 8 mA

• 0.15 0.26
• 0.33 - 0.4 V
• - 0.1 - 1.0 - 1.0 A

input leakage

VI = VCC or GND;

II

VCC = 5.5 V

current OFF-state

VI = VIH or VIL; VCC = 5.5 V;

IOZ

• - 0.5 - 5.0 - 10 A

output current VO = VCC or GND per input

pin; other inputs at VCC or GND; IO = 0 A

• - 50 - 500 - 1000 A

supply current

VI = VCC or GND; IO = 0 A;

ICC

VCC = 5.5 V

additional

VI = VCC  2.1 V;

ICC supply current other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V; IO = 0 A per input pin; Dn inputs

• 75 270
• 338 - 368 A

per input pin; OE input

• 100 360
• 450 - 490 A

per input pin; SI input

• 150 540
• 675 - 735 A

per input pin; MR input

• 150 540
• 675 - 735 A

per input pin; SO input

• 150 540
• 675 - 735 A

input

• 3.5 -

pF

CI capacitance

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11. Dynamic characteristics

Table 6. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17.

74HC7403-Q100

[1]

propagation MR to DIR or DOR; see tpd delay

Figure 8 VCC = 2.0 V

• 69 210
• 265 - 315 ns

VCC = 4.5 V

• 25 42 - 53 - 63 ns

VCC = 6.0 V

• 20 36 - 45 - 54 ns

[1]

SI to DIR; see Figure 6 VCC = 2.0 V

• 66 205
• 255 - 310 ns

VCC = 4.5 V

• 24 41 - 51 - 62 ns

VCC = 5 V; CL = 15 pF

• 15 - - - - - ns

VCC = 6.0 V

• 19 35 - 43 - 53 ns

[1]

SO to DOR; see Figure 9 VCC = 2.0 V

• 94 290
• 365 - 435 ns

VCC = 4.5 V

• 34 58 - 73 - 87 ns

VCC = 5 V; CL = 15 pF

• 15 - - - - - ns

VCC = 6.0 V

• 27 49 - 62 - 74 ns

[1]

DOR to Qn; see Figure 10 VCC = 2.0 V

• 11 35 - 45 - 55 ns

VCC = 4.5 V

• 4 7 - 9 - 11 ns

VCC = 6.0 V

• 3 6 - 8 - 9 ns

[1]

SO to Qn; see Figure 14 VCC = 2.0 V

• 105 325
• 406 - 488 ns

VCC = 4.5 V

• 38 65 - 81 - 98 ns

VCC = 6.0 V

• 30 55 - 69 - 83 ns

HIGH to

MR to Qn; see Figure 8

tPHL LOW

VCC = 2.0 V

• 52 160
• 200 - 240 ns

propagation

VCC = 4.5 V

• 19 32 - 40 - 48 ns

delay

VCC = 6.0 V

• 15 27 - 34 - 41 ns

[5]

LOW to

SI to DOR; see Figure 10

tPLH HIGH

VCC = 2.0 V

• 2.2 7 - 8.8 - 10.5 ns

propagation

VCC = 4.5 V

• 0.8 1.4
• 1.8 - 2.1 ns

delay

VCC = 6.0 V

• 0.6 1.2
• 1.5 - 1.8 ns

[6]

SO to DIR; see Figure 7 VCC = 2.0 V

• 2.8 9 - 11.2 - 13.5 ns

VCC = 4.5 V

• 1.0 1.8
• 2.2 - 2.7 ns

VCC = 6.0 V

• 0.8 1.5
• 1.9 - 2.3 ns

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Table 6. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17.

[2]

ten enable time OE to Qn; see Figure 16

VCC = 2.0 V

• 44 150
• 190 - 225 ns

VCC = 4.5 V

• 16 30 - 38 - 45 ns

VCC = 6.0 V

• 13 26 - 32 - 38 ns

[3]

disable time OE to Qn; see Figure 16 tdis

VCC = 2.0 V

• 50 150
• 190 - 225 ns

VCC = 4.5 V

• 18 30 - 38 - 45 ns

VCC = 6.0 V

• 14 26 - 33 - 38 ns

[4]

transition Qn; see Figure 14 tt time

VCC = 2.0 V

• 14 60 - 75 - 90 ns

VCC = 4.5 V

• 5 12 - 15 - 18 ns

VCC = 6.0 V

• 4 10 - 13 - 15 ns

pulse width SI HIGH or LOW; tW

see Figure 6 VCC = 2.0 V

35 11 - 45 - 55 - ns

VCC = 4.5 V

7 4 - 9 - 11 - ns

VCC = 6.0 V

6 3 - 8 - 9 - ns

SO HIGH or LOW; see Figure 9 VCC = 2.0 V

70 22 - 90 - 105 - ns

VCC = 4.5 V

14 8 - 18 - 21 - ns

VCC = 6.0 V

12 6 - 15 - 18 - ns

DIR HIGH; see Figure 7 VCC = 2.0 V

10 41 130

8 165 8 195 ns

VCC = 4.5 V

5 15 26 4 33 4 39 ns

VCC = 6.0 V

4 12 22 3 28 3 23 ns

DOR HIGH; see Figure 10 VCC = 2.0 V

14 52 160 12

200 12 240 ns

VCC = 4.5 V

7 19 32 6 40 6 48 ns

VCC = 6.0 V

6 15 27 5 34 5 41 ns

MR LOW; see Figure 8 VCC = 2.0 V

120 39 - 150 - 180 - ns

VCC = 4.5 V

24 14 - 30 - 36 - ns

VCC = 6.0 V

20 11 - 26 - 31 - ns

recovery

MR to SI; see Figure 15

trec time

VCC = 2.0 V

80 24 - 100 - 120 - ns

VCC = 4.5 V

16 8 - 20 - 24 - ns

VCC = 6.0 V

14 7 - 17 - 20 - ns

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Table 6. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17.

tsu set-up time Dn to SI; see Figure 13

VCC = 2.0 V

8 36

• 6 - 6 - ns

VCC = 4.5 V

4 13

• 3 - 3 - ns

VCC = 6.0 V

3 10

• 3 - 3 - ns

hold time

Dn to SI; see Figure 13

th

VCC = 2.0 V

135 44

• 170 - 205 - ns

VCC = 4.5 V

27 16 - 34 - 12 - ns

VCC = 6.0 V

5 13 - 29 - 14 - ns

maximum SI, SO burst mode; see fmax frequency Figure 11 and Figure 12

VCC = 2.0 V

3.6 9.9

• 2.8 - 2.4 - MHz

VCC = 4.5 V

18 30 - 14 - 12 - MHz

VCC = 5 V; CL = 15 pF

• 30 - - - - - MHz

VCC = 6.0 V

21 36 - 16 - 14 - MHz

SI, SO using flags; see Figure 6 and Figure 9 VCC = 2.0 V

3.6 9.9

• 2.8 - 2.4 - MHz

VCC = 4.5 V

18 30 - 14 - 12 - MHz

VCC = 5 V; CL = 15 pF

• 30 - - - - - MHz

VCC = 6.0 V

21 36 - 16 - 14 - MHz

SI, SO cascaded; see Figure 6 and Figure 9 VCC = 2.0 V

• 7.6 - - - - - MHz

VCC = 4.5 V

• 23 - - - - - MHz

VCC = 6.0 V

• 27 - - - - - MHz

[7]

power

VI = GND to VCC

• 475 - - - - - pF

CPD dissipation capacitance

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Table 6. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17.

74HCT7403-Q100

[1]

propagation MR to DIR or DOR; see tpd delay

Figure 8 VCC = 4.5 V

• 30 51 - 53 - 63 ns

[1]

SI to DIR; see Figure 6 VCC = 4.5 V

• 25 43 - 54 - 65 ns

VCC = 5 V; CL = 15 pF

• 17 - - - - - ns

[1]

SO to DOR; see Figure 9 VCC = 4.5 V

• 36 61 - 76 - 92 ns

VCC = 5 V; CL = 15 pF

• 17 - - - - - ns

[1]

DOR to Qn; see Figure 10 VCC = 4.5 V

• 7 12 - 15 - 18 ns

[1]

SO to Qn; see Figure 14 VCC = 4.5 V

• 42 72 - 90 - 108 ns

HIGH to

MR to Qn; see Figure 8

tPHL LOW

VCC = 4.5 V

• 22 38 - 48 - 57 ns

propagation delay

[5]

LOW to

SI to DOR; see Figure 10

tPLH HIGH

VCC = 4.5 V

• 0.8 1.4
• 1.75 - 2.1 ns

propagation

[6]

SO to DIR; see Figure 7

delay

VCC = 4.5 V

• 1.0 1.8
• 2.25 - 2.7 ns

[2]

enable time OE to Qn; see Figure 16 ten

VCC = 4.5 V

• 16 30 - 38 - 45 ns

[3]

disable time OE to Qn; see Figure 16 tdis

VCC = 4.5 V

• 19 30 - 38 - 45 ns

[4]

transition Qn; see Figure 14 tt time

VCC = 4.5 V

• 5 12 - 15 - 18 ns

pulse width SI HIGH or LOW; tW

see Figure 6 VCC = 4.5 V

9 5 - 6 - 8 - ns

SO HIGH or LOW; see Figure 9 VCC = 4.5 V

14 8 - 18 - 21 - ns

DIR HIGH; see Figure 7 VCC = 4.5 V

5 17 29 4 36 4 44 ns

DOR HIGH; see Figure 10 VCC = 4.5 V

7 21 36 6 45 6 54 ns

MR LOW; see Figure 8 VCC = 4.5 V

26 15 - 33 - 39 - ns

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Table 6. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 17.

trec recovery

MR to SI; see Figure 15

time

VCC = 4.5 V

18 10 - 23 - 27 - ns

set-up time Dn to SI; see Figure 13 tsu

VCC = 4.5 V

5 16

• 4 - 4 - ns

hold time

Dn to SI; see Figure 13

th

VCC = 4.5 V

30 18 - 38 - 45 - ns

maximum SI, SO burst mode; see fmax frequency Figure 11 and Figure 12

VCC = 4.5 V

18 30 - 14 - 12 - MHz

VCC = 5 V; CL = 15 pF

• 30 - - - - - MHz

SI, SO using flags; see Figure 6 and Figure 9 VCC = 4.5 V

18 30 - 14 - 12 - MHz

VCC = 5 V; CL = 15 pF

• 30 - - - - - MHz

SI, SO cascaded; see Figure 6 and Figure 9 VCC = 4.5 V

• 23 - - - - - MHz

[7]

power

VI = GND to VCC  1.5 V

• 490 - - - - - pF

CPD dissipation capacitance

[1] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] This is the ripple through delay. [6] This is the bubble-up delay. [7] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs.

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12. Waveforms

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Table 7. Measurement points

74HC7403-Q100

0.5VCC

0.5VCC

0.1VCC

0.9VCC

74HCT7403-Q100

1.3 V

1.3 V

0.1VCC

0.9VCC

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Table 8. Test data

74HC7403-Q100

VCC

6 ns

15 pF, 50 pF

1 k

open

GND

VCC

74HCT7403-Q100 3 V

6 ns

15 pF, 50 pF

1 k

open

GND

VCC

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13. Application information

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13.1 Expanded format

Figure 21 shows two cascaded FIFOs providing a capacity of 128 words x 4 bits. Figure 22 shows the signals on the nodes of both FIFOs after the application of the SI pulse, when both FIFOs are initially empty. After a ripple through delay, data arrives at the output of FIFOA. Due to SOA being HIGH, a DORA pulse is generated. The requirements od SIB and DnB are satisfied by the DORA pulse width and the timing between the rising edge of DORA and QnA. After a second ripple through delay data arrives at the output of FIFOB.

Figure 23 shows the signals on the nodes of both FIFOs after the application of the SOB pulse, when both FIFOs are initially full. After a bubble-up delay, a DIRB pulse is generated, which acts as a SOA pulse for FIFOA. One word is transferred from the output of FIFOA to the input of FIFOB. The requirements of the SOA pulse for FIFOA is satisfied by the pulse width of DORB. After a second bubble-up delay an empty space arrives at DnA, at which time DIRA goes HIGH. Figure 24 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.

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13.1.1 Sequence 1 (both FIFOs empty, starting SHIFT-IN process)

After an MR pulse has been applied, FIFOA and FIFOB are empty. The DOR flags of

FIFOA and FIFOB go LOW due to no valid data being present at the outputs. The DIR

flags are set HIGH due to the FIFOs being ready to accept data. SOB is held HIGH and

two SIA pulses are applied (1). These pulses allow two data words to ripple through the

output stage of FIFOA and the input stage of FIFIB (2). When data arrives at the output of

FIFOB, a DORB pulse is generated (3). When SOB goes LOW, the first bit is shifted out

and a second bit ripples through to the output after which DORB goes high (4).

13.1.2 Sequence 2 (FIFOB runs full)

After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in,

DIRB remains LOW due to FIFOB being full (5). DORA goes LOW due to FIFOA being

empty.

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13.1.3 Sequence 3 (FIFOA runs full) When 65 words are shifted in, DORA remains HIGH due to valid data remaining at the output of FIFOA. QnA remains HIGH, being the polarity of the 65th word (6). After the 128th SI pulse, DIR remains LOW and both FIFOs are full (7). Additional pulses have no effect.

13.1.4 Sequence 4 (both FIFOs full, starting SHIFT-OUT) SIA is held HIGH and two SOB pulses are applied (8). These pulses shift out two words and thus allow two empty locations to bubble-up to the input stage of FIFOB, and proceed to FIFOA (9). When the first empty location arrives at the input of FIFOA, a DIRA pulse is generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH (11).

13.1.5 Sequence 5 (FIFOA runs empty) At the start of sequence 5, FIFOA contains 63 valid words due to two words being shifted out and one word being shifted in, in sequence 4. And additional series of SOB pulses are applied. After 63 SOB pulses, all words from FIFOA are shifted in FIFOB. DORA remains LOW (12).

13.1.6 Sequence 6 (FIFOB runs empty) After the next SOB pulse, DIRB remains HIGH due to the input stage of FIFOB being empty. After another 63 SOB pulses, DORB remains LOW due to both FIFOS being empty (14). Additional SOB pulses have no effect. The last word remains available at the output Qn.

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14. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

Fig 25. Package outline SOT109-1 (SO16)

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15. Abbreviations

Table 9. Abbreviations Acronym

Description

CMOS

Complementary Metal Oxide Semiconductor

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

FIFO

First In First Out

MIL

Military

16. Revision history

Table 10. Revision history Document ID

Release date Data sheet status

Change notice

Supersedes

74HC_HCT7403_Q100 v.1 20120921

-

-

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17. Legal information

17.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

17.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own

risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

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No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

18. Contact information

For more information, please visit: http://www.nxp.com

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, please send an email to: salesaddresses@nxp.com

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19. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Expanded format . . . . . . . . . . . . . . . . . . . . . . . 5

7.1.1 Parallel expension . . . . . . . . . . . . . . . . . . . . . . 5 7.1.2 Serial expension . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Recommended operating conditions. . . . . . . . 6 10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Application information. . . . . . . . . . . . . . . . . . 21 13.1 Expanded format . . . . . . . . . . . . . . . . . . . . . . 23 13.1.1 Sequence 1 (both FIFOs empty, starting SHIFT-IN process) . . . . . . . . . . . . . . . . . . . . . 26

13.1.2 Sequence 2 (FIFOB runs full). . . . . . . . . . . . . 26 13.1.3 Sequence 3 (FIFOA runs full). . . . . . . . . . . . . 27 13.1.4 Sequence 4 (both FIFOs full, starting SHIFT-OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.1.5 Sequence 5 (FIFOA runs empty) . . . . . . . . . . 27 13.1.6 Sequence 6 (FIFOB runs empty) . . . . . . . . . . 27 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 28 15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 29 16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 29 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 18 Contact information. . . . . . . . . . . . . . . . . . . . . 31 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2012.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 September 2012 Document identifier: 74HC_HCT7403_Q100