74HCT7046A

74HC7046A PHILIPS

Document overview

• PDF pages: 38

Technical content

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APPLICATION INFORMATION

This information is a guide for the approximation of values of external components to be used with the 74HC/HCT7046 in a phase-lock-loop system. References should be made to Figs 27, 28 and 29 as indicated in the table.

Values of the selected components should be within the following ranges: R1 between 3 kΩ and 300 kΩ; R2 between 3 kΩ and 300 kΩ; R1 + R2 parallel value > 2.7 kΩ; C1 greater than 40 pF.

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APPLICATION INFORMATION

Lock-detection circuit The built-in lock-detection circuit will only work when used in conjunction with the phase comparator PC2. The lock-indication is derived from the phase error between SIGIN and COMPIN. The PC2 has a typical phase error of zero degrees over the entire VCO operating range. However, to remain in-lock the circuit requires some small adjustments. The variation is dependent on the loop parameters and back-lash time (typically 5 ns). Depending

on the application, the phase error can be defined as the limit, a phase error of greater magnitude would be considered out-of-lock. An example of an in-lock detection circuit using the “7046A” is shown in Fig.30. If the PLL is in-lock, only very small pulses will come from the “up” or “down” connections of PC2. These pulses are filtered out by a RC network. A Schmitt trigger produces a steady state level, a HIGH level indicates an in-lock condition and a pulsed output indicates an out-of-lock condition as shown in Fig.31.

See Fig.31 for input waveform.

Fig.30 An example of an in-lock detection circuit using the “7046A”.

(a)

(b)

Fig.31 Waveforms showing the lock detection process; (a) in-lock; (b) out-of-lock.

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PLL design example The frequency synthesizer, used in the design example shown in Fig.34, has the following parameters: Output frequency: 2 MHz to 3 MHz frequency steps : 100 kHz settling time

: 1 ms

overshoot

: < 20%

The open-loop gain is H (s) x G (s) = Kp × Kf × Ko × Kn.

Where: Kp = phase comparator gain = low-pass filter transfer gain Kf Ko = Kv/s VCO gain Kn = 1/n divider ratio

The programmable counter ratio Kn can be found as follows: fout 2 MHz

Nmin. ----------- ---------------------- 20 = =

=

fstep 100 kHz

fout 3 MHz = ----------- = ---------------------- = 30 Nmax. fstep 100 kHz

The VCO is set by the values of R1, R2 and C1, R2 = 10 kΩ (adjustable). The values can be determined using the information in the section “DESIGN CONSIDERATIONS”. With fo = 2.5 MHz and fL = 500 kHz this gives the following values (VCC = 5.0 V): R1 = 10 kΩ R2 = 10 kΩ C1 = 500 pF The VCO gain is: 2fL × 2 × π

1 MHz

= ---------------------------------------------- = = ----------------- × 2π ≈ 2 × 106 r/s/v KV

3.2

– 0.9) 0.9 – ( VCC

The gain of the phase comparator is: VCC ------------ 0.4 V/r. Kp = = 4 × π

The transfer gain of the filter is given by: 1 + τ2s Kf = ------------------------------------- 1 + ( + ) s τ1 τ2

Where: τ1 R3C2 and τ2

= R4C2.

=

The characteristics equation is: 1 + H (s) × G (s) = 0. This results in:

Kp Kv Kn

1 + × × × Kp Kv Kn τ2

× ×

s2 + ----------------------------------------------------- s --------------------------------

= 0.

+

( + )

( + )

τ1 τ2

τ1 τ2

The natural frequency ωn is defined as follows:

˙ Kp Kv Kn × × = --------------------------------. ωn ( + ) τ1 τ2

and the damping value ζ is defined as follows:

1 + × × × Kp Kv Kn τ2 1

.

---------- ----------------------------------------------------- ζ = × 2ωn

+ τ1 τ2

The overshoot and settling time percentages are now used to determine ωn. From Fig.35 it can be seen that the damping ratio ζ = 0.8 will produce an overshoot of less than 20% and settle to within 5% at ωnt = 4.5. The required settling time is 1 ms. This results in: 5 5 = 5 × 103 r/s.

= = t--- 0.001 --------------- ωn

Rewriting the equation for natural frequency results in:

Kp Kv Kn × ×

( + ) = --------------------------------. τ1 τ2

2 ωn

The maximum overshoot occurs at Nmax.:

0.4 × 2 × 106

= 0.0011 s.

( + ) =

--------------------------------- τ1 τ2

2 5000 × 30

When C2 = 470 nF, then

) × 2 × × ζ 1 +

–

( τ1 τ2

ωn

R4 ----------------------------------------------------------------- 790 Ω. =

=

Kp Kv Kn × ×

R3 is calculated using the damping ratio equation: τ1 R3 = – R4 = 2 kΩ. -------- C2

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Fig.34 Frequency synthesizer.

Note For an extensive description and application example please refer to application note ordering number 9398 649 90011. Also available a computer design program for PLL’s ordering number 9398 961 10061.

MGA959

1.6

−0.6

= 0.3 ζ

1.4

−0.4

0.5

∆ω (t)

∆Φ (t)

e

e

0.707

∆ωe /ω n

∆Φe /ω n

1.0

1.2

−0.2

= 5.0 ζ

0

1.0

= 2.0 ζ

0.8

0.2

0.6

0.4

0.4

0.6

0.2

0.8

0

1.0

0 1 2 3 4 5 6 7 8 ω nt

Fig.35 Type 1, second order frequency step response.

Since the output frequency is proportional to the VCO control voltage, the PLL frequency response can be observed with an oscilloscope by monitoring pin 9 of the VCO. The average frequency response, as calculated by the Laplace method, is found experimentally by smoothing this voltage at pin 9 with a simple RC filter, whose time constant is long compared to the phase detector sampling rate but short compared to the PLL response time.

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