74HC640 PHILIPS

Document overview

  • PDF pages: 6

Technical content

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FEATURES

  • Octal bidirectional bus interface
  • Inverting 3-state outputs
  • Output capability: bus driver
  • ICC category: MSI

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

GENERAL DESCRIPTION

The 74HC/HCT640 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT640 are octal transceivers featuring inverting 3-state bus compatible outputs in both send and receive directions. The “640” features an output enable (OE) input for easy cascading and a send/receive (DIR) for direction control. OE controls the outputs so that the buses are effectively isolated. The “640” is similar to the “245” but has inverting outputs.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
t / t PHL PLH propagation delay A to B ; n n B to A n n C = 15 pF; V = 5 V L CC 9 9 ns
C I input capacitance 3.5 3.5 pF
C I/O input/output capacitance 10 10 pF
C PD power dissipation capacitance per transceiver notes 1 and 2 35 35 pF

Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

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PIN NO. SYMBOL NAME AND FUNCTION
1 2, 3, 4, 5, 6, 7, 8, 9 10 18, 17, 16, 15, 14, 13, 12, 11 19 20 DIR A to A 0 7 GND B to B 0 7 OE V CC direction control data inputs/outputs ground (0 V) data inputs/outputs output enable input (active LOW) positive supply voltage
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inputs inputs/outputs
OE DIR A n B n
L L H L H X A=B inputs Z inputs B=A Z
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SYMBOL PARAMETER T (°C) amb UNIT TEST CONDITIONS
74HCT V CC (V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t / t PHL PLH propagation delay A to B n; n B to A n n 11 22 28 33 ns 4.5 Fig.5
t / t PZH PZL 3-state output enable time OE, DIR to A ; n OE, DIR to B n 18 30 38 45 ns 4.5 Fig.6
t / t PHZ PLZ 3-state output disable time OE, DIR to A ; n OE, DIR to B n 19 30 38 45 ns 4.5 Fig.6
t / t THL TLH output transition time 5 12 15 18 ns 4.5 Fig.5
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