Download PDF74HC597 PHILIPS
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| PIN NO. | SYMBOL | NAME AND FUNCTION |
|---|---|---|
| 8 9 10 11 12 13 14 15, 1, 2, 3, 4, 5, 6, 7 16 | GND Q MR SH CP ST CP PL D S D to D 0 7 V CC | ground (0 V) serial data output asynchronous reset input (active LOW) shift clock input (LOW-to-HIGH, edge-triggered) storage clock input (LOW-to-HIGH, edge-triggered) parallel load input (active LOW) serial data input parallel data inputs positive supply voltage |
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| ST CP | SH CP | PL | MR | FUNCTION |
| ↑ | X | X | X | data loaded to input latches |
| ↑ | X | L | H | data loaded from inputs to shift register |
| no clock edge | X | L | H | data transferred from input flip-flops to shift register |
| X | X | L | L | invalid logic, state of shift register indeterminate when signals removed |
| X | X | H | L | shift register cleared |
| X | ↑ | H | H | shift register clocked Q = Q n− 1, Q = D n 0 S |
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| SYMBOL | PARAMETER | T (°C) amb | UNIT | TEST CONDITIONS | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HCT | V CC (V) | WAVEFORMS | |||||||||
| +25 | −40 to +85 | −40 to +125 | |||||||||
| min. | typ. | max. | min. | max. | min. | max. | |||||
| t / t PHL PLH | propagation delay SH to Q CP | 23 | 40 | 50 | 60 | ns | 4.5 | Fig.7 | |||
| t PHL | propagation delay MR to Q | 28 | 49 | 61 | 74 | ns | 4.5 | Fig.8 | |||
| t / t PHL PLH | propagation delay ST to Q CP | 33 | 57 | 71 | 86 | ns | 4.5 | Fig.7 | |||
| t / t PHL PLH | propagation delay PL to Q | 30 | 52 | 65 | 78 | ns | 4.5 | Fig.9 | |||
| t / t THL TLH | output transition time | 7 | 15 | 19 | 22 | ns | 4.5 | Fig.9 | |||
| t W | SH pulse width CP HIGH or LOW | 16 | 7 | 20 | 24 | ns | 4.5 | Fig.7 | |||
| t W | ST pulse width CP HIGH or LOW | 16 | 6 | 20 | 24 | ns | 4.5 | Fig.7 | |||
| t W | MR pulse width LOW | 25 | 14 | 31 | 38 | ns | 4.5 | Fig.8 | |||
| t W | PL pulse width LOW | 20 | 10 | 25 | 30 | ns | 4.5 | Fig.9 | |||
| t rem | removal time MR to SH CP | 12 | −2 | 15 | 18 | ns | 4.5 | Fig.10 | |||
| t su | set-up time D to ST n CP | 12 | 5 | 15 | 18 | ns | 4.5 | Fig.11 | |||
| t su | set-up time D to SH S CP | 12 | 2 | 15 | 18 | ns | 4.5 | Fig.11 | |||
| t su | set-up time PL to SH CP | 12 | 4 | 15 | 18 | ns | 4.5 | Fig.12 | |||
| t h | hold time D to ST n CP | 5 | −1 | 5 | 5 | ns | 4.5 | Fig.11 | |||
| t h | hold time PL, D to SH S CP | 5 | −2 | 5 | 5 | ns | 4.5 | Fig.11 | |||
| f max | maximum pulse frequency SH CP | 30 | 75 | 24 | 20 | MHz | 4.5 | Fig.7 | |||
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