74HCT595N

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Document overview

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Technical content

Page 1

8-bit serial-in, serial or parallel-out shift register with output

latches; 3-state

1. General description

The 74HC595; 74HCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks.

Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.

The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.

2. Features and benefits

 8-bit serial input  8-bit serial or parallel output  Storage register with 3-state outputs  Shift register with direct clear  100 MHz (typical) shift out frequency  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C

3. Applications

 Serial-to-parallel data conversion  Remote control holding register

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3-state

4. Ordering information

Table 1. Ordering information

plastic dual in-line package; 16 leads (300 mil)

74HC595N

40 C to +125 C DIP16

SOT38-4

74HCT595N

plastic small outline package; 16 leads;

74HC595D

40 C to +125 C SO16

SOT109-1

body width 3.9 mm

74HCT595D

plastic shrink small outline package; 16 leads;

74HC595DB

40 C to +125 C SSOP16

SOT338-1

body width 5.3 mm

74HCT595DB

plastic thin shrink small outline package; 16 leads;

74HC595PW 40 C to +125 C TSSOP16

SOT403-1

body width 4.4 mm

74HCT595PW

40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced

74HC595BQ

SOT763-1

very thin quad flat package; no leads; 16 terminals;

74HCT595BQ

body 2.5  3.5  0.85 mm

5. Functional diagram

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3-state

6. Pinning information

6.1 Pinning

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6.2 Pin description

Table 2. Pin description Symbol

Pin

Description

Q1

1

parallel data output 1

Q2

2

parallel data output 2

Q3

3

parallel data output 3

Q4

4

parallel data output 4

Q5

5

parallel data output 5

Q6

6

parallel data output 6

Q7

7

parallel data output 7

GND

8

ground (0 V)

Q7S

9

serial data output

10

master reset (active LOW)

MR SHCP

11

shift register clock input

STCP

12

storage register clock input output enable input (active LOW)

13

OE DS

14

serial data input

Q0

15

parallel data output 0

16

supply voltage

VCC

7. Functional description

Table 3. Function table[1]

a LOW-level on MR only affects the shift registers

X X L L X L NC

X

L L X L L empty shift register loaded into storage register

 X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state

X L H H Q6S NC

logic HIGH-level shifted into shift register stage 0. Contents of all



shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). QnS contents of shift register stages (internal QnS) are transferred to

X

L H X NC



the storage register and parallel output stages

Q6S QnS contents of shift register shifted through; previous contents of the

L H X

 

[1] H = HIGH voltage state; L = LOW voltage state;  = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state.

shift register is transferred to the storage register and the parallel output stages

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8. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Max Unit

supply voltage

0.5 +7 V

VCC

input clamping current

VI < 0.5 V or VI > VCC + 0.5 V

• 20 mA

IIK

output clamping current

VO < 0.5 V or VO > VCC + 0.5 V

• 20 mA

IOK

output current

VO = 0.5 V to (VCC + 0.5 V)

IO

pin Q7S

• 25 mA

pins Qn

• 35 mA

supply current

• 70 mA

ICC

ground current

70 - mA

IGND

storage temperature

65 +150 C

Tstg

total power dissipation

Ptot

[1] -

750 mW

DIP16 package

[2] -

500 mW

SO16 package

[3] -

500 mW

SSOP16 package

[3] -

500 mW

TSSOP16 package

[4] -

500 mW

DHVQFN16 package

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. [3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C. [4] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.

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9. Recommended operating conditions

Table 5. Recommended operating conditions

supply voltage VCC input voltage VI output voltage VO

VCC = 2.0 V

t/V input transition rise and fall rate

VCC = 4.5 V VCC = 6.0 V

ambient temperature Tamb

10. Static characteristics

Table 6. Static characteristics

2.0 5.0 6.0 4.5 5.0 5.5 V

0 - VCC 0 - VCC V

0 - VCC 0 - VCC V

• - 625 - - - ns/V
• 1.67 139
• 1.67 139 ns/V
• - 83 - - - ns/V

40 +25 +125 40 +25 +125 C

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

74HC595 HIGH-level

VCC = 2.0 V

1.5 1.2 - 1.5

• V

VIH input voltage

VCC = 4.5 V

3.15 2.4 - 3.15

• V

VCC = 6.0 V

4.2 3.2 - 4.2

• V

LOW-level

VCC = 2.0 V

• 0.8 0.5 - 0.5 V

VIL input voltage

VCC = 4.5 V

• 2.1 1.35
• 1.35 V

VCC = 6.0 V

• 2.8 1.8 - 1.8 V

HIGH-level

VI = VIH or VIL

VOH output voltage

all outputs IO = 20 A; VCC = 2.0 V

1.9 2.0 - 1.9

• V

IO = 20 A; VCC = 4.5 V

4.4 4.5 - 4.4

• V

IO = 20 A; VCC = 6.0 V

5.9 6.0 - 5.9

• V

Q7S output IO = 4 mA; VCC = 4.5 V

3.84 4.32 - 3.7

• V

IO = 5.2 mA; VCC = 6.0 V

5.34 5.81 - 5.2

• V

Qn bus driver outputs IO = 6 mA; VCC = 4.5 V

3.84 4.32 - 3.7

• V

IO = 7.8 mA; VCC = 6.0 V

5.34 5.81 - 5.2

• V

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Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

VOL LOW-level

VI = VIH or VIL

output voltage

all outputs IO = 20 A; VCC = 2.0 V

• 0 0.1 - 0.1 V

IO = 20 A; VCC = 4.5 V

• 0 0.1 - 0.1 V

IO = 20 A; VCC = 6.0 V

• 0 0.1 - 0.1 V

Q7S output IO = 4 mA; VCC = 4.5 V

• 0.15 0.33
• 0.4 V

IO = 5.2 mA; VCC = 6.0 V

• 0.16 0.33
• 0.4 V

Qn bus driver outputs IO = 6 mA; VCC = 4.5 V

• 0.15 0.33
• 0.4 V

IO = 7.8 mA; VCC = 6.0 V

• 0.16 0.33
• 0.4 V

input leakage

VI = VCC or GND; VCC = 6.0 V

• - 1.0
• 1.0 A

II current

• - 5.0
• 10 A

OFF-state

VI = VIH or VIL; VCC = 6.0 V;

IOZ output current VO = VCC or GND

• - 80 - 160 A

supply current

VI = VCC or GND; IO = 0 A;

ICC

VCC = 6.0 V

CI input

• 3.5 - - - pF

capacitance 74HCT595 HIGH-level

VCC = 4.5 V to 5.5 V

2.0 1.6 - 2.0

• V

VIH input voltage VIL LOW-level

VCC = 4.5 V to 5.5 V

• 1.2 0.8 - 0.8 V

input voltage HIGH-level

VI = VIH or VIL; VCC = 4.5 V

VOH output voltage

all outputs IO = 20 A

4.4 4.5 - 4.4

• V

Q7S output IO = 4 mA

3.84 4.32 - 3.7

• V

Qn bus driver outputs IO = 6 mA

3.7 4.32 - 3.7

• V

LOW-level

VI = VIH or VIL; VCC = 4.5 V

VOL output voltage

all outputs IO = 20 A

• 0 0.1 - 0.1 V

Q7S output IO = 4.0 mA

• 0.15 0.33
• 0.4 V

Qn bus driver outputs IO = 6.0 mA

• 0.16 0.33
• 0.4 V

input leakage

VI = VCC or GND; VCC = 5.5 V

• - 1.0
• 1.0 A

II current

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Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

IOZ OFF-state

VI = VIH or VIL; VCC = 5.5 V;

• - 5.0
• 10 A

output current VO = VCC or GND supply current

VI = VCC or GND; IO = 0 A;

• - 80 - 160 A

ICC

VCC = 5.5 V

additional

per input pin; IO = 0 A; VI = VCC 

ICC supply current 2.1 V; other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V pins MR, SHCP, STCP, OE

• 150 675
• 735 A

pin DS

• 25 113
• 123 A

input

• 3.5 - - - pF

CI capacitance

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3-state

11. Dynamic characteristics

Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.

74HC595

[2]

propagation SHCP to Q7S; see Figure 9 tpd delay

VCC = 2 V

• 52 160
• 200 - 240 ns

VCC = 4.5 V

• 19 32
• 40 - 48 ns

VCC = 6 V

• 15 27
• 34 - 41 ns

[2]

STCP to Qn; see Figure 10 VCC = 2 V

• 55 175
• 220 - 265 ns

VCC = 4.5 V

• 20 35
• 44 - 53 ns

VCC = 6 V

• 16 30
• 37 - 45 ns

[3]

MR to Q7S; see Figure 12 VCC = 2 V

• 47 175
• 220 - 265 ns

VCC = 4.5 V

• 17 35
• 44 - 53 ns

VCC = 6 V

• 14 30
• 37 - 45 ns

[4]

enable time OE to Qn; see Figure 13 ten

VCC = 2 V

• 47 150
• 190 - 225 ns

VCC = 4.5 V

• 17 30
• 38 - 45 ns

VCC = 6 V

• 14 26
• 33 - 38 ns

[5]

disable time OE to Qn; see Figure 13 tdis

VCC = 2 V

• 41 150
• 190 - 225 ns

VCC = 4.5 V

• 15 30
• 38 - 45 ns

VCC = 6 V

• 12 27
• 33 - 38 ns

pulse width SHCP HIGH or LOW; tW

see Figure 9 VCC = 2 V

75 17

• 95 - 110 - ns

VCC = 4.5 V

15 6 - 19 - 22 - ns

VCC = 6 V

13 5 - 16 - 19 - ns

STCP HIGH or LOW; see Figure 10 VCC = 2 V

75 11 - 95 - 110 - ns

VCC = 4.5 V

15 4 - 19 - 22 - ns

VCC = 6 V

13 3 - 16 - 19 - ns

MR LOW; see Figure 12 VCC = 2 V

75 17

• 95 - 110 - ns

VCC = 4.5 V

15 6 - 19 - 22 - ns

VCC = 6 V

13 5 - 16 - 19 - ns

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3-state

Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.

tsu set-up time DS to SHCP; see Figure 10

VCC = 2 V

50 11 - 65 - 75 - ns

VCC = 4.5 V

10 4 - 13 - 15 - ns

VCC = 6 V

9 3 - 11 - 13 - ns

SHCP to STCP; see Figure 11 VCC = 2 V

75 22

• 95 - 110 - ns

VCC = 4.5 V

15 8 - 19 - 22 - ns

VCC = 6 V

13 7 - 16 - 19 - ns

hold time DS to SHCP; see Figure 11 th

VCC = 2 V

3 6 - 3 - 3 - ns

VCC = 4.5 V

3 2 - 3 - 3 - ns

VCC = 6 V

3 2 - 3 - 3 - ns

recovery MR to SHCP; see Figure 12 trec time

VCC = 2 V

50 19

• 65 - 75 - ns

VCC = 4.5 V

10 7

• 13 - 15 - ns

VCC = 6 V

9 6 - 11 - 13 - ns

maximum SHCP or STCP; fmax frequency see Figure 9 and 10

VCC = 2 V

9 30 - 4.8 - 4 - MHz

VCC = 4.5 V

30 91

• 24 - 20 - MHz

VCC = 6 V

35 108

• 28 - 24 - MHz

[6][7]

power

fi = 1 MHz; VI = GND to VCC

• 115 - - - - - pF

CPD dissipation capacitance 74HCT595; VCC = 4.5 V to 5.5 V

[2]

propagation SHCP to Q7S; see Figure 9

• 25 42
• 53 - 63 ns

tpd delay

[2] - 24 40

• 50 - 60 ns

STCP to Qn; see Figure 10

[3]

MR to Q7S; see Figure 12

• 23 40
• 50 - 60 ns

[4]

enable time OE to Qn; see Figure 13

• 21 35
• 44 - 53 ns

ten

[5]

disable time OE to Qn; see Figure 13

• 18 30
• 38 - 45 ns

tdis pulse width SHCP HIGH or LOW;

16 6 - 20 - 24 - ns

tW

see Figure 9 STCP HIGH or LOW;

16 5 - 20 - 24 - ns

see Figure 10 MR LOW; see Figure 12

20 8 - 25 - 30 - ns

set-up time DS to SHCP; see Figure 10

16 5 - 20 - 24 - ns

tsu

16 8 - 20 - 24 - ns

SHCP to STCP; see Figure 11

hold time DS to SHCP; see Figure 11

3 2 - 3 - 3 - ns

th

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Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.

trec recovery MR to SHCP; see Figure 12

10 7 - 13 - 15 - ns

time maximum SHCP and STCP;

30 52 - 24 - 20 - MHz

fmax frequency see Figure 9 and 10

[6] -

power

fi = 1 MHz; VI = GND to VCC

130 - - - - - pF

CPD

[7]

dissipation capacitance

[1] Typical values are measured at nominal supply voltage. [2] tpd is the same as tPHL and tPLH. [3] tpd is the same as tPHL only. [4] ten is the same as tPZL and tPZH. [5] tdis is the same as tPLZ and tPHZ. [6] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL  VCC2  fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. [7] All 9 outputs switching.

12. Waveforms

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3-state

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3-state

Table 8. Measurement points

74HC595

0.5VCC

0.5VCC

74HCT595

1.3 V

1.3 V

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3-state

Table 9. Test data

74HC595

VCC

6 ns

50 pF

1 k

open

GND

VCC

74HCT595

3 V

6 ns

50 pF

1 k

open

GND

VCC

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3-state

13. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

Fig 15. Package outline SOT38-4 (DIP16)

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3-state

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

Fig 16. Package outline SOT109-1 (SO16)

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3-state

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

Fig 17. Package outline SOT338-1 (SSOP16)

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3-state

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

Fig 18. Package outline SOT403-1 (TSSOP16)

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DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT763-1

16 terminals; body 2.5 x 3.5 x 0.85 mm

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Fig 19. Package outline SOT763-1 (DHVQFN16)

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14. Abbreviations

Table 10. Abbreviations Acronym

Abbreviation

CMOS

Complementary Metal Oxide Semiconductor

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

LSTTL

Low-power Schottky Transistor-Transistor Logic

MM

Machine Model

15. Revision history

Table 11. Revision history Document ID

Release date

Data sheet status

Change notice

74HC_HCT595 v.6

20111212

-

• Legal pages updated.

Modifications: 74HC_HCT595 v.5

20110628

-

74HC_HCT595 v.4

20030604

Product specification

-

74HC_HCT595_CNV v.3 19980604

Product specification

-

3-state

Supersedes 74HC_HCT595 v.5

74HC_HCT595 v.4 74HC_HCT595_CNV v.3 -

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3-state

16. Legal information

16.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

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Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

17. Contact information

For more information, please visit: http://www.nxp.com

3-state

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, please send an email to: salesaddresses@nxp.com

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18. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

9 Recommended operating conditions. . . . . . . . 7 10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21 15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 17 Contact information. . . . . . . . . . . . . . . . . . . . . 23 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3-state

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2011.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 December 2011 Document identifier: 74HC_HCT595