Download PDF74HC564 PHILIPS
Document overview
- PDF pages: 7
Technical content
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Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
FEATURES
- 3-state inverting outputs for bus oriented applications
- 8-bit positive-edge triggered register
- Common 3-state output enable input
- Independent register and 3-state buffer operation
- Output capability: bus driver
- ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT564 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
The 74HC/HCT564 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The “564” is functionally identical to the “574” but has inverting outputs. The “564” is functionally identical to the
“534”, but has a different pinning.
| SYMBOL | PARAMETER | CONDITIONS | TYPICAL | UNIT | |
|---|---|---|---|---|---|
| HC | HCT | ||||
| t t PHL/ PLH | propagation delay CP to Q n | C = 15 pF; V = 5 V L CC | 15 | 16 | ns |
| f max | maximum clock frequency | 127 | 62 | MHz | |
| C I | input capacitance | 3.5 | 3.5 | pF | |
| C PD | power dissipation capacitance per flip-flop | notes 1 and 2 | 27 | 27 | pF |
Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
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| PIN NO. | SYMBOL | NAME AND FUNCTION |
|---|---|---|
| 1 2, 3, 4, 5, 6, 7, 8, 9 10 11 19, 18, 17, 16, 15, 14, 13, 12 20 | OE D to D 0 7 GND CP Q to Q 0 7 V CC | 3-state output enable input (active LOW) data inputs ground (0 V) clock input (LOW-to-HIGH, edge-triggered) 3-state flip-flop outputs positive supply voltage |
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| OPERATING MODES | INPUTS | INTERNAL FLIP-FLOPS | OUTPUTS | ||
| OE | CP | D n | Q to Q 0 7 | ||
| load and read register | L L | ↑ ↑ | l h | L H | H L |
| load register and disable outputs | H H | ↑ ↑ | l h | L H | Z Z |
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| SYMBOL | PARAMETER | T (°C) amb | UNIT | TEST CONDITIONS | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HCT | V CC (V) | WAVEFORMS | |||||||||
| +25 | −40 to +85 | −40 to +125 | |||||||||
| min. | typ. | max. | min. | max. | min. | max. | |||||
| t / t PHL PLH | propagation delay CP to Q n | 19 | 35 | 44 | 53 | ns | 4.5 | Fig.6 | |||
| t / t PZH PZL | 3-state output enable time OE to Q n | 19 | 35 | 44 | 53 | ns | 4.5 | Fig.8 | |||
| t / t PHZ PLZ | 3-state output disable time OE to Q n | 19 | 30 | 38 | 45 | ns | 4.5 | Fig.8 | |||
| t / t THL TLH | output transition time | 5 | 12 | 15 | 18 | ns | 4.5 | Fig.6 | |||
| t W | clock pulse width HIGH or LOW | 18 | 8 | 23 | 27 | ns | 4.5 | Fig.6 | |||
| t su | set-up time D to CP n | 12 | 3 | 15 | 18 | ns | 4.5 | Fig.7 | |||
| t h | hold time D to CP n | 3 | −2 | 3 | 3 | ns | 4.5 | Fig.7 | |||
| f max | maximum clock pulse frequency | 27 | 56 | 22 | 18 | MHz | 4.5 | Fig.6 | |||
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