74HC4510 PHILIPS

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Technical content

Product specification File under Integrated Circuits, IC06 December 1990 INTEGRATED CIRCUITS 74HC/HCT4510 BCD up/down counter For a complete data sheet, please also download:

  • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
  • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510

FEATURES

  • Output capability: standard
  • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4510 are high-speed Si-gate CMOS devices and are pin compatible with the “4510” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4510 are edge-triggered synchronous up/down BCD counters with a clock input (CP), an up/down count control input (UP/ DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR). Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all other input conditions except the MR input, which must be LOW. With PL LOW, the counter changes on the LOW-to-HIGH transition of CP if CE is LOW. UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting up, TC is LOW when Q0 and Q3 are HIGH andCE is LOW. When counting down,TC is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counter (Q0 to Q 3 = LOW) independent of all other input conditions. Logic equation for terminal count: QUICK REFERENCE DATA GND = 0 V; Tamb =2 5°C; tr =tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD =C PD × VCC 2 × fi + ∑ (CL × VCC 2 × fo) where: fi= input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC 2 × fo) = sum of outputs C L = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI= GND to VCC . For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL / tPLH propagation delay CP to Qn C L = 15 pF; VCC = 5 V 2 12 3n s fmax maximum clock frequency 57 58 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per package notes 1 and 2 50 53 pF

Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION

1 PL parallel load input (active HIGH)

4, 12, 13, 3 D 0 to D3 parallel inputs

5 CE count enable input (active LOW)

6, 11, 14, 2 Q 0 to Q3 parallel outputs

7 TC terminal count output (active LOW)

8 GND ground (0 V)

9 MR asynchronous master reset input (active HIGH)

10 UP/

15 CP clock input (LOW-to-HIGH, edge-triggered)

CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510 Fig.4 Functional diagram. FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH clock transition MR PL UP/ DN CE CP MODE L L L L H H L L L X X X L H X X H L L X X X X parallel load no change count down count up reset Fig.5 Timing diagram.

Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510 Fig.6 Logic diagram.

Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr =tf= 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 tPHL / tPLH propagation delay CP to Qn 220 275 330 ns 2.0 4.5 6.0 Fig.7 t PHL propagation delay MR to Qn 210 265 315 ns 2.0 4.5 6.0 Fig.10 t PLH / tPHL propagation delay PL to Qn 250 315 375 ns 2.0 4.5 6.0 Fig.9 t PHL / tPLH propagation delay CP toTC 260 325 395 ns 2.0 4.5 6.0 Fig.7 t PHL / tPLH propagation delay CE toTC 125 155 190 ns 2.0 4.5 6.0 Fig.8 t PLH propagation delay MR to TC 235 295 355 ns 2.0 4.5 6.0 Fig.10 t PHL / tPLH propagation delay PL toTC 300 375 450 ns 2.0 4.5 6.0 Fig.9 t THL / tTLH output transition time 19 110 ns 2.0 4.5 6.0 Fig.9 t W pulse width CP,CE HIGH or LOW 100 120 ns 2.0 4.5 6.0 Fig.7 t W parallel load pulse width HIGH 100 120 ns 2.0 4.5 6.0 Fig.10 t W master reset pulse width HIGH 100 125 150 ns 2.0 4.5 6.0 Fig.10

Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510 trem removal time MR to CP 100 120 ns 2.0 4.5 6.0 Fig.10 t rem removal time PL to CP 100 120 ns 2.0 4.5 6.0 Fig.10 t su set-up time UP/DN to CP 100 125 150 ns 2.0 4.5 6.0 Fig.8 t su set-up time CE to CP 100 125 150 ns 2.0 4.5 6.0 Fig.8 t su set-up time D n to PL 100 125 150 ns 2.0 4.5 6.0 Fig.11 t h hold time CE to CP ns 2.0 4.5 6.0 Fig.8 t h hold time D n to PL ns 2.0 4.5 6.0 Fig.11 t h hold time UP/DN to CP −19 ns 2.0 4.5 6.0 Fig.8 f max maximum clock pulse frequency 6.0 4.8 4.0 MHz 2.0 4.5 6.0 Fig.7 SYMBOL PARAMETER T amb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125

Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr =tf= 6 ns; CL = 50 pF INPUT UNIT LOAD COEFFICIENT D n PL,CE UP/DN CP MR 0.75 1.00 1.00 1.25 1.50 SYMBOL PARAMETER T amb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 tPHL / tPLH propagation delay CP to Qn 27 50 63 75 ns 4.5 Fig.7 tPHL propagation delay MR to Qn 25 42 53 63 ns 4.5 Fig.10 tPLH / tPHL propagation delay PL to Qn 28 53 66 80 ns 4.5 Fig.9 tPHL / tPLH propagation delay CP toTC 29 58 73 87 ns 4.5 Fig.7 tPHL / tPLH propagation delay CE toTC 17 31 39 47 ns 4.5 Fig.8 tPLH propagation delay MR to TC 31 50 63 75 ns 4.5 Fig.10 tPHL / tPLH propagation delay PL toTC 35 68 85 102 ns 4.5 Fig.10 tTHL / tTLH output transition time 7 15 19 22 ns 4.5 Fig.9 tW pulse width CP,CE HIGH or LOW 16 9 20 24 ns 4.5 Fig.7 tW parallel load pulse width HIGH 16 6 20 24 ns 4.5 Fig.10 tW master reset pulse width HIGH 20 4 25 30 ns 4.5 Fig.10

Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510 trem removal time MR to CP 23 13 29 35 ns 4.5 Fig.10 trem removal time PL to CP 17 10 21 26 ns 4.5 Fig.10 tsu set-up time UP/DN to CP 20 12 25 30 ns 4.5 Fig.8 tsu set-up time CE to CP 20 6 25 30 ns 4.5 Fig.8 tsu set-up time D n to PL 20 6 25 30 ns 4.5 Fig.11 th hold time CE to CP 5 0 5 5 ns 4.5 Fig.8 th hold time D n to PL 5 0 5 5 ns 4.5 Fig.11 th hold time UP/DN to CP 0 −5 0 0 ns 4.5 Fig.8 fmax maximum clock pulse frequency 30 53 24 20 MHz 4.5 Fig.7 SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 AC WAVEFORMS Fig.7 Waveforms showing the clock (CP) to output (Qn) and terminal count (TC) propagation delays, the clock pulse width and the maximum clock pulse frequency. (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.8 Waveforms showing the set-up and hold times from count enable (CE) and up/down (UP/DN) control inputs to the clock pulse (CP), the propagation delays from UP/ DN, CE toTC. (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V.

Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510 Fig.9 Waveforms showing the preset enable pulse width, preset enable to output delays and output transition times. (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.10 Waveforms showing the master reset pulse, master reset to terminal count and Qn delay and master reset to clock removal time. (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.11 Waveforms showing the data set-up and hold times to parallel load (PL). (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V.

Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510

APPLICATION INFORMATION

Fig.12 Cascading counter packages (parallel clocking). Terminal count (TC) lines at the 2nd, 3rd, etc. stages may have a negative-going glitch pulse resulting from differential delays of different 4510s. These negative-going glitches do not affect proper 4510 operation. However, if the terminal count signals are used to trigger other edge sensitive logic devices, such as flip-flops or counters, the terminal count signals should be gated with the clock signal using a 2-input OR gate such as HC/HCT32. Fig.13 Cascading counter packages (ripple clocking). Ripple clocking mode: the UP/DN control can be changed at any count. The only restriction on changing the UP/DN control is that the clock input to the first counting stage must be “HIGH”. For cascading counters operating in a fixed up-count or down-count mode, the OR gates are not required between stages and TC is connected directly to the CP input of the next stage withCE grounded.

Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510 Fig.14 State diagram. Count-up mode: illegal states in BCD counters corrected in one count. Count-down mode: illegal states in BCD counters corrected in one or two counts. Count-up mode. Count-down mode. Fig.15 Programmable cascaded frequency divider. Use the following formulae to calculate Ntotal: Formulae are only applicable if legal data is provided to the parallel inputs. N total i π

10 N i×()

N 0+= fout fin N total Note 1. no count; foutis HIGH. parallel inputs count-up n count-down nD 3 D 2 D 1 D 0 (1) (1) PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.