Download PDF74HC4510 PHILIPS
Document overview
- PDF pages: 12
Technical content
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FEATURES
- Output capability: standard
- ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4510 are high-speed Si-gate CMOS devices and are pin compatible with the “4510” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4510 are edge-triggered synchronous up/down BCD counters with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH
parallel load input (PL), four parallel inputs (D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR). Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all other input conditions except the MR input, which must be LOW. With PL LOW, the counter changes on the LOW-to-HIGH transition of CP if CE is LOW. UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting up, TC is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting down, TC is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counter (Q0 to
Q3 = LOW) independent of all other input conditions.
TC = CE . {(UP/DN) . Q0 . Q3+(UP/DN) . Q0 . Q1 . Q2 . Q3}
Logic equation for terminal count:
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
| SYMBOL | PARAMETER | CONDITIONS | TYPICAL | UNIT | |
|---|---|---|---|---|---|
| HC | HCT | ||||
| t / t PHL PLH | propagation delay CP to Q n | C = 15 pF; V = 5 V L CC | 21 | 23 | ns |
| f max | maximum clock frequency | 57 | 58 | MHz | |
| C I | input capacitance | 3.5 | 3.5 | pF | |
| C PD | power dissipation capacitance per package | notes 1 and 2 | 50 | 53 | pF |
Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
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| PIN NO. | SYMBOL | NAME AND FUNCTION |
|---|---|---|
| 1 4, 12, 13, 3 5 6, 11, 14, 2 7 8 9 10 15 16 | PL D to D 0 3 CE Q to Q 0 3 TC GND MR UP/DN CP V CC | parallel load input (active HIGH) parallel inputs count enable input (active LOW) parallel outputs terminal count output (active LOW) ground (0 V) asynchronous master reset input (active HIGH) up/down control input clock input (LOW-to-HIGH, edge-triggered) positive supply voltage |
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| MR | PL | UP/DN | CE | CP | MODE |
| L L L L H | H L L L X | X X L H X | X H L L X | X X ↑ ↑ X | parallel load no change count down count up reset |
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| SYMBOL | PARAMETER | T (°C) amb | UNIT | TEST CONDITIONS | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HCT | V CC (V) | WAVEFORMS | |||||||||
| +25 | −40 to +85 | −40 to +125 | |||||||||
| min. | typ. | max. | min. | max. | min. | max. | |||||
| t / t PHL PLH | propagation delay CP to Q n | 27 | 50 | 63 | 75 | ns | 4.5 | Fig.7 | |||
| t PHL | propagation delay MR to Q n | 25 | 42 | 53 | 63 | ns | 4.5 | Fig.10 | |||
| t / t PLH PHL | propagation delay PL to Q n | 28 | 53 | 66 | 80 | ns | 4.5 | Fig.9 | |||
| t / t PHL PLH | propagation delay CP to TC | 29 | 58 | 73 | 87 | ns | 4.5 | Fig.7 | |||
| t / t PHL PLH | propagation delay CE to TC | 17 | 31 | 39 | 47 | ns | 4.5 | Fig.8 | |||
| t PLH | propagation delay MR to TC | 31 | 50 | 63 | 75 | ns | 4.5 | Fig.10 | |||
| t / t PHL PLH | propagation delay PL to TC | 35 | 68 | 85 | 102 | ns | 4.5 | Fig.10 | |||
| t / t THL TLH | output transition time | 7 | 15 | 19 | 22 | ns | 4.5 | Fig.9 | |||
| t W | pulse width CP, CE HIGH or LOW | 16 | 9 | 20 | 24 | ns | 4.5 | Fig.7 | |||
| t W | parallel load pulse width HIGH | 16 | 6 | 20 | 24 | ns | 4.5 | Fig.10 | |||
| t W | master reset pulse width HIGH | 20 | 4 | 25 | 30 | ns | 4.5 | Fig.10 | |||
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| SYMBOL | PARAMETER | T (°C) amb | UNIT | TEST CONDITIONS | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HCT | V CC (V) | WAVEFORMS | |||||||||
| +25 | −40 to +85 | −40 to +125 | |||||||||
| min. | typ. | max. | min. | max. | min. | max. | |||||
| t rem | removal time MR to CP | 23 | 13 | 29 | 35 | ns | 4.5 | Fig.10 | |||
| t rem | removal time PL to CP | 17 | 10 | 21 | 26 | ns | 4.5 | Fig.10 | |||
| t su | set-up time UP/DN to CP | 20 | 12 | 25 | 30 | ns | 4.5 | Fig.8 | |||
| t su | set-up time CE to CP | 20 | 6 | 25 | 30 | ns | 4.5 | Fig.8 | |||
| t su | set-up time D to PL n | 20 | 6 | 25 | 30 | ns | 4.5 | Fig.11 | |||
| t h | hold time CE to CP | 5 | 0 | 5 | 5 | ns | 4.5 | Fig.8 | |||
| t h | hold time D to PL n | 5 | 0 | 5 | 5 | ns | 4.5 | Fig.11 | |||
| t h | hold time UP/DN to CP | 0 | −5 | 0 | 0 | ns | 4.5 | Fig.8 | |||
| f max | maximum clock pulse frequency | 30 | 53 | 24 | 20 | MHz | 4.5 | Fig.7 | |||
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APPLICATION INFORMATION
Terminal count (TC) lines at the 2nd, 3rd, etc. stages may have a negative-going glitch pulse resulting from differential delays of different 4510s. These negative-going glitches do not affect proper 4510 operation. However, if the terminal count signals are used to trigger other edge sensitive logic devices, such as flip-flops or counters, the terminal count signals should be gated with the clock signal using a 2-input OR gate such as HC/HCT32.
Fig.12 Cascading counter packages (parallel clocking).
Ripple clocking mode: the UP/DN control can be changed at any count. The only restriction on changing the UP/DN control is that the clock input to the first counting stage must be “HIGH”. For cascading counters operating in a fixed up-count or down-count mode, the OR gates are not required between stages and TC is connected directly to the CP input of the next stage with CE grounded.
Fig.13 Cascading counter packages (ripple clocking).
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