74HC4316 PHILIPS

Document overview

  • PDF pages: 15

Technical content

Page 1

PDF page 1 diagram

Page 2

FEATURES

  • Low “ON” resistance: 160 Ω (typ.) at VCC − VEE = 4.5 V 120 Ω (typ.) at VCC − VEE = 6.0 V 80 Ω (typ.) at VCC − VEE = 9.0 V
  • Logic level translation: to enable 5 V logic to communicate with ± 5 V analog signals
  • Typical “break before make” built in
  • Output capability: non-standard
  • ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4316 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

VEE = GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The 74HC/HCT4316 have four independent analog switches. Each switch has two input/output terminals (nY, nZ) and an active HIGH select input (nS). When the enable input (E) is HIGH, all four analog switches are turned off. Current through a switch will not cause additional VCC current provided the voltage at the terminals of the switch is maintained within the supply voltage range; VCC >> (VY, VZ) >> VEE. Inputs nY and nZ are electrically equivalent terminals. VCC and GND are the supply voltage pins for the digital control inputs (E and nS). The VCC to GND ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT. The analog inputs/outputs (nY and nZ) can swing between

VCC as a positive limit and VEE as a negative limit. VCC − VEE may not exceed 10.0 V. See the “4016” for the version without logic level translation.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
t PZH turn “ON” time E to V OS nS to V OS C = 15 pF; R = 1 kΩ; L L V = 5 V CC 19 16 19 17 ns ns
t PZL turn “ON” time E to V OS nS to V OS 19 16 24 21 ns ns
t / t PHZ PLZ turn “OFF” time E to V OS nS to V OS 20 16 21 19 ns ns
C I input capacitance 3.5 3.5 pF
C PD power dissipation capacitance per switch notes 1 and 2 13 14 pF
C S max. switch capacitance 5 5 pF

Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ { (CL + CS) × VCC2 × fo } where: fi = input frequency in MHz fo = output frequency in MHz ∑ { (CL + CS) × VCC2 × fo } = sum of outputs

CL = output load capacitance in pF CS = max. switch capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V

Page 3

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION
1, 4, 10, 13 2, 3, 11, 12 7 8 9 15, 5, 6, 14 16 1Z to 4Z 1Y to 4Y E GND V EE 1S to 4S V CC independent inputs/outputs independent inputs/outputs enable input (active LOW) ground (0 V) negative supply voltage select inputs (active HIGH) positive supply voltage
PDF page 3 diagram
PDF page 3 diagram
PDF page 3 diagram
PDF page 3 diagram

(b)

Fig.2 Logic symbol.

Fig.1 Pin configuration.

Fig.3 IEC logic symbol.

Page 4

FUNCTION TABLE

Column 1 Column 2 Column 3
INPUTS SWITCH
E nS
L L H L H X off on off
PDF page 4 diagram

Note 1. H = HIGH voltage level L = LOW voltage level X = don’t care

APPLICATIONS

  • Signal gating
  • Modulation
  • Demodulation
  • Chopper

Fig.4 Functional diagram.

PDF page 4 diagram

Fig.5 Schematic diagram (one switch).

Page 5

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to VEE = GND (ground = 0 V)

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS
V CC DC supply voltage −0.5 +11.0 V
±I IK DC digital input diode current 20 mA for V < −0.5 V or V > V + 0.5 V I I CC
±I SK DC switch diode current 20 mA for V < −0.5 V or V > V + 0.5 V S S CC
±I S DC switch current 25 mA for −0.5 V < V < V + 0.5 V S CC
±I EE DC V current EE 20 mA
±I ; CC ±I GND DC V or GND current CC 50 mA
T stg storage temperature range −65 +150 °C
P tot power dissipation per package plastic DIL 750 mW for temperature range: −40 to +125 °C 74HC/HCT above +70 °C: derate linearly with 12 mW/K
plastic mini-pack (SO) 500 mW above +70 °C: derate linearly with 8 mW/K
P S power dissipation per switch 100 mW

Note to ratings To avoid drawing VCC current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminals Z, no VCC current will flow out of terminal Yn. In this case there is no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or VEE.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER 74HC 74HCT UNIT CONDITIONS
min. typ. max. min. typ. max.
V CC DC supply voltage V −GND CC 2.0 5.0 10.0 4.5 5.0 5.5 V see Figs 6 and 7
V CC DC supply voltage V −V CC EE 2.0 5.0 10.0 2.0 5.0 10.0 V see Figs 6 and 7
V I DC input voltage range GND V CC GND V CC V
V S DC switch voltage range V EE V CC V EE V CC V
T amb operating ambient temperature range −40 +85 −40 +85 °C see DC and AC CHARACTERISTICS
T amb operating ambient temperature range −40 +125 −40 +125 °C
t, t r f input rise and fall times 6.0 1000 500 400 250 6.0 500 ns V = 2.0 V CC V = 4.5 V CC V = 6.0 V CC V = 10.0 V CC

Page 6

PDF page 6 diagram

Fig.6 Guaranteed operating area as a function of the supply voltages for 74HC4316.

DC CHARACTERISTICS FOR 74HC/HCT

For 74HC: VCC − GND or VCC − VEE = 2.0, 4.5, 6.0 and 9.0 V

PDF page 6 diagram

Fig.7 Guaranteed operating area as a function of the supply voltages for 74HCT4316.

For 74HCT: VCC − GND = 4.5 and 5.5 V; VCC − VEE = 2.0, 4.5, 6.0 and 9.0 V

SYMBOL PARAMETER T (°C) amb UNIT TEST CONDITIONS
74HC/HCT V CC (V) V EE (V) I S (µA) V is V I
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
R ON ON resistance (peak) − 160 120 85 − 320 240 170 − 400 300 215 − 480 360 255 Ω Ω Ω Ω 2.0 4.5 6.0 4.5 0 0 0 −4.5 100 1000 1000 1000 V CC to V EE V IH or V IL
R ON ON resistance (rail) 160 80 70 60 − 160 140 120 − 200 175 150 − 240 210 180 Ω Ω Ω Ω 2.0 4.5 6.0 4.5 0 0 0 −4.5 100 1000 1000 1000 V EE V IH or V IL
R ON ON resistance (rail) 170 90 80 65 − 180 160 135 − 225 200 170 − 270 240 205 Ω Ω Ω Ω 2.0 4.5 6.0 4.5 0 0 0 −4.5 100 1000 1000 1000 V CC V IH or V IL
∆R ON maximum ∆ON resistance between any two channels − 16 9 6 Ω Ω Ω Ω 2.0 4.5 6.0 4.5 0 0 0 −4.5 V CC to V EE V H or V IL

Notes 1. At supply voltages (VCC − VEE) approaching 2.0 V the analog switch ON-resistance becomes extremely non-linear. Therefore it is recommended that these devices are used to transmit digital signals only, when using these supply voltages. 2. For test circuit measuring RON see Fig.8.

Page 7

DC CHARACTERISTICS FOR 74HC

Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER T (°C) amb UNIT TEST CONDITIONS
74HC V CC (V) V EE (V) V I OTHER
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
V IH HIGH level input voltage 1.5 3.15 4.2 6.3 1.2 2.4 3.2 4.3 1.5 3.15 4.2 6.3 1.5 3.15 4.2 6.3 V 2.0 4.5 6.0 9.0
V IL LOW level input voltage 0.8 2.1 2.8 4.3 0.5 1.35 1.8 2.7 0.5 1.35 1.8 2.7 0.5 1.35 1.8 2.7 V 2.0 4.5 6.0 9.0
±I I input leakage current 0.1 0.2 1.0 2.0 1.0 2.0 µA 6.0 10.0 0 0 V CC or GND
±I S analog switch OFF-state current 0.1 1.0 1.0 µA 10.0 0 V IH or V IL V = S V −V CC EE (see Fig.10)
±I S analog switch ON-state current 0.1 1.0 1.0 µA 10.0 0 V IH or V IL V = S V −V CC EE (see Fig.11)
I CC quiescent supply current 8.0 16.0 80.0 160.0 160.0 320.0 µA 6.0 10.0 0 0 V CC or GND V = V is EE or V ; CC V = V OS CC or V EE

Page 8

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

SYMBOL PARAMETER T (°C) amb UNIT TEST CONDITIONS
74HC V CC (V) V EE (V) OTHER
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t / t PHL PLH propagation delay V to V is os 17 6 5 4 60 12 10 8 75 15 13 10 90 18 15 12 ns 2.0 4.5 6.0 4.5 0 0 0 −4.5 R = ∞; C = 50 pF L L (see Fig.18)
t / t PZH PZL turn “ON” time E to V os 61 22 18 19 205 41 35 37 255 51 43 47 310 62 53 56 ns 2.0 4.5 6.0 4.5 0 0 0 −4.5 R = 1 kΩ; L C = 50 pF L (see Figs 19, 20 and 21)
t / t PZH PZL turn “ON” time nS to V os 52 19 15 17 175 35 30 34 220 44 37 43 265 53 45 51 ns 2.0 4.5 6.0 4.5 0 0 0 −4.5 R = 1 kΩ; L C = 50 pF L (see Figs 19, 20 and 21)
t / t PHZ PLZ turn “OFF” time E to V os 63 23 18 21 220 44 37 39 275 55 47 49 330 66 56 59 ns 2.0 4.5 6.0 4.5 0 0 0 −4.5 R = 1 kΩ; L C = 50 pF L (see Figs 19, 20 and 21)
t / t PHZ PLZ turn “OFF” time nS to V os 55 20 16 18 175 35 30 36 220 44 37 45 265 53 45 54 ns 2.0 4.5 6.0 4.5 0 0 0 −4.5 R = 1 kΩ; L C = 50 pF L (see Figs 19, 20 and 21)

Page 9

DC CHARACTERISTICS FOR 74HCT

Voltages are referenced to GND (ground = 0)

SYMBOL PARAMETER T (°C) amb UNIT TEST CONDITIONS
74HCT V CC (V) V EE (V) V I OTHER
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
V IH HIGH level input voltage 2.0 1.6 2.0 2.0 V 4.5 to 5.5
V IL LOW level input voltage 1.2 0.8 0.8 0.8 V 4.5 to 5.5
±I I input leakage current 0.1 1.0 1.0 µA 5.5 0 V CC or GND
±I S analog switch OFF-state current 0.1 1.0 1.0 µA 10.0 0 V IH or V IL V = S V −V CC EE (see Fig.10)
±I S analog switch ON-state current 0.1 1.0 1.0 µA 10.0 0 V IH or V IL V = S V −V CC EE (see Fig.11)
I CC quiescent supply current 8.0 16.0 80.0 160.0 160.0 320.0 µA 5.5 5.0 0 −5.0 V CC or GND V = V is EE or V ; CC V = V OS CC or V EE
∆I CC additional quiescent supply current per input pin for unit load coefficient is 1 (note 1) 100 360 450 490 µA 4.5 to 5.5 0 V CC −2.1 V other inputs at V or CC GND

Note 1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT
nS E 0.50 0.50

Page 10

PDF page 10 diagram

Page 11

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

SYMBOL PARAMETER T (°C) amb UNIT TEST CONDITIONS
74HCT V CC (V) V EE (V) OTHER
+25 −40 TO +85 −40 to +125
min. typ. max. min. max. min. max.
t / t PHL PLH propagation delay V to V is os 6 4 12 8 15 10 18 12 ns 4.5 4.5 0 −4.5 R = ∞; L C = 50 pF L (see Fig.18)
t PZH turn “ON” time E to V os 22 21 44 42 55 53 66 63 ns 4.5 4.5 0 −4.5 R = 1 kΩ; L C = 50 pF L (see Figs 19, 20 and 21)
t PZL turn “ON” time E to V os 28 21 56 42 70 53 84 63 ns 4.5 4.5 0 −4.5
t PZH turn “ON” time nS to V os 20 17 40 34 53 43 60 51 ns 4.5 4.5 0 −4.5 R = 1 kΩ; L C = 50 pF L (see Figs 19, 20 and 21)
t PZL turn “ON” time nS to V os 25 17 50 34 63 43 75 51 ns 4.5 4.5 0 −4.5
t / t PHZ PLZ turn “OFF” time E to V os 25 23 50 46 63 58 75 69 ns 4.5 4.5 0 −4.5 R = 1 kΩ; L C = 50 pF L (see Figs 19, 20 and 21)
t / t PHZ PLZ turn “OFF” time nS to V os 22 20 44 40 55 50 66 60 ns 4.5 4.5 0 −4.5 R = 1 kΩ; L C = 50 pF L (see Figs 19, 20 and 21)

Page 12

ADDITIONAL AC CHARACTERISTICS FOR 74HC/HCT

Recommended conditions and typical values GND = 0 V; Tamb = 25 °C

SYMBOL PARAMETER typ. UNIT V CC (V) V EE (V) V is(p-p) (V) CONDITIONS
sine-wave distortion f = 1 kHz 0.80 0.40 % % 2.25 4.5 −2.25 −4.5 4.0 8.0 R = 10 kΩ; C = 50 pF L L (see Fig.14)
sine-wave distortion f = 10 kHz 2.40 1.20 % % 2.25 4.5 −2.25 −4.5 4.0 8.0 R = 10 kΩ; C = 50 pF L L (see Fig.14)
switch “OFF” signal feed-through −50 −50 dB dB 2.25 4.5 −2.25 −4.5 note 1 R = 600 Ω; C = 50 pF L L f = 1 MHz (see Figs 12 and 15)
crosstalk between any two switches −60 −60 dB dB 2.25 4.5 −2.25 −4.5 note 1 R = 600 Ω; C = 50 pF; L L f = 1 MHz; (see Fig.16)
V (p-p) crosstalk voltage between control and any switch (peak-to-peak value) 110 220 mV mV 4.5 4.5 0 −4.5 R = 600 kΩ; C = 50 pF; L L f = 1 MHz (E or nS, square-wave between V CC and GND, t = t = 6 ns) r f (see Fig.17)
f max minimum frequency response (−3 dB) 150 160 MHz MHz 2.25 4.5 −2.25 −4.5 note 2 R = 50 Ω; C = 10 pF L L (see Figs 13 and 14)
C S maximum switch capacitance 5 pF

Notes 1. Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 Ω). 2. Adjust input voltage Vis to 0 dBm level at VOS for 1 MHz (0 dBm = 1 mW into 50 Ω).

General note Vis is the input voltage at an nY or nZ terminal, whichever is assigned as an input. Vos is the output voltage at an nY or nZ terminal, whichever is assigned as an output.

PDF page 12 diagram

Test conditions: VCC = 4.5 V; GND = 0 V; VEE = −4.5 V; RL = 50 Ω; Rsource = 1 kΩ.

Fig.12 Typical switch “OFF” signal feed-through as a function of frequency.

Page 13

PDF page 13 diagram

Page 14

PDF page 14 diagram

Page 15

TEST CIRCUIT AND WAVEFORMS

PDF page 15 diagram

Fig.20 Test circuit for measuring AC performance.

PDF page 15 diagram

Fig.21 Input pulse definitions.

Conditions

Column 1 Column 2 Column 3
TEST SWITCH V is
t PZH t PZL t PHZ t PLZ others V EE V CC V EE V CC open V CC V EE V CC V EE pulse
Column 1 Column 2 Column 3 Column 4 Column 5
FAMILY AMPLITUDE V M t; t r f
f ; max PULSE WIDTH OTHER
74HC 74HCT V CC 3.0 V 50% 1.3 V < 2 ns < 2 ns 6 ns 6 ns

Definitions for Figs 20 and 21: CL = load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values). RT = termination resistance should be equal to the output impedance ZO of the pulse generator. tr = tf = 6 ns; when measuring fmax, there is no constraint to tr, tf with 50% duty factor.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.