74HCT423BQ

74HC423 NXP

Document overview

• PDF pages: 23

Technical content

Page 1

1. General description

74HC423; 74HCT423 are high-speed Si-gate CMOS devices that are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC423; 74HCT423 dual retriggerable monostable multivibrator with reset has two methods of output pulse width control.

1. The minimum pulse width is essentially determined by the selection of an external resistor (REXT) and capacitor (CEXT), see Section 12.1. 2. Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired. When nRD is LOW, it forces the nQ output LOW, the nQ output HIGH and also inhibits the triggering. Figure 10 and Figure 11 illustrate pulse control by reset.

The nA and nB inputs’ Schmitt trigger action makes them highly tolerant to slower input rise and fall times.

The 74HC423; 74HCT423 are identical to the 74HC123; 74HCT123 except that they cannot be triggered via the reset input.

2. Features

I DC triggered from active HIGH or active LOW inputs I Retriggerable for very long pulses up to 100% duty factor I Direct reset terminates output pulse I Schmitt-trigger action on all inputs except for the reset input I Complies with JEDEC standard no. 7A I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from −40 °C to +85 °C and from −40 °C to +125 °C

Page 2

3. Ordering information

Table 1. Ordering information

plastic dual in-line package; 16 leads (300 mil)

74HC423N

−40 °C to +125 °C DIP16

SOT38-4

74HCT423N

plastic small outline package; 16 leads;

74HC423D

−40 °C to +125 °C SO16

SOT109-1

body width 3.9 mm

74HCT423D 74HC423BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin

SOT763-1

quad flat package; no leads; 16 terminals;

74HCT423BQ

body 2.5 × 3.5 × 0.85 mm plastic shrink small outline package; 16 leads;

74HCT423DB −40 °C to +125 °C SSOP16

SOT338-1

body width 5.3 mm

74HCT423PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;

SOT403-1

body width 4.4 mm

4. Functional diagram

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Page 4

5. Pinning information

5.1 Pinning

5.2 Pin description

Table 2. Pin description Symbol

Pin

1A, 2A

1, 9

1B, 2B

2, 10

1RD, 2RD

3, 11

1Q, 2Q

4, 12

GND

8

1Q, 2Q

13, 5

1CEXT, 2CEXT

14, 6

1REXT/CEXT, 2REXT/CEXT

15, 7 16

VCC

Description

trigger input (negative edge triggered) trigger input (positive edge triggered) direct reset (active LOW) output (active LOW) ground (0 V) output (active HIGH) external capacitor connection external resistor/capacitor connection supply voltage

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Page 5

6. Functional description

Table 3. Function table[1]

L

X

X

L

H

L[2]

H[2]

X

H

X

L[2]

H[2]

X

X

L

[2] If the monostable multivibrator was triggered before this condition was established, the pulse will continue as programmed.

7. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Max Unit

supply voltage

−0.5 +7 V

VCC

[1] -

input clamping current

VI < −0.5 V or VI > VCC + 0.5 V

±20 mA

IIK

[1] -

output clamping current

VO < −0.5 V or VO > VCC + 0.5 V

±20 mA

IOK

output current

−0.5 V < VO < VCC + 0.5 V

• ±25 mA

IO

supply current

• 50 mA

ICC

ground current

−50 - mA

IGND

storage temperature

−65 +150 °C

Tstg

[2] -

total power dissipation

DIP16 package

750 mW

Ptot

[3] -

500 mW

SO16, SSOP16, TSSOP16 and DHVQFN16 packages

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP16 packages: above 70 °C the value of Ptot derates linearly at 12 mW/K. [3] For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K; For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K; For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.

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Page 6

8. Recommended operating conditions

Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V).

supply voltage

2.0 5.0 6.0 4.5 5.0 5.5 V

VCC input voltage

0 - VCC 0 - VCC V

VI output voltage

0 - VCC 0 - VCC V

VO ambient temperature

−40 - +125 −40 - +125 °C

Tamb

VCC = 2.0 V

• - 625 - - - ns/V

∆t/∆V input transition rise and fall rate

VCC = 4.5 V

• 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V

• - 83 - - - ns/V

9. Static characteristics

Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

74HC423 HIGH-level

VCC = 2.0 V

VIH input voltage

VCC = 4.5 V VCC = 6.0 V

LOW-level

VCC = 2.0 V

VIL input voltage

VCC = 4.5 V VCC = 6.0 V

HIGH-level

VI = VIH or VIL

VOH output voltage

IO = −20 µA; VCC = 2.0 V IO = −20 µA; VCC = 4.5 V IO = −20 µA; VCC = 6.0 V IO = −4.0 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V

LOW-level

VI = VIH or VIL

VOL output voltage

IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V

input leakage

VI = VCC or GND; VCC = 6.0 V

II current supply current

VI = VCC or GND; IO = 0 A;

ICC

VCC = 6.0 V

1.5 1.2

• 1.5 - 1.5 - V

3.15 2.4

• 3.15 - 3.15 - V

4.2 3.2

• 4.2 - 4.2 - V
• 0.8 0.5
• 0.5 - 0.5 V
• 2.1 1.35 - 1.35 - 1.35 V - 2.8 1.8
• 1.8 - 1.8 V

1.9 2.0

• 1.9 - 1.9 - V

4.4 4.5

• 4.4 - 4.4 - V

5.9 6.0

• 5.9 - 5.9 - V

3.98 4.32 - 3.84 -

3.7 - V

5.48 5.81 - 5.34 -

5.2 - V

• 0 0.1 - 0.1 - 0.1 V
• 0 0.1 - 0.1 - 0.1 V
• 0 0.1 - 0.1 - 0.1 V
• 0.15 0.26 - 0.33 -

0.4 V

• 0.16 0.26 - 0.33 -

0.4 V

• - ±0.1 - ±1.0 - ±1.0 µA
• - 8.0 - 80 - 160 µA

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Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

CI input capacitance 74HCT423 HIGH-level input

VCC = 4.5 V to 5.5 V

VIH voltage LOW-level input

VCC = 4.5 V to 5.5 V

VIL voltage HIGH-level

VI = VIH or VIL; VCC = 4.5 V

VOH output voltage

IO = −20 µA IO = −4.0 mA

LOW-level output

VI = VIH or VIL; VCC = 4.5 V

VOL voltage

IO = 20 µA IO = 4.0 mA

input leakage

VI = VCC or GND; VCC = 5.5 V

II current supply current

VI = VCC or GND; VCC = 5.5 V;

ICC

IO = 0 A

additional supply

per input pin; VI = VCC − 2.1 V;

∆ICC current

other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A nA, nB inputs nRD input

input capacitance CI

• 3.5 - - - - - pF

2.0 1.6

• 2.0 - 2.0 - V
• 1.2 0.8
• 0.8 - 0.8 V

4.4 4.5

• 4.4 - 4.4 - V

3.98 4.32 - 3.84 -

3.7 - V

• 0 0.1 - 0.1 - 0.1 V
• 0.15 0.26 - 0.33 -

0.4 V

• - ±0.1 - ±1.0 - ±1.0 µA
• - 8.0 - 80 - 160 µA
• 35 126
• 158 - 172 µA
• 50 180
• 225 - 245 µA
• 3.5 - - - - - pF

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10. Dynamic characteristics

Table 7. Dynamic characteristics GND = 0 V; test circuit see Figure 12.

74HC423 propagation

nA or nB to nQ or nQ; REXT = 5 kΩ;

tpd delay

CEXT = 0 pF; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V nRD to nQ or nQ; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V

transition time see Figure 7 tt

VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V

pulse width

nA input LOW; see Figure 7 and Figure 8

tW

VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V nB input HIGH; see Figure 7 and Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V nRD input LOW; see Figure 7 and Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V nQ HIGH or nQ LOW; VCC = 5.0 V; REXT = 10 kΩ; CEXT = 100 nF; see Figure 7 and Figure 8 nQ HIGH or nQ LOW; VCC = 5.0 V; REXT = 5 kΩ; CEXT = 0 pF; VI = GND to VCC; see Figure 7 and Figure 8

trtrig retrigger time

nA or nB input; VCC = 5.0 V; REXT = 5 kΩ; CEXT = 0 pF; see Figure 10

[1]

• 80 255 - 320 - 385 ns - 29 51
• 64 - 77 ns
• 25 - - - - - ns
• 23 43
• 54 - 65 ns

[1]

• 66 215 - 270 - 325 ns - 24 43
• 54 - 65 ns
• 20 - - - - - ns
• 19 37
• 46 - 55 ns

[2]

• 19 75
• 95 - 110 ns
• 7 15 - 19 - 22 ns
• 6 13 - 16 - 19 ns

100 11

• 125 - 150 - ns

20 4 - 25 - 30 - ns

17 3 - 21 - 26 - ns

100 17

• 125 - 150 - ns

20 6 - 25 - 30 - ns

17 5 - 21 - 26 - ns

100 14

• 125 - 150 - ns

20 5 - 25 - 30 - ns

17 4 - 21 - 26 - ns

• 450 -
• - - - µs

[3] - 75 - - - - - ns

[4] - 110 -

• - - - ns

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Table 7. Dynamic characteristics …continued GND = 0 V; test circuit see Figure 12.

REXT external timing

VCC = 2.0 V; see Figure 8

10 - 1000 -

• - - kΩ

resistor

VCC = 5.0 V

2 - 1000 -

• - - kΩ

[5]

external timing

VCC = 5.0 V; see Figure 8

no limits

pF

CEXT capacitor

[6]

power

per package; VI = GND to VCC

• 54 - - - - - pF

CPD dissipation capacitance 74HCT423 propagation

nA or nB to nQ or nQ; REXT = 5 kΩ;

tpd delay

CEXT = 0 pF; see Figure 7

[1]

VCC = 4.5 V

• 30 51
• 64 - 77 ns

[1]

VCC = 5.0 V; CL = 15 pF

• 26 - - - - - ns

[1]

nRD to nQ or nQ; REXT = 5 kΩ;

• 26 48
• 60 - 72 ns

CEXT = 0 pF; see Figure 7

[1]

VCC = 4.5 V

• 26 48
• 60 - 72 ns

[1]

VCC = 5.0 V; CL = 15 pF

• 22 - - - - - ns

[2]

transition time

VCC = 4.5 V; Figure 7

• 7 15 - 19 - 22 ns

tt pulse width

trigger pulse; nA input LOW; VCC = 4.5 V;

20 5 - 25 - 30 - ns

tW

see Figure 7 and Figure 10 trigger pulse; nB input HIGH; VCC = 4.5 V;

20 5 - 25 - 30 - ns

see Figure 7 and Figure 10 reset pulse; nRD input LOW; VCC = 4.5 V;

20 7 - 25 - 30 - ns

see Figure 7 and Figure 11

• 450 -
• - - - µs

output pulse; nQ HIGH or nQ LOW; VCC = 5.0 V; REXT = 10 kΩ; CEXT = 100 nF; see Figure 7, Figure 10 and Figure 11

[3]

output pulse; nQ HIGH or nQ LOW;

• 75 - - - - - ns

VCC = 5.0 V; REXT = 5 kΩ; CEXT = 0 pF; VI = GND to VCC − 1.5 V; see Figure 7, Figure 10 and Figure 11

trtrig retrigger time

nA or nB input; VCC = 5.0 V; REXT = 5 kΩ;

• 110 -
• - - - ns

CEXT = 0 pF; see Figure 10

external timing

VCC = 5.0 V; see Figure 8

2 - 1000 -

• - - kΩ

REXT resistor

[5]

external timing

VCC = 5.0 V; see Figure 8

no limits

pF

CEXT capacitor

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Page 10

Table 7. Dynamic characteristics …continued GND = 0 V; test circuit see Figure 12.

[6]

CPD power

per package; VI = GND to VCC − 1.5 V

• 56 - - - - - pF

dissipation capacitance

[1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] For other REXT and CEXT combinations see Figure 8. If CEXT > 10 pF, the next formula is valid: tW = K × REXT × CEXT (typ.), where: tW = output pulse width in ns; REXT = external resistor in kΩ; CEXT = external capacitor in pF; K = 0.55 for VCC = 2.0 V and 0.45 for VCC = 5.0 V; see Figure 9. Inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF. [4] The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width will only be extended when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time.

If CEXT > 10 pF, the next formula (at VCC = 5.0 V) for the set-up time of a retrigger pulse is valid: trtrig = 30 + 0.19 × REXT × CEXT0.9 + 13 × REXT1.05 (typ.); where: trtrig = retrigger time in ns; CEXT = external capacitor in pF; REXT = external resistor in kΩ. Inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF. [5] When the device is powered-up, initiate the device via a reset pulse, when CEXT < 50 pF. [6] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo); where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V;

N = number of inputs switching; ∑ (CL × VCC2 × fo) = sum of outputs.

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11. Waveforms

Table 8. Measurement points

74HC423

VCC

0.5VCC

0.5VCC

0.1VCC

0.9VCC

74HCT423

3 V

1.3 V

1.3 V

0.1VCC

0.9VCC

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Table 9. Test data

2.0 V to 6.0 V

VCC

6 ns

15 pF, 50 pF

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12. Application information

12.1 Timing component connections

The basic output pulse width is essentially determined by the values of the external timing components REXT and CEXT.

12.1.1 Minimum monostable pulse width To set the minimum pulse width, when CEXT < 10 nF, see Figure 8 and when CEXT > 10 nF, the output pulse width is defined as: tW = 0.45 × REXT × CEXT (typ.), where:

tW = pulse width in µs;

REXT = external resistor in kΩ;

CEXT = external capacitor in nF.

12.2 Power-up considerations

When the monostable is powered-up it may produce an output pulse, with a pulse width defined by the values of REXT and CEXT, this output pulse can be eliminated using the circuit shown in Figure 14.

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12.3 Power-down considerations

A large capacitor CEXT may cause problems when powering-down the monostable due to the capacitor’s stored energy. When a system containing this device is powered-down or a rapid decrease of VCC to zero occurs, the monostable may sustain damage, due to the capacitor discharging through the input protection diodes. To avoid this possibility, use a damping diode DEXT preferably a germanium or Schottky type diode able to withstand large current surges and connect as shown in Figure 15.

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13. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

ME

D

A2 A

A1

L

c

e

w M

Z

b1

(e ) 1

b

b2

MH

9

16

pin 1 index

E

1

8

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

95-01-14

SOT38-4

03-02-13

Fig 16. Package outline SOT38-4 (DIP16)

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SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A X

c

y

HE

v M A

Z

16

9

Q

A2

A (A ) 3

A1

pin 1 index

θ Lp L

1

8

e

detail X

w M bp

0 2.5 5 mm scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT109-1

076E07

MS-012

03-02-19

Fig 17. Package outline SOT109-1 (SO16)

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Page 18

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT763-1

16 terminals; body 2.5 x 3.5 x 0.85 mm

A B

D

A A1

E

c

detail X

terminal 1 index area

C

terminal 1

e1

index area

y

y1 C

e

v M C A B

b

w M C

2

7

L

1

8

Eh

e

16

9

15

10

Dh

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Fig 18. Package outline SOT763-1 (DHVQFN16)

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SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A X

c

y

HE

v M A

Z

9

16

Q

A2

A (A )

A1

3

pin 1 index

θ Lp L

8

1

detail X

w M bp

e

0 2.5 5 mm scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT338-1

MO-150

03-02-19

Fig 19. Package outline SOT338-1 (SSOP16)

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TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

E

A

D

X

c

y

HE

v M A

Z

9

16

Q (A )

A2

3 A

A1

pin 1 index

θ Lp L

1

8

detail X

w M bp

e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT403-1

MO-153

03-02-18

Fig 20. Package outline SOT403-1 (TSSOP16)

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14. Abbreviations

Table 10. Abbreviations Acronym

Description

Complementary Metal Oxide Semiconductor

CMOS DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

15. Revision history

Table 11. Revision history Document ID

Release date Data sheet status

Change notice Supersedes

20080724

-

74HC_HCT423_CNV_2

• The format of this data sheet has been redesigned to comply with the new identity

Modifications:

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.
• Section 3 “Ordering information”, Section 5 “Pinning information”and Section 13 “Package outline”, added type numbers 74HC423BQ and 74HCT423BQ (DHVQFN16 package).
• Figure 4 “Logic diagram”, Figure 13 “Timing component connections” and Figure 15 “Power-down protection circuit” redrawn.
• Section 10 “Dynamic characteristics” CPD values added.
• Figure 12 “Test circuit for measuring switching times” added.
• Section 12.1 “Timing component connections” moved to Section 12.
• Section 14 “Abbreviations” added.

Product specification

74HC_HCT423_CNV_2

19980708

-

-

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16. Legal information

16.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or

17. Contact information

For more information, please visit: http://www.nxp.com

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, please send an email to: salesaddresses@nxp.com

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18. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Recommended operating conditions. . . . . . . . 6

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 Application information. . . . . . . . . . . . . . . . . . 14 12.1 Timing component connections . . . . . . . . . . . 14 12.1.1 Minimum monostable pulse width. . . . . . . . . . 14 12.2 Power-up considerations . . . . . . . . . . . . . . . . 14 12.3 Power-down considerations . . . . . . . . . . . . . . 15 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21 15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 17 Contact information. . . . . . . . . . . . . . . . . . . . . 22 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2008.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 24 July 2008 Document identifier: 74HC_HCT423_3