74HCT4094N

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• PDF pages: 23

Technical content

Page 1

1. General description

The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the

storage register appears at the outputs whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

 Complies with JEDEC standard JESD7A  Input levels:  For 74HC4094: CMOS level  For 74HCT4094: TTL level  Low-power dissipation  ESD protection:  HBM JESD22-A114F exceeds 2 000 V  MM JESD22-A115-A exceeds 200 V  Specified from 40 C to +85 C and from 40 C to +125 C

3. Applications

 Serial-to-parallel data conversion  Remote control holding register

Page 2

4. Ordering information

Table 1. Ordering information

74HC4094N

40 C to +125 C DIP16

74HCT4094N 74HC4094D

40 C to +125 C SO16

3.9 mm

74HCT4094D 74HC4094DB 40 C to +125 C SSOP16 74HCT4094DB 74HC4094PW 40 C to +125 C TSSOP16

5. Functional diagram

plastic dual in-line package; 16 leads (300 mil)

SOT38-4

plastic small outline package; 16 leads; body width

SOT109-1

plastic shrink small outline package; 16 leads;

SOT338-1

body width 5.3 mm

plastic thin shrink small outline package; 16 leads;

SOT403-1

body width 4.4 mm

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Page 3

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Page 4

6. Pinning information

6.1 Pinning

6.2 Pin description

Table 2. Pin description Symbol

Pin

Description

STR

1

strobe input

D

2

data input

CP

3

clock input

QP0 to QP7

4, 5, 6, 7, 14, 13, 12, 11

parallel output ground supply voltage

8

VSS QS1, QS2

9, 10

serial output output enable input

OE

15 16

supply voltage

VDD

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Page 5

7. Functional description

Table 3. Function table[1]

L

X

X

Z

Z

Q6S

NC



L

X

X

Z

Z

NC

Q7S



H

L

X

NC

NC

Q6S

NC



H

H

L

L

QPn 1

Q6S

NC



H

H

H

H

QPn 1

Q6S

NC



H

H

H

NC

NC

NC

Q7S



[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs. H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition;  = negative-going transition; Z = HIGH-impedance OFF-state; NC = no change; Q6S = the data in register stage 6 before the LOW to HIGH clock transition; Q7S = the data in register stage 7 before the HIGH to LOW clock transition.

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Page 6

8. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Max Unit

supply voltage

0.5 +7 V

VCC

input clamping current

VI < 0.5 V or VI > VCC + 0.5 V

• 20 mA

IIK

output clamping current

VO < 0.5 V or VO > VCC + 0.5 V

• 20 mA

IOK

output current

VO = 0.5 V to (VCC + 0.5 V)

• 25 mA

IO

supply current

• +50 mA

ICC

ground current

• 50 mA

IGND

storage temperature

65 +150 C

Tstg

[1] -

total power dissipation

DIP16 package

750 mW

Ptot

[2] -

SO16, SSOP16 and TSSOP16 packages

500 mW

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16: Ptot derates linearly with 8 mW/K above 70 C. For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

9. Recommended operating conditions

Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V)

supply voltage

2.0 5.0 6.0 4.5 5.0 5.5 V

VCC input voltage

0 - VCC 0 - VCC V

VI output voltage

0 - VCC 0 - VCC V

VO ambient temperature

40 +25 +125 40

+25 +125 C

Tamb

VCC = 2.0 V

• - 625 - - - ns/V

t/V input transition rise and fall rate

VCC = 4.5 V

• 1.67 139
• 1.67 139

ns/V

VCC = 6.0 V

• - 83 - - - ns/V

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Page 7

10. Static characteristics

Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

74HC4094 HIGH-level

VCC = 2.0 V

1.5 1.2 - 1.5 - 1.5 - V

VIH input voltage

VCC = 4.5 V

3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V

4.2 3.2 - 4.2 - 4.2 - V

LOW-level

VCC = 2.0 V

• 0.8 0.5
• 0.5 - 0.5 V

VIL input voltage

VCC = 4.5 V

• 2.1 1.35
• 1.35 - 1.35 V

VCC = 6.0 V

• 2.8 1.8
• 1.8 - 1.8 V

HIGH-level

VI = VIH or VIL

VOH output voltage

IO = 20 A; VCC = 2.0 V

1.9 2.0 - 1.9 - 1.9 - V

IO = 20 A; VCC = 4.5 V

4.4 4.5 - 4.4 - 4.4 - V

IO = 20 A; VCC = 6.0 V

5.9 6.0 - 5.9 - 5.9 - V

IO = 4.0 mA; VCC = 4.5 V

3.98 4.32 - 3.84 - 3.7 - V

IO = 5.2 mA; VCC = 6.0 V

5.48 5.81 - 5.34 - 5.2 - V

LOW-level

VI = VIH or VIL

VOL output voltage

IO = 20 A; VCC = 2.0 V

• 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 4.5 V

• 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 6.0 V

• 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 4.5 V

• 0.15 0.26
• 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V

• 0.16 0.26
• 0.33 - 0.4 V
• - 0.1 - 1.0 - 1.0 A

input leakage

VI = VCC or GND;

II

VCC = 6.0 V

current

• - 0.5 - 5.0 - 10.0 A

OFF-state

VI = VIH or VIL;

IOZ output current VO = VCC or GND;

VCC = 6.0 V

ICC

• - 8.0 - 80 - 160 A

supply current

VI = VCC or GND; IO = 0 A; VCC = 6.0 V

input

• 3.5 -

pF

CI capacitance 74HCT4094 HIGH-level

VCC = 4.5 V to 5.5 V

2.0 1.6 - 2.0 - 2.0 - V

VIH input voltage VIL LOW-level

VCC = 4.5 V to 5.5 V

• 1.2 0.8
• 0.8 - 0.8 V

input voltage HIGH-level

VI = VIH or VIL; VCC = 4.5 V

VOH output voltage

IO = 20 A

4.4 4.5 - 4.4 - 4.4 - V

IO = 4.0 mA

3.98 4.32 - 3.84 - 3.7 - V

LOW-level

VI = VIH or VIL; VCC = 4.5 V

VOL output voltage

IO = 20 A

• 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA

• 0.15 0.26
• 0.33 - 0.4 V

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Page 8

Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

II input leakage

VI = VCC or GND;

• - 0.1 - 1.0 - 1.0 A

current

VCC = 5.5 V

• - 0.5 - 5.0 - 10 A

OFF-state

VI = VIH or VIL; VCC = 5.5 V;

IOZ output current VO = VCC or GND per input

pin; other inputs at VCC or GND; IO = 0 A

ICC supply current

VI = VCC or GND; IO = 0 A;

• - 8.0 - 80 - 160 A

VCC = 5.5 V

additional

VI = VCC  2.1 V;

ICC supply current other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V; IO = 0 A per input pin; STR input

• 100 360
• 450 - 490 A

per input pin; OE input

• 150 540
• 675 - 735 A

per input pin; CP input

• 150 540
• 675 - 735 A

per input pin; D input

• 40 144
• 180 - 196 A

input

• 3.5 -

pF

CI capacitance

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Page 9

11. Dynamic characteristics

Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.

74HC4094

[1]

propagation CP to QS1; see Figure 8 tpd delay

VCC = 2.0 V

• 50 150
• 190 - 225 ns

VCC = 4.5 V

• 18 30 - 38 - 45 ns

VCC = 5 V; CL = 15 pF

• 15 - - - - - ns

VCC = 6.0 V

• 14 26 - 33 - 38 ns

[1]

CP to QS2; see Figure 8 VCC = 2.0 V

• 44 135
• 170 - 205 ns

VCC = 4.5 V

• 16 27 - 34 - 41 ns

VCC = 5 V; CL = 15 pF

• 13 - - - - - ns

VCC = 6.0 V

• 13 23 - 29 - 35 ns

[1]

CP to QPn; see Figure 8 VCC = 2.0 V

• 63 195
• 245 - 295 ns

VCC = 4.5 V

• 23 39 - 49 - 59 ns

VCC = 5 V; CL = 15 pF

• 20 - - - - - ns

VCC = 6.0 V

• 18 33 - 42 - 50 ns

[1]

STR to QPn; see Figure 9 VCC = 2.0 V

• 58 180
• 225 - 270 ns

VCC = 4.5 V

• 21 36 - 45 - 54 ns

VCC = 5 V; CL = 15 pF

• 18 - - - - - ns

VCC = 6.0 V

• 17 31 - 38 - 46 ns

[2]

enable time OE to QPn; see Figure 11 ten

VCC = 2.0 V

• 55 175
• 220 - 265 ns

VCC = 4.5 V

• 20 35 - 44 - 53 ns

VCC = 6.0 V

• 16 30 - 37 - 45 ns

[3]

disable time OE to QPn; see Figure 11 tdis

VCC = 2.0 V

• 41 125
• 155 - 190 ns

VCC = 4.5 V

• 15 25 - 31 - 38 ns

VCC = 6.0 V

• 12 21 - 26 - 32 ns

[4]

transition QPn and QSn; see tt time

Figure 8 VCC = 2.0 V

• 19 75 - 95 - 110 ns

VCC = 4.5 V

• 7 15 - 19 - 22 ns

VCC = 6.0 V

• 6 13 - 16 - 19 ns

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Page 10

Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.

tW pulse width CP HIGH or LOW;

see Figure 8 VCC = 2.0 V

80 14 - 100 - 120 - ns

VCC = 4.5 V

16 5 - 20 - 24 - ns

VCC = 6.0 V

14 4 - 17 - 20 - ns

STR HIGH; see Figure 9 VCC = 2.0 V

80 14 - 100 - 120 - ns

VCC = 4.5 V

16 5 - 20 - 24 - ns

VCC = 6.0 V

14 4 - 17 - 20 - ns

set-up time D to CP; see Figure 10 tsu

VCC = 2.0 V

50 14 - 65 - 75 - ns

VCC = 4.5 V

10 5 - 13 - 15 - ns

VCC = 6.0 V

9 4 - 11 - 13 - ns

CP to STR; see Figure 9 VCC = 2.0 V

100 28

• 125 - 150 - ns

VCC = 4.5 V

20 10 - 25 - 30 - ns

VCC = 6.0 V

17 8 - 21 - 26 - ns

hold time

D to CP; see Figure 10

th

VCC = 2.0 V

3 -6 - 3 - 3 - ns

VCC = 4.5 V

3 -2 - 3 - 3 - ns

VCC = 6.0 V

3 -2 - 3 - 3 - ns

CP to STR; see Figure 9 VCC = 2.0 V

0 -14 - 0 - 0 - ns

VCC = 4.5 V

0 -5 - 0 - 0 - ns

VCC = 6.0 V

0 -4 - 0 - 0 - ns

maximum CP; see Figure 8 fmax frequency

VCC = 2.0 V

6.0 28 - 4.8 - 4.0 - MHz

VCC = 4.5 V

30 87 - 24 - 20 - MHz

VCC = 5 V; CL = 15 pF

• 95 - - - - - MHz

VCC = 6.0 V

35 103

• 28 - 24 - MHz

[5]

power

CL = 50 pF; f = 1 MHz;

• 83 - - - - - pF

CPD dissipation VI = GND to VCC capacitance

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Page 11

Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.

74HCT4094

[1]

propagation CP to QS1; see Figure 8 tpd delay

VCC = 4.5 V

• 23 39 - 49 - 59 ns

VCC = 5 V; CL = 15 pF

• 19 - - - - - ns

[1]

CP to QS2; see Figure 8 VCC = 4.5 V

• 21 36 - 45 - 54 ns

VCC = 5 V; CL = 15 pF

• 18 - - - - - ns

[1]

CP to QPn; see Figure 8 VCC = 4.5 V

• 25 43 - 54 - 65 ns

VCC = 5 V; CL = 15 pF

• 21 - - - - - ns

[1]

STR to QPn; see Figure 9 VCC = 4.5 V

• 22 39 - 49 - 59 ns

VCC = 5 V; CL = 15 pF

• 19 - - - - - ns

[2]

enable time OE to QPn; see Figure 11 ten

VCC = 4.5 V

• 20 35 - 44 - 53 ns

[3]

disable time OE to QPn; see Figure 11 tdis

VCC = 4.5 V

• 21 35 - 44 - 53 ns

[4]

transition QPn and QSn; see tt time

Figure 8 VCC = 4.5 V

• 7 15 - 19 - 22 ns

pulse width CP HIGH or LOW; tW

see Figure 8 VCC = 4.5 V

16 7 - 20 - 24 - ns

STR HIGH; see Figure 9 VCC = 4.5 V

16 5 - 20 - 24 - ns

set-up time Dn to CP; see Figure 10 tsu

VCC = 4.5 V

10 4 - 13 - 15 - ns

CP to STR; see Figure 9 VCC = 4.5 V

20 9 - 25 - 30 - ns

hold time

Dn to CP; see Figure 10

th

VCC = 4.5 V

4 0 - 4 - 4 - ns

CP to STR; see Figure 9 VCC = 4.5 V

0 4 - 0 - 0 - ns

maximum CP; see Figure 8 fmax frequency

VCC = 4.5 V

30 80 - 24 - 20 - MHz

VCC = 5 V; CL = 15 pF

• 86 - - - - - MHz

[5]

power

CL = 50 pF; f = 1 MHz;

• 92 - - - - - pF

CPD dissipation VI = GND to VCC capacitance

[1] tpd is the same as tPLH and tPHL.

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Page 12

[2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs.

12. Waveforms

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Page 13

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Page 14

Table 8. Measurement points

74HC4094

0.5VCC

0.5VCC

0.1VOH

0.9VOH

74HCT4094

1.3 V

1.3 V

0.1VOH

0.9VOH

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Page 15

Table 9. Test data

74HC4094

VCC

6 ns

15 pF, 50 pF

1 k

open

GND

VCC

74HCT4094

3 V

6 ns

15 pF, 50 pF

1 k

open

GND

VCC

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Page 16

13. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

ME

D

A2 A

A1

L

c

e

w M

Z

b1

(e ) 1

b

b2

MH

9

16

pin 1 index

E

1

8

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

95-01-14

SOT38-4

03-02-13

Fig 13. Package outline SOT38-4 (DIP16)

16 of 23

Page 17

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A X

c

y

HE

v M A

Z

16

9

Q

A2

A (A ) 3

A1

pin 1 index

θ Lp L

1

8

e

detail X

w M bp

0 2.5 5 mm scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT109-1

076E07

MS-012

03-02-19

Fig 14. Package outline SOT109-1 (SO16)

17 of 23

Page 18

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A X

c

y

HE

v M A

Z

9

16

Q

A2

A (A )

A1

3

pin 1 index

θ Lp L

8

1

detail X

w M bp

e

0 2.5 5 mm scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

MO-150

SOT338-1

03-02-19

Fig 15. Package outline SOT338-1 (SSOP16)

18 of 23

Page 19

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

E

A

D

X

c

y

HE

v M A

Z

9

16

Q (A )

A2

3 A

A1

pin 1 index

θ Lp L

1

8

detail X

w M bp

e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT403-1

MO-153

03-02-18

Fig 16. Package outline SOT403-1 (TSSOP16)

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Page 20

14. Abbreviations

Table 10. Abbreviations Acronym

Description

CMOS

Complementary Metal Oxide Semiconductor

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

15. Revision history

Table 11. Revision history Document ID

Release date Data sheet status

Change notice

74HC_HCT4094 v.6

20121231

-

• General description updated.

Modifications: 74HC_HCT4094 v.5

20120628

-

• VX and VY measurement points added to Table 8.

Modifications: 74HC_HCT4094 v.4

20111219

-

• Legal pages updated.

Modifications: 74HC_HCT4094 v.3

20110214

-

74HC_HCT4094_CNV v.2 19970901

Product specification

-

Supersedes 74HC_HCT4094 v.5

74HC_HCT4094 v.4

74HC_HCT4094 v.3

74HC_HCT4094_CNV v.2 -

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16. Legal information

16.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

17. Contact information

For more information, please visit: http://www.nxp.com

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, please send an email to: salesaddresses@nxp.com

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18. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

9 Recommended operating conditions. . . . . . . . 6 10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20 15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 17 Contact information. . . . . . . . . . . . . . . . . . . . . 22 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2012.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 31 December 2012 Document identifier: 74HC_HCT4094