74HCT4067N

74HC4067 NXP

Document overview

• PDF pages: 29

Technical content

Page 1

1. General description

The 74HC4067; 74HCT4067 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4067B. The device is specified in compliance with JEDEC standard no. 7A.

The 74HC4067; 74HCT4067 is a 16-channel analog multiplexer/demultiplexer with four address inputs (S0 to S3), an active-LOW enable input (E), sixteen independent inputs/outputs (Y0 to Y15) and a common input/output (Z).

The 74HC4067; 74HCT4067 contains sixteen bidirectional analog switches, each with one side connected to an independent input/output (Y0 to Y15) and the other side connected to a common input/output (Z).

With pin E = LOW, one of the sixteen switches is selected by pins S0 to S3 (low impedance ON-state). All unselected switches are in the high-impedance OFF-state. With pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins S0 to S3.

The analog inputs/outputs (Y0 to Y15, and Z) can swing between VCC as a positive limit and GND as a negative limit. VCC to GND may not exceed 10 V.

2. Features

I Low ON resistance: N 80 Ω (typical) at VCC = 4.5 V N 70 Ω (typical) at VCC = 6.0 V N 60 Ω (typical) at VCC = 9.0 V I Typical ‘break before make’ built-in

3. Applications

I Analog multiplexing and demultiplexing I Digital multiplexing and demultiplexing I Signal gating

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4. Ordering information

Table 1. Ordering information

74HC4067

plastic dual in-line package; 24 leads (600 mil);

74HC4067N

−40 °C to +125 °C DIP24

SOT101-1

reverse bending plastic small outline package; 24 leads;

74HC4067D

−40 °C to +125 °C SO24

SOT137-1

body width 7.5 mm plastic shrink small outline package; 24 leads;

74HC4067DB

−40 °C to +125 °C SSOP24

SOT340-1

body width 5.3 mm

74HC4067PW −40 °C to +125 °C TSSOP24 plastic thin shrink small outline package; 24 leads;

SOT355-1

body width 4.4 mm

−40 °C to +125 °C DHVQFN24 plastic dual in-line compatible thermal enhanced very

74HC4067BQ

SOT815-1

thin quad flat package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm

74HCT4067

plastic dual in-line package; 24 leads (600 mil);

74HCT4067N

−40 °C to +125 °C DIP24

SOT101-1

reverse bending plastic small outline package; 24 leads;

74HCT4067D

−40 °C to +125 °C SO24

SOT137-1

body width 7.5 mm plastic shrink small outline package; 24 leads;

74HCT4067DB −40 °C to +125 °C SSOP24

SOT340-1

body width 5.3 mm

74HCT4067PW −40 °C to +125 °C TSSOP24 plastic thin shrink small outline package; 24 leads;

SOT355-1

body width 4.4 mm

74HCT4067BQ −40 °C to +125 °C DHVQFN24 plastic dual in-line compatible thermal enhanced very

SOT815-1

thin quad flat package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm

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5. Functional diagram

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6. Pinning information

6.1 Pinning

6.2 Pin description

Table 2. Pin description Symbol Pin

Description

Z

1

common input/output

Y7

2

independent input/output 7

Y6

3

independent input/output 6

Y5

4

independent input/output 5

Y4

5

independent input/output 4

Y3

6

independent input/output 3

Y2

7

independent input/output 2

Y1

8

independent input/output 1

Y0

9

independent input/output 0

S0

10

address input 0

S1

11

address input 1

GND

12

ground (0 V)

S3

13

address input 3

S2

14

address input 2

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Table 2. Pin description …continued Symbol Pin

Description

E

15

enable input (active LOW)

Y15

16

independent input/output 15

Y14

17

independent input/output 14

Y13

18

independent input/output 13

Y12

19

independent input/output 12

Y11

20

independent input/output 11

Y10

21

independent input/output 10

Y9

22

independent input/output 9

Y8

23

independent input/output 8

24

supply voltage

VCC

7. Functional description

Table 3. Function table[1]

L

L

L

L

L

Y0 to Z

L

L

L

L

H

Y1 to Z

L

L

L

H

L

Y2 to Z

L

L

L

H

H

Y3 to Z

L

L

H

L

L

Y4 to Z

L

L

H

L

H

Y5 to Z

L

L

H

H

L

Y6 to Z

L

L

H

H

H

Y7 to Z

L

H

L

L

L

Y8 to Z

L

H

L

L

H

Y9 to Z

L

H

L

H

L

Y10 to Z

L

H

L

H

H

Y11 to Z

L

H

H

L

L

Y12 to Z

L

H

H

L

H

Y13 to Z

L

H

H

H

L Y14 to Z

L

H

H

H

H Y15 to Z

H

X

X

X

X

-

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.

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8. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Max Unit

[1] −0.5

supply voltage

+11.0 V

VCC input clamping current

VI < −0.5 V or VI > VCC + 0.5 V

• ±20 mA

IIK switch clamping current

VSW < −0.5 V or VSW > VCC + 0.5 V

• ±20 mA

ISK switch current

VSW = −0.5 V to (VCC + 0.5 V)

• ±25 mA

ISW supply current

• 50 mA

ICC ground current

• −50 mA

IGND storage temperature

−65 +150 °C

Tstg total power dissipation

Tamb = −40 °C to +125 °C

Ptot

[2] -

750 mW

DIP24 package

[3] -

500 mW

SO24 package

[4] -

500 mW

SSOP24 package

[4] -

500 mW

TSSOP24 package

[5] -

500 mW

DHVQFN24 package

P power dissipation

per switch

• 100 mW

[1] To avoid drawing VCC current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of terminals Yn. In this case there is no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or GND. [2] For DIP24 package: Ptot derates linearly with 12 mW/K above 70 °C. [3] For SO24 package: Ptot derates linearly with 8 mW/K above 70 °C. [4] For SSOP24 and TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. [5] For DHVQFN24 package: Ptot derates linearly with 4.5 mW/K above 60 °C.

9. Recommended operating conditions

Table 5. Recommended operating conditions Symbol Parameter

Conditions

Min Typ Max Unit

74HC4067 supply voltage

2.0 5.0 10.0 V

VCC input voltage

GND - VCC V

VI switch voltage

GND - VCC V

VSW rise time

VCC = 2.0 V

• - 1000 ns

tr

VCC = 4.5 V

• 6.0 500 ns

VCC = 6.0 V

• - 400 ns

VCC = 10.0 V

• - 250 ns

fall time

VCC = 2.0 V

• - 1000 ns

tf

VCC = 4.5 V

• 6.0 500 ns

VCC = 6.0 V

• - 400 ns

VCC = 10.0 V

• - 250 ns

ambient temperature

−40 +25 +125 °C

Tamb

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Table 5. Recommended operating conditions …continued Symbol Parameter

Conditions

Min Typ Max Unit

74HCT4067 supply voltage

4.5 5.0 5.5 V

VCC input voltage

GND - VCC V

VI switch voltage

GND - VCC V

VSW rise time

VCC = 4.5 V

• 6.0 500 ns

tr fall time

VCC = 4.5 V

• 6.0 500 ns

tf ambient temperature

−40 +25 +125 °C

Tamb

10. Static characteristics

Table 6. RON resistance per switch for types 74HC4067 and 74HCT4067 VI = VIH or VIL; for test circuit see Figure 8. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. For 74HC4067: VCC − GND = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4067: VCC − GND = 4.5 V.

ON resistance (peak)

Vis = VCC to GND

RON(peak)

[1]

VCC = 2.0 V; ISW = 100 µA

• - - - Ω

VCC = 4.5 V; ISW = 1000 µA

110 180 225 270 Ω

VCC = 6.0 V; ISW = 1000 µA

95 160 200 240 Ω

VCC = 9.0 V; ISW = 1000 µA

75 130 165 195 Ω

ON resistance (rail)

Vis = GND or VCC

RON(rail)

[1]

VCC = 2.0 V; ISW = 100 µA

150 - - -

VCC = 4.5 V; ISW = 1000 µA

90 160 200 240 Ω

VCC = 6.0 V; ISW = 1000 µA

80 140 175 210 Ω

VCC = 9.0 V; ISW = 1000 µA

70 120 150 180 Ω

ON resistance mismatch

Vis = VCC to GND

∆RON

between channels

[1]

VCC = 2.0 V

• - - - Ω

VCC = 4.5 V

9 - - - Ω

VCC = 6.0 V

8 - - - Ω

VCC = 9.0 V

6 - - - Ω

[1] At supply voltages (VCC − GND) approaching 2 V, the analog switch ON resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital signals only, when using these supply voltages.

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Table 7. Static characteristics 74HC4067 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 25 °C HIGH-level input voltage

VCC = 2.0 V

1.5 1.2 - V

VIH

VCC = 4.5 V

3.15 2.4

• V

VCC = 6.0 V

4.2 3.2 - V

VCC = 9.0 V

6.3 4.7 - V

LOW-level input voltage

VCC = 2.0 V

• 0.8 0.5 V

VIL

VCC = 4.5 V

• 2.1 1.35 V

VCC = 6.0 V

• 2.8 1.80 V

VCC = 9.0 V

• 4.3 2.70 V

input leakage current

VI = VCC or GND

II

VCC = 6.0 V

• - ±0.1 µA

VCC = 10.0 V

• - ±0.2 µA

OFF-state leakage current

VCC = 10.0 V; VI = VIH or VIL;

IS(OFF)

|VSW| = VCC − GND; see Figure 10 per channel

• - ±0.1 µA

all channels

• - ±0.8 µA

ON-state leakage current

VCC = 10.0 V; VI = VIH or VIL;

• - ±0.8 µA

IS(ON)

|VSW| = VCC − GND; see Figure 11

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Table 7. Static characteristics 74HC4067 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

ICC supply current

VI = VCC or GND; Vis = GND or VCC; Vos = VCC or GND VCC = 6.0 V

• - 8.0 µA

VCC = 10.0 V

• - 16.0 µA

input capacitance

• 3.5 - pF

CI Tamb = −40 °C to +85 °C

HIGH-level input voltage

VCC = 2.0 V

1.5 - - V

VIH

VCC = 4.5 V

3.15 -

• V

VCC = 6.0 V

4.2 - - V

VCC = 9.0 V

6.3 - - V

LOW-level input voltage

VCC = 2.0 V

• - 0.50 V

VIL

VCC = 4.5 V

• - 1.35 V

VCC = 6.0 V

• - 1.80 V

VCC = 9.0 V

• - 2.70 V

input leakage current

VI = VCC or GND

II

VCC = 6.0 V

• - ±1.0 µA

VCC = 10.0 V

• - ±2.0 µA

OFF-state leakage current

VCC = 10.0 V; VI = VIH or VIL;

IS(OFF)

|VSW| = VCC − GND; see Figure 10 per channel

• - ±1.0 µA

all channels

• - ±8.0 µA

ON-state leakage current

VCC = 10.0 V; VI = VIH or VIL;

• - ±8.0 µA

IS(ON)

|VSW| = VCC − GND; see Figure 11

supply current

VI = VCC or GND; Vis = GND or VCC;

ICC

Vos = VCC or GND VCC = 6.0 V

• - 80.0 µA

VCC = 10.0 V

• - 160 µA

Tamb = −40 °C to +125 °C HIGH-level input voltage

VCC = 2.0 V

1.5 - - V

VIH

VCC = 4.5 V

3.15 -

• V

VCC = 6.0 V

4.2 - - V

VCC = 9.0 V

6.3 - - V

LOW-level input voltage

VCC = 2.0 V

• - 0.50 V

VIL

VCC = 4.5 V

• - 1.35 V

VCC = 6.0 V

• - 1.80 V

VCC = 9.0 V

• - 2.70 V

input leakage current

VI = VCC or GND

II

VCC = 6.0 V

• - ±1.0 µA

VCC = 10.0 V

• - ±2.0 µA

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Table 7. Static characteristics 74HC4067 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

IS(OFF) OFF-state leakage current

VCC = 10.0 V; VI = VIH or VIL; |VSW| = VCC − GND; see Figure 10 per channel

• - ±1.0 µA

all channels

• - ±8.0 µA

ON-state leakage current

VCC = 10.0 V; VI = VIH or VIL;

• - ±8.0 µA

IS(ON)

|VSW| = VCC − GND; see Figure 11

supply current

VI = VCC or GND; Vis = GND or VCC;

ICC

Vos = VCC or GND VCC = 6.0 V

• - 160 µA

VCC = 10.0 V

• - 320 µA

Table 8. Static characteristics 74HCT4067 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 25 °C HIGH-level input voltage

VCC = 4.5 V to 5.5 V

2.0 1.6 - V

VIH LOW-level input voltage

VCC = 4.5 V to 5.5 V

• 1.2 0.8 V

VIL input leakage current

VI = VCC or GND; VCC = 5.5 V

• - ±0.1 µA

II OFF-state leakage current

VCC = 5.5 V; VI = VIH or VIL;

IS(OFF)

|VSW| = VCC − GND; see Figure 10 per channel

• - ±0.1 µA

all channels

• - ±0.8 µA

ON-state leakage current

VCC = 5.5 V; VI = VIH or VIL;

• - ±0.8 µA

IS(ON)

|VSW| = VCC − GND; see Figure 11

supply current

VI = VCC or GND; Vis = GND or VCC;

• - 8.0 µA

ICC

Vos = VCC or GND; VCC = 4.5 V to 5.5 V

additional supply current

per input pin; VI = VCC − 2.1 V; other inputs

∆ICC

at VCC or GND; VCC = 4.5 V to 5.5 V pin E

• 60 216 µA

pin Sn

• 50 180 µA

input capacitance

• 3.5 - pF

CI Tamb = −40 °C to +85 °C

HIGH-level input voltage

VCC = 4.5 V to 5.5 V

2.0 - - V

VIH LOW-level input voltage

VCC = 4.5 V to 5.5 V

• - 0.8 V

VIL input leakage current

VI = VCC or GND; VCC = 5.5 V

• - ±1.0 µA

II OFF-state leakage current

VCC = 5.5 V; VI = VIH or VIL;

IS(OFF)

|VSW| = VCC − GND; see Figure 10 per channel

• - ±1.0 µA

all channels

• - ±8.0 µA

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Table 8. Static characteristics 74HCT4067 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

VCC = 5.5 V; VI = VIH or VIL;

IS(ON) ON-state leakage current

• - ±8.0 µA

|VSW| = VCC − GND; see Figure 11 VI = VCC or GND; Vis = GND or VCC;

supply current

• - 80.0 µA

ICC

Vos = VCC or GND; VCC = 4.5 V to 5.5 V per input pin; VI = VCC − 2.1 V; other

additional supply current ∆ICC

inputs at VCC or GND; VCC = 4.5 V to 5.5 V pin E

• - 270 µA

pin Sn

• - 225 µA

Tamb = −40 °C to +125 °C HIGH-level input voltage

VCC = 4.5 V to 5.5 V

2.0 - - V

VIH LOW-level input voltage

VCC = 4.5 V to 5.5 V

• - 0.8 V

VIL

VI = VCC or GND; VCC = 5.5 V

input leakage current

• - ±1.0 µA

II

VCC = 5.5 V; VI = VIH or VIL;

OFF-state leakage current IS(OFF)

|VSW| = VCC − GND; see Figure 10 per channel

• - ±1.0 µA

all channels

• - ±8.0 µA

VCC = 5.5 V; VI = VIH or VIL;

ON-state leakage current

• - ±8.0 µA

IS(ON)

|VSW| = VCC − GND; see Figure 11 VI = VCC or GND; Vis = GND or VCC;

supply current

• - 160 µA

ICC

Vos = VCC or GND; VCC = 4.5 V to 5.5 V per input pin; VI = VCC − 2.1 V; other

additional supply current ∆ICC

inputs at VCC or GND; VCC = 4.5 V to 5.5 V pin E

• - 294 µA

pin Sn

• - 245 µA

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11. Dynamic characteristics

Table 9. Dynamic characteristics 74HC4067 GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

[1][2]

propagation delay

Yn to Z; see Figure 12

tpd

VCC = 2.0 V

25 75 95 110 ns

VCC = 4.5 V

9 15 19 22 ns

VCC = 6.0 V

7 13 16 19 ns

VCC = 9.0 V

5 9 11 14 ns

Z to Yn VCC = 2.0 V

18 60 75 90 ns

VCC = 4.5 V

6 12 15 18 ns

VCC = 6.0 V

5 10 13 15 ns

VCC = 9.0 V

4 8 10 12 ns

[3]

turn-off time

E to Yn; see Figure 13

toff

VCC = 2.0 V

74 250 315 375 ns

VCC = 4.5 V

27 50 63 75 ns

VCC = 5.0 V; CL = 15 pF

27 - - - ns

VCC = 6.0 V

22 43 54 64 ns

VCC = 9.0 V

20 38 48 57 ns

Sn to Yn VCC = 2.0 V

83 250 315 375 ns

VCC = 4.5 V

30 50 63 75 ns

VCC = 5.0 V; CL = 15 pF

29 - - - ns

VCC = 6.0 V

24 43 54 64 ns

VCC = 9.0 V

21 38 48 57 ns

E to Z VCC = 2.0 V

85 275 345 415 ns

VCC = 4.5 V

31 55 69 83 ns

VCC = 6.0 V

25 47 59 71 ns

VCC = 9.0 V

24 42 53 63 ns

Sn to Z VCC = 2.0 V

94 290 365 435 ns

VCC = 4.5 V

34 58 73 87 ns

VCC = 6.0 V

27 47 62 74 ns

VCC = 9.0 V

25 45 56 68 ns

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Table 9. Dynamic characteristics 74HC4067 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

[4]

ton turn-on time

E to Yn; see Figure 13 VCC = 2.0 V

80 275 345 415 ns

VCC = 4.5 V

29 55 69 83 ns

VCC = 5.0 V; CL = 15 pF

26 - - - ns

VCC = 6.0 V

23 47 59 71 ns

VCC = 9.0 V

17 42 53 63 ns

Sn to Yn VCC = 2.0 V

88 300 375 450 ns

VCC = 4.5 V

32 60 75 90 ns

VCC = 5.0 V; CL = 15 pF

29 - - - ns

VCC = 6.0 V

26 51 64 77 ns

VCC = 9.0 V

18 45 56 68 ns

E to Z VCC = 2.0 V

85 275 345 415 ns

VCC = 4.5 V

31 55 69 83 ns

VCC = 6.0 V

25 47 59 71 ns

VCC = 9.0 V

18 42 53 63 ns

Sn to Z VCC = 2.0 V

94 300 375 450 ns

VCC = 4.5 V

34 60 75 90 ns

VCC = 6.0 V

27 51 64 77 ns

VCC = 9.0 V

19 45 56 68 ns

[5]

power dissipation

per switch; VI = GND to VCC

• 29 - - pF

CPD capacitance

[1] tpd is the same as tPHL and tPLH. [2] Due to higher Z terminal capacitance (16 switches versus 1) the delay figures to the Z terminal are higher than those to the Y terminal. [3] ton is the same as tPHZ and tPLZ. [4] toff is the same as tPZH and tPZL. [5] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑{(CL + Csw) × VCC2 × fo} where: fi = input frequency in MHz; fo = output frequency in MHz; ∑{(CL + Csw) × VCC2 × fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V.

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Table 10. Dynamic characteristics 74HCT4067 GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.

[1][2]

propagation delay Yn to Z; see Figure 12 tpd

VCC = 4.5 V

9 15 19 22 ns

Z to Yn VCC = 4.5 V

6 12 15 18 ns

[3]

turn-off time

E to Yn; see Figure 13

toff

VCC = 4.5 V

26 55 69 83 ns

VCC = 5.0 V; CL = 15 pF

26 - - - ns

Sn to Yn VCC = 4.5 V

31 55 69 83 ns

VCC = 5.0 V; CL = 15 pF

30 - - - ns

E to Z VCC = 4.5 V

30 60 75 90 ns

Sn to Z VCC = 4.5 V

35 60 75 90 ns

[4]

turn-on time

E to Yn; see Figure 13

ton

VCC = 4.5 V

32 60 75 90 ns

VCC = 5.0 V; CL = 15 pF

32 - - - ns

Sn to Yn VCC = 4.5 V

35 60 75 90 ns

VCC = 5.0 V; CL = 15 pF

33 - - - ns

E to Z VCC = 4.5 V

38 65 81 98 ns

Sn to Z VCC = 4.5 V

38 65 81 98 ns

[5]

power dissipation

per switch; VI = GND to (VCC − 1.5 V)

• 29 - - pF

CPD capacitance

[1] tpd is the same as tPHL and tPLH. [2] Due to higher Z terminal capacitance (16 switches versus 1) the delay figures to the Z terminal are higher than those to the Y terminal. [3] ton is the same as tPHZ and tPLZ. [4] toff is the same as tPZH and tPZL. [5] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑{(CL + Csw) × VCC2 × fo} where: fi = input frequency in MHz; fo = output frequency in MHz; ∑{(CL + Csw) × VCC2 × fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V.

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12. Waveforms

Table 11. Measurement points Type

VI

VM

74HC4067

VCC

0.5VCC

74HCT4067

3.0 V

1.3 V

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Table 12. Test data

tPHL, tPLH

GND

GND or VCC GND to VCC

tPHZ, tPZH

GND to VCC GND to VCC VCC

tPLZ, tPZL

GND to VCC GND to VCC

GND

[1] For 74HCT4067: maximum input voltage VI = 3.0 V.

6 ns 50 pF

• open

6 ns 50 pF, 15 pF 1 kΩ

GND

6 ns 50 pF, 15 pF 1 kΩ

VCC

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13. Additional dynamic characteristics

Table 13. Additional dynamic characteristics Recommended conditions and typical values; GND = 0 V; Tamb = 25 °C. Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input. Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

RL = 10 kΩ; CL = 50 pF; see Figure 15

THD total harmonic distortion

fi = 1 kHz VCC = 4.5 V; Vis(p-p) = 4.0 V

• 0.04 -

%

VCC = 9.0 V; Vis(p-p) = 8.0 V

• 0.02 -

%

fi = 10 kHz VCC = 4.5 V; Vis(p-p) = 4.0 V

• 0.12 -

%

VCC = 9.0 V; Vis(p-p) = 8.0 V

• 0.06 -

%

[1]

isolation (OFF-state)

RL = 600 Ω; CL = 50 pF; see Figure 16

αiso

VCC = 4.5 V

• −50 - dB

VCC = 9.0 V

• −50 - dB

[2]

−3 dB frequency response

RL = 50 Ω; CL = 10 pF; see Figure 17

f(-3dB)

VCC = 4.5 V

• 90 - MHz

VCC = 9.0 V

• 100 - MHz

switch capacitance

independent pins Y

• 5 - pF

Csw

common pin Z

• 45 - pF

[1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 Ω). [2] Adjust input voltage Vis to 0 dBm level at Vos for fi = 1 MHz (0 dBm = 1 mW into 50 Ω). After set-up, fi is increased to obtain a reading of −3 dB at Vos.

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Page 20

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Page 21

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Page 22

14. Package outline

DIP24: plastic dual in-line package; 24 leads (600 mil)

SOT101-1

ME

D

A2 A

L

A1

c

e

w M

Z

b1

(e ) 1

b

MH

13

24

pin 1 index

E

1

12

0 5 10 mm scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

Fig 18. Package outline SOT101-1 (DIP24)

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Page 23

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

D

E

A X

c

HE

v M A

y

Z

24

13

Q

A2

A (A )

A1

3

pin 1 index

θ Lp L

1

12

detail X

e

w M bp

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

Fig 19. Package outline SOT137-1 (SO24)

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Page 24

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm

SOT340-1

D

E

A X

c

HE

v M A

y

Z

24

13

Q

A2

A (A ) 3

A1

pin 1 index

θ Lp L

1

12

detail X

w M bp

e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT340-1

MO-150

03-02-19

Fig 20. Package outline SOT340-1 (SSOP24)

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Page 25

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

D

E

A X

c

HE

v M A

y

Z

13

24

Q

A2

(A ) A 3

A1

pin 1 index

θ Lp L

1

12

detail X

w M bp

e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT355-1

MO-153

03-02-19

Fig 21. Package outline SOT355-1 (TSSOP24)

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DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;

SOT815-1

no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm

B A

D

A A1

E

c

detail X

terminal 1 index area

C

e1

terminal 1

y1 C

index area

y

v M C A B

e

b

w M C

2

11

L

12

1

e2

Eh

24

13

23

14

X

Dh

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Fig 22. Package outline SOT815-1 (DHVQFN24)

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15. Revision history

Table 14. Revision history Document ID

Release date

Data sheet status

Change notice Supersedes

20071015

-

74HC_HCT4067_CNV_2

• The format of this data sheet has been redesigned to comply with the new identity

Modifications:

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.
• Added: type numbers 74HC4067BQ and 74HCT4067BQ (DHVQFN24 package).

74HC_HCT4067_CNV_2 19970901

Product specification

-

-

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16. Legal information

16.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or

17. Contact information

For additional information, please visit: http://www.nxp.com

malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, send an email to: salesaddresses@nxp.com

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18. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 7 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8

9 Recommended operating conditions. . . . . . . . 8 10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 14 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13 Additional dynamic characteristics . . . . . . . . 19 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 16.3

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17 Contact information. . . . . . . . . . . . . . . . . . . . . 28 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2007.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 October 2007 Document identifier: 74HC_HCT4067_3