74HCT4053PW112

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Document overview

• PDF pages: 32

Technical content

Page 1

1. General description

The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.

The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a common enable input (E). Each multiplexer/demultiplexer has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs (Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3.

VCC and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for 74HCT4053. The analog inputs/outputs (nY0 to nY1, and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC  VEE may not exceed 10.0 V.

For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).

2. Features and benefits

 Wide analog input voltage range from 5 V to +5 V  Low ON resistance:  80  (typical) at VCC  VEE = 4.5 V  70  (typical) at VCC  VEE = 6.0 V  60  (typical) at VCC  VEE = 9.0 V  Logic level translation: to enable 5 V logic to communicate with 5 V analog signals  Typical ‘break before make’ built-in  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C

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3. Applications

 Analog multiplexing and demultiplexing  Digital multiplexing and demultiplexing  Signal gating

4. Ordering information

Table 1. Ordering information

plastic dual in-line package; 16 leads (300 mil)

74HC4053N

40 C to +125 C DIP16

SOT38-4

74HCT4053N

plastic small outline package; 16 leads;

74HC4053D

40 C to +125 C SO16

SOT109-1

body width 3.9 mm

74HCT4053D

plastic shrink small outline package; 16 leads;

74HC4053DB 40 C to +125 C SSOP16

SOT338-1

body width 5.3 mm

74HCT4053DB 74HC4053PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;

SOT403-1

body width 4.4 mm

74HCT4053PW 74HC4053BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very

SOT763-1

thin quad flat package; no leads; 16 terminals;

74HCT4053BQ

body 2.5  3.5  0.85 mm

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5. Functional diagram

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Page 4

6. Pinning information

6.1 Pinning

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Page 5

6.2 Pin description

Table 2. Pin description Symbol

Pin

Description

6

enable input (active LOW)

E

7

supply voltage

VEE GND

8

ground supply voltage

S1, S2, S3

11, 10, 9

select input

1Y0, 2Y0, 3Y0

12, 2, 5

independent input or output

1Y1, 2Y1, 3Y1

13, 1, 3

independent input or output

1Z, 2Z, 3Z

14, 15, 4

common output or input

16

supply voltage

VCC

7. Functional description

Table 3. Function table [1]

L

L

nY0 to nZ

L

H

nY1 to nZ

H

X

switches off

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.

8. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol

Parameter

Conditions

Min

Max

Unit

[1] 0.5

supply voltage

+11.0

V

VCC

input clamping current

VI < 0.5 V or VI > VCC + 0.5 V

-

20

mA

IIK

switch clamping current

VSW < 0.5 V or VSW > VCC + 0.5 V

-

20

mA

ISK

switch current

0.5 V < VSW < VCC + 0.5 V

-

25

mA

ISW

supply current

-

20

mA

IEE

supply current

-

50

mA

ICC

ground current

-

50

mA

IGND

storage temperature

65

+150

C

Tstg

[2] -

total power dissipation

DIP16 package

750

mW

Ptot

[3] -

500

mW

SO16, (T)SSOP16, and DHVQFN16 package

P

power dissipation

per switch

-

100

mW

[1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow out of terminals nYn, and in this case there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE. [2] For DIP16 packages: above 70 C the value of Ptot derates linearly with 12 mW/K.

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[3] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.

9. Recommended operating conditions

Table 5. Recommended operating conditions

supply voltage

see Figure 7

VCC

and Figure 8 VCC  GND

2.0 5.0 10.0 4.5 5.0 5.5 V

VCC  VEE

2.0 5.0 10.0 2.0 5.0 10.0 V

input voltage

GND - VCC GND - VCC V

VI switch voltage

VEE - VCC VEE - VCC V

VSW ambient temperature

40 +25 +125

40 +25 +125 C

Tamb

VCC = 2.0 V

• - 625 - - - ns/V

t/V input transition rise and fall rate

VCC = 4.5 V

• 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V

• - 83 - - - ns/V

VCC = 10.0 V

• - 31 - - - ns/V

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10. Static characteristics

Table 6. RON resistance per switch for 74HC4053 and 74HCT4053 VI = VIH or VIL; for test circuit see Figure 9. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. For 74HC4053: VCC GND or VCC VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4053: VCC GND = 4.5 V and 5.5 V, VCC VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 25 C RON(peak) ON resistance (peak)

Vis = VCC to VEE

[1] -

VCC = 2.0 V; VEE = 0 V; ISW = 100 A

• - 

VCC = 4.5 V; VEE = 0 V; ISW = 1000 A

• 100 180



VCC = 6.0 V; VEE = 0 V; ISW = 1000 A

• 90 160 

VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A

• 70 130 

ON resistance (rail)

Vis = VEE

RON(rail)

[1] -

VCC = 2.0 V; VEE = 0 V; ISW = 100 A

150 -



VCC = 4.5 V; VEE = 0 V; ISW = 1000 A

• 80 140 

VCC = 6.0 V; VEE = 0 V; ISW = 1000 A

• 70 120 

VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A

• 60 105 

Vis = VCC

[1] -

VCC = 2.0 V; VEE = 0 V; ISW = 100 A

150 -



VCC = 4.5 V; VEE = 0 V; ISW = 1000 A

• 90 160 

VCC = 6.0 V; VEE = 0 V; ISW = 1000 A

• 80 140 

VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A

• 65 120 

ON resistance mismatch

Vis = VCC to VEE

RON between channels

[1] -

VCC = 2.0 V; VEE = 0 V

• - 

VCC = 4.5 V; VEE = 0 V

• 9 - 

VCC = 6.0 V; VEE = 0 V

• 8 - 

VCC = 4.5 V; VEE = 4.5 V

• 6 - 

Tamb = 40 C to +85 C RON(peak) ON resistance (peak)

Vis = VCC to VEE

[1] -

VCC = 2.0 V; VEE = 0 V; ISW = 100 A

• - 

VCC = 4.5 V; VEE = 0 V; ISW = 1000 A

• - 225 

VCC = 6.0 V; VEE = 0 V; ISW = 1000 A

• - 200 

VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A

• - 165 

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Table 6. RON resistance per switch for 74HC4053 and 74HCT4053 …continued VI = VIH or VIL; for test circuit see Figure 9. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. For 74HC4053: VCC GND or VCC VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4053: VCC GND = 4.5 V and 5.5 V, VCC VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. Symbol Parameter

Conditions

Min Typ Max Unit

RON(rail) ON resistance (rail)

Vis = VEE

[1] -

VCC = 2.0 V; VEE = 0 V; ISW = 100 A

• - 

VCC = 4.5 V; VEE = 0 V; ISW = 1000 A

• - 175 

VCC = 6.0 V; VEE = 0 V; ISW = 1000 A

• - 150 

VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A

• - 130 

Vis = VCC

[1] -

VCC = 2.0 V; VEE = 0 V; ISW = 100 A

• - 

VCC = 4.5 V; VEE = 0 V; ISW = 1000 A

• - 200 

VCC = 6.0 V; VEE = 0 V; ISW = 1000 A

• - 175 

VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A

• - 150 

Tamb = 40 C to +125 C RON(peak) ON resistance (peak)

Vis = VCC to VEE

[1] -

VCC = 2.0 V; VEE = 0 V; ISW = 100 A

• - 

VCC = 4.5 V; VEE = 0 V; ISW = 1000 A

• - 270 

VCC = 6.0 V; VEE = 0 V; ISW = 1000 A

• - 240 

VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A

• - 195 

ON resistance (rail)

Vis = VEE

RON(rail)

[1] -

VCC = 2.0 V; VEE = 0 V; ISW = 100 A

• - 

VCC = 4.5 V; VEE = 0 V; ISW = 1000 A

• - 210 

VCC = 6.0 V; VEE = 0 V; ISW = 1000 A

• - 180 

VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A

• - 160 

Vis = VCC

[1] -

VCC = 2.0 V; VEE = 0 V; ISW = 100 A

• - 

VCC = 4.5 V; VEE = 0 V; ISW = 1000 A

• - 240 

VCC = 6.0 V; VEE = 0 V; ISW = 1000 A

• - 210 

VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A

• - 180 

[1] When supply voltages (VCC  VEE) near 2.0 V the analog switch ON resistance becomes extremely non-linear. When using a supply of 2 V, it is recommended to use these devices only for transmitting digital signals.

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Table 7. Static characteristics for 74HC4053 Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max

Unit

Tamb = 25 C

HIGH-level input

VCC = 2.0 V

1.5 1.2 - V

VIH

voltage

VCC = 4.5 V

3.15 2.4

• V

VCC = 6.0 V

4.2 3.2 - V

VCC = 9.0 V

6.3 4.7 - V

LOW-level input

VCC = 2.0 V

• 0.8 0.5 V

VIL

voltage

VCC = 4.5 V

• 2.1 1.35 V

VCC = 6.0 V

• 2.8 1.8 V

VCC = 9.0 V

• 4.3 2.7 V

input leakage current

VEE = 0 V; VI = VCC or GND

II

VCC = 6.0 V

• - 0.1 A

VCC = 10.0 V

• - 0.2 A

OFF-state leakage

VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;

IS(OFF)

VSW = VCC  VEE; see Figure 11

current

per channel

• - 0.1 A

all channels

• - 0.1 A

ON-state leakage

VI = VIH or VIL; VSW = VCC  VEE;

• - 0.1 A

IS(ON)

current

VCC = 10.0 V; VEE = 0 V; see Figure 12

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Table 7. Static characteristics for 74HC4053 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max

Unit

ICC

supply current

VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE VCC = 6.0 V

• - 8.0 A

VCC = 10.0 V

• - 16.0 A

input capacitance

• 3.5 - pF

CI

switch capacitance

independent pins nYn

• 5 - pF

Csw

common pins nZ

• 8 - pF

Tamb = 40 C to +85 C

HIGH-level input

VCC = 2.0 V

1.5 - - V

VIH

voltage

VCC = 4.5 V

3.15 -

• V

VCC = 6.0 V

4.2 - - V

VCC = 9.0 V

6.3 - - V

LOW-level input

VCC = 2.0 V

• - 0.5 V

VIL

voltage

VCC = 4.5 V

• - 1.35 V

VCC = 6.0 V

• - 1.8 V

VCC = 9.0 V

• - 2.7 V

input leakage current

VEE = 0 V; VI = VCC or GND

II

VCC = 6.0 V

• - 1.0 A

VCC = 10.0 V

• - 2.0 A

OFF-state leakage

VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;

IS(OFF)

current

VSW = VCC  VEE; see Figure 11 per channel

• - 1.0 A

all channels

• - 1.0 A

ON-state leakage

VI = VIH or VIL; VSW = VCC  VEE;

• - 1.0 A

IS(ON)

VCC = 10.0 V; VEE = 0 V; see Figure 12

current

ICC

supply current

VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE VCC = 6.0 V

• - 80.0 A

VCC = 10.0 V

• - 160.0 A

Tamb = 40 C to +125 C

HIGH-level input

VCC = 2.0 V

1.5 - - V

VIH

voltage

VCC = 4.5 V

3.15 -

• V

VCC = 6.0 V

4.2 - - V

VCC = 9.0 V

6.3 - - V

LOW-level input

VCC = 2.0 V

• - 0.5 V

VIL

voltage

VCC = 4.5 V

• - 1.35 V

VCC = 6.0 V

• - 1.8 V

VCC = 9.0 V

• - 2.7 V

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Table 7. Static characteristics for 74HC4053 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max

Unit

II

input leakage current

VEE = 0 V; VI = VCC or GND VCC = 6.0 V

• - 1.0 A

VCC = 10.0 V

• - 2.0 A

OFF-state leakage

VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;

IS(OFF)

VSW = VCC  VEE; see Figure 11

current

per channel

• - 1.0 A

all channels

• - 1.0 A

ON-state leakage

VI = VIH or VIL; VSW = VCC  VEE;

• - 1.0 A

IS(ON)

current

VCC = 10.0 V; VEE = 0 V; see Figure 12

supply current

VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC;

ICC

Vos = VCC or VEE VCC = 6.0 V

• - 160.0 A

VCC = 10.0 V

• - 320.0 A

Table 8. Static characteristics for 74HCT4053 Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max

Unit

Tamb = 25 C

HIGH-level input

VCC = 4.5 V to 5.5 V

2.0 1.6 - V

VIH

voltage LOW-level input

VCC = 4.5 V to 5.5 V

• 1.2 0.8 V

VIL

voltage input leakage current

VI = VCC or GND; VCC = 5.5 V; VEE = 0 V

• - 0.1 A

II

OFF-state leakage

VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;

IS(OFF)

VSW = VCC  VEE; see Figure 11

current

per channel

• - 0.1 A

all channels

• - 0.1 A

ON-state leakage

VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;

• - 0.1 A

IS(ON)

VSW = VCC  VEE; see Figure 12

current supply current

VI = VCC or GND; Vis = VEE or VCC;

ICC

Vos = VCC or VEE VCC = 5.5 V; VEE = 0 V

• - 8.0 A

VCC = 5.0 V; VEE = 5.0 V

• - 16.0 A
• 50 180 A

additional supply

per input; VI = VCC  2.1 V; other inputs at VCC

ICC

or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V

current

CI

input capacitance

• 3.5 - pF

switch capacitance

independent pins nYn

• 5 - pF

Csw

common pins nZ

• 8 - pF

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Table 8. Static characteristics for 74HCT4053 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max

Unit

Tamb = 40 C to +85 C

HIGH-level input

VCC = 4.5 V to 5.5 V

2.0 - - V

VIH

voltage

VIL

LOW-level input

VCC = 4.5 V to 5.5 V

• - 0.8 V

voltage input leakage current

VI = VCC or GND; VCC = 5.5 V; VEE = 0 V

• - 1.0 A

II

OFF-state leakage

VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;

IS(OFF)

current

VSW = VCC  VEE; see Figure 11 per channel

• - 1.0 A

all channels

• - 1.0 A

ON-state leakage

VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;

• - 1.0 A

IS(ON)

VSW = VCC  VEE; see Figure 12

current

ICC

supply current

VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE VCC = 5.5 V; VEE = 0 V

• - 80.0 A

VCC = 5.0 V; VEE = 5.0 V

• - 160.0 A
• - 225 A

additional supply

per input; VI = VCC  2.1 V; other inputs at VCC

ICC

or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V

current

Tamb = 40 C to +125 C

HIGH-level input

VCC = 4.5 V to 5.5 V

2.0 - - V

VIH

voltage LOW-level input

VCC = 4.5 V to 5.5 V

• - 0.8 V

VIL

voltage input leakage current

VI = VCC or GND; VCC = 5.5 V; VEE = 0 V

• - 1.0 A

II

OFF-state leakage

VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;

IS(OFF)

VSW = VCC  VEE; see Figure 11

current

per channel

• - 1.0 A

all channels

• - 1.0 A

ON-state leakage

VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;

• - 1.0 A

IS(ON)

VSW = VCC  VEE; see Figure 12

current supply current

VI = VCC or GND; Vis = VEE or VCC;

ICC

Vos = VCC or VEE VCC = 5.5 V; VEE = 0 V

• - 160.0 A

VCC = 5.0 V; VEE = 5.0 V

• - 320.0 A
• - 245 A

additional supply

per input; VI = VCC  2.1 V; other inputs at VCC

ICC

or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V

current

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Page 13

11. Dynamic characteristics

Table 9. Dynamic characteristics for 74HC4053 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 25 C

[1]

propagation delay Vis to Vos; RL =  ; see Figure 13 tpd

VCC = 2.0 V; VEE = 0 V

• 15 60 ns

VCC = 4.5 V; VEE = 0 V

• 5 12 ns

VCC = 6.0 V; VEE = 0 V

• 4 10 ns

VCC = 4.5 V; VEE = 4.5 V

• 4 8 ns

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Page 14

Table 9. Dynamic characteristics for 74HC4053 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

[2]

ton turn-on time

E to Vos; RL = ; see Figure 14 VCC = 2.0 V; VEE = 0 V

• 60 220 ns

VCC = 4.5 V; VEE = 0 V

• 20 44 ns

VCC = 5.0 V; VEE = 0 V; CL = 15 pF

• 17 - ns

VCC = 6.0 V; VEE = 0 V

• 16 37 ns

VCC = 4.5 V; VEE = 4.5 V

• 15 31 ns

[2]

Sn to Vos; RL = ; see Figure 14 VCC = 2.0 V; VEE = 0 V

• 75 220 ns

VCC = 4.5 V; VEE = 0 V

• 25 44 ns

VCC = 5.0 V; VEE = 0 V; CL = 15 pF

• 21 - ns

VCC = 6.0 V; VEE = 0 V

• 20 37 ns

VCC = 4.5 V; VEE = 4.5 V

• 15 31 ns

[3]

turn-off time

E to Vos; RL = 1 k; see Figure 14

toff

VCC = 2.0 V; VEE = 0 V

• 63 210 ns

VCC = 4.5 V; VEE = 0 V

• 21 42 ns

VCC = 5.0 V; VEE = 0 V; CL = 15 pF

• 18 - ns

VCC = 6.0 V; VEE = 0 V

• 17 36 ns

VCC = 4.5 V; VEE = 4.5 V

• 15 29 ns

[3]

Sn to Vos; RL = 1 k; see Figure 14 VCC = 2.0 V; VEE = 0 V

• 60 210 ns

VCC = 4.5 V; VEE = 0 V

• 20 42 ns

VCC = 5.0 V; VEE = 0 V; CL = 15 pF

• 17 - ns

VCC = 6.0 V; VEE = 0 V

• 16 36 ns

VCC = 4.5 V; VEE = 4.5 V

• 15 29 ns

[4] -

power dissipation

per switch; VI = GND to VCC

36 - pF

CPD capacitance Tamb = 40 C to +85 C

[1]

propagation delay Vis to Vos; RL =  ; see Figure 13 tpd

VCC = 2.0 V; VEE = 0 V

• - 75 ns

VCC = 4.5 V; VEE = 0 V

• - 15 ns

VCC = 6.0 V; VEE = 0 V

• - 13 ns

VCC = 4.5 V; VEE = 4.5 V

• - 10 ns

14 of 32

Page 15

Table 9. Dynamic characteristics for 74HC4053 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

[2]

ton turn-on time

E to Vos; RL = ; see Figure 14 VCC = 2.0 V; VEE = 0 V

• - 275 ns

VCC = 4.5 V; VEE = 0 V

• - 55 ns

VCC = 6.0 V; VEE = 0 V

• - 47 ns

VCC = 4.5 V; VEE = 4.5 V

• - 39 ns

[2]

Sn to Vos; RL = ; see Figure 14 VCC = 2.0 V; VEE = 0 V

• - 275 ns

VCC = 4.5 V; VEE = 0 V

• - 55 ns

VCC = 6.0 V; VEE = 0 V

• - 47 ns

VCC = 4.5 V; VEE = 4.5 V

• - 39 ns

[3]

turn-off time

E to Vos; RL = 1 k; see Figure 14

toff

VCC = 2.0 V; VEE = 0 V

• - 265 ns

VCC = 4.5 V; VEE = 0 V

• - 53 ns

VCC = 6.0 V; VEE = 0 V

• - 45 ns

VCC = 4.5 V; VEE = 4.5 V

• - 36 ns

[3]

Sn to Vos; RL = 1 k; see Figure 14 VCC = 2.0 V; VEE = 0 V

• - 265 ns

VCC = 4.5 V; VEE = 0 V

• - 53 ns

VCC = 6.0 V; VEE = 0 V

• - 45 ns

VCC = 4.5 V; VEE = 4.5 V

• - 36 ns

Tamb = 40 C to +125 C

[1]

propagation delay Vis to Vos; RL =  ; see Figure 13 tpd

VCC = 2.0 V; VEE = 0 V

• - 90 ns

VCC = 4.5 V; VEE = 0 V

• - 18 ns

VCC = 6.0 V; VEE = 0 V

• - 15 ns

VCC = 4.5 V; VEE = 4.5 V

• - 12 ns

[2]

turn-on time

E to Vos; RL = ; see Figure 14

ton

VCC = 2.0 V; VEE = 0 V

• - 330 ns

VCC = 4.5 V; VEE = 0 V

• - 66 ns

VCC = 6.0 V; VEE = 0 V

• - 56 ns

VCC = 4.5 V; VEE = 4.5 V

• - 47 ns

[2]

Sn to Vos; RL = ; see Figure 14 VCC = 2.0 V; VEE = 0 V

• - 330 ns

VCC = 4.5 V; VEE = 0 V

• - 66 ns

VCC = 6.0 V; VEE = 0 V

• - 56 ns

VCC = 4.5 V; VEE = 4.5 V

• - 47 ns

15 of 32

Page 16

Table 9. Dynamic characteristics for 74HC4053 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

[3]

toff turn-off time

E to Vos; RL = 1 k; see Figure 14 VCC = 2.0 V; VEE = 0 V

• - 315 ns

VCC = 4.5 V; VEE = 0 V

• - 63 ns

VCC = 6.0 V; VEE = 0 V

• - 54 ns

VCC = 4.5 V; VEE = 4.5 V

• - 44 ns

[3]

Sn to Vos; RL = 1 k; see Figure 14 VCC = 2.0 V; VEE = 0 V

• - 315 ns

VCC = 4.5 V; VEE = 0 V

• - 63 ns

VCC = 6.0 V; VEE = 0 V

• - 54 ns

VCC = 4.5 V; VEE = 4.5 V

• - 44 ns

[1] tpd is the same as tPHL and tPLH. [2] ton is the same as tPZH and tPZL. [3] toff is the same as tPHZ and tPLZ. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + {(CL + Csw)  VCC2  fo} where: fi = input frequency in MHz; fo = output frequency in MHz; N = number of inputs switching; {(CL + Csw)  VCC2  fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V.

Table 10. Dynamic characteristics for 74HCT4053 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 25 C

[1]

propagation delay Vis to Vos; RL = ; see Figure 13 tpd

VCC = 4.5 V; VEE = 0 V

• 5 12 ns

VCC = 4.5 V; VEE = 4.5 V

• 4 8 ns

[2]

turn-on time

E to Vos; RL = 1 k; see Figure 14

ton

VCC = 4.5 V; VEE = 0 V

• 27 48 ns

VCC = 5.0 V; VEE = 0 V; CL = 15 pF

• 23 - ns

VCC = 4.5 V; VEE = 4.5 V

• 16 34 ns

[2]

Sn to Vos; RL = 1 k; see Figure 14 VCC = 4.5 V; VEE = 0 V

• 25 48 ns

VCC = 5.0 V; VEE = 0 V; CL = 15 pF

• 21 - ns

VCC = 4.5 V; VEE = 4.5 V

• 16 34 ns

16 of 32

Page 17

Table 10. Dynamic characteristics for 74HCT4053 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

[3]

toff turn-off time

E to Vos; RL = 1 k; see Figure 14 VCC = 4.5 V; VEE = 0 V

• 24 44 ns

VCC = 5.0 V; VEE = 0 V; CL = 15 pF

• 20 - ns

VCC = 4.5 V; VEE = 4.5 V

• 15 31 ns

[3]

Sn to Vos; RL = 1 k; see Figure 14 VCC = 4.5 V; VEE = 0 V

• 22 44 ns

VCC = 5.0 V; VEE = 0 V; CL = 15 pF

• 19 - ns

VCC = 4.5 V; VEE = 4.5 V

• 15 31 ns

[4] -

power dissipation

per switch; VI = GND to VCC  1.5 V

36 - pF

CPD capacitance Tamb = 40 C to +85 C

[1]

propagation delay Vis to Vos; RL = ; see Figure 13 tpd

VCC = 4.5 V; VEE = 0 V

• - 15 ns

VCC = 4.5 V; VEE = 4.5 V

• - 10 ns

[2]

turn-on time

E to Vos; RL = 1 k; see Figure 14

ton

VCC = 4.5 V; VEE = 0 V

• - 60 ns

VCC = 4.5 V; VEE = 4.5 V

• - 43 ns

[2]

Sn to Vos; RL = 1 k; see Figure 14 VCC = 4.5 V; VEE = 0 V

• - 60 ns

VCC = 4.5 V; VEE = 4.5 V

• - 43 ns

[3]

turn-off time

E to Vos; RL = 1 k; see Figure 14

toff

VCC = 4.5 V; VEE = 0 V

• - 55 ns

VCC = 4.5 V; VEE = 4.5 V

• - 39 ns

[3]

Sn to Vos; RL = 1 k; see Figure 14 VCC = 4.5 V; VEE = 0 V

• - 55 ns

VCC = 4.5 V; VEE = 4.5 V

• - 39 ns

Tamb = 40 C to +125 C

[1]

propagation delay Vis to Vos; RL = ; see Figure 13 tpd

VCC = 4.5 V; VEE = 0 V

• - 18 ns

VCC = 4.5 V; VEE = 4.5 V

• - 12 ns

[2]

turn-on time

E to Vos; RL = 1 k; see Figure 14

ton

VCC = 4.5 V; VEE = 0 V

• - 72 ns

VCC = 4.5 V; VEE = 4.5 V

• - 51 ns

[2]

Sn to Vos; RL = 1 k; see Figure 14 VCC = 4.5 V; VEE = 0 V

• - 72 ns

VCC = 4.5 V; VEE = 4.5 V

• - 51 ns

17 of 32

Page 18

Table 10. Dynamic characteristics for 74HCT4053 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter

Conditions

Min Typ Max Unit

[3]

toff turn-off time

E to Vos; RL = 1 k; see Figure 14 VCC = 4.5 V; VEE = 0 V

• - 66 ns

VCC = 4.5 V; VEE = 4.5 V

• - 47 ns

[3]

Sn to Vos; RL = 1 k; see Figure 14 VCC = 4.5 V; VEE = 0 V

• - 66 ns

VCC = 4.5 V; VEE = 4.5 V

• - 47 ns

[1] tpd is the same as tPHL and tPLH. [2] ton is the same as tPZH and tPZL. [3] toff is the same as tPHZ and tPLZ. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + {(CL + Csw)  VCC2  fo} where: fi = input frequency in MHz; fo = output frequency in MHz; N = number of inputs switching; {(CL + Csw)  VCC2  fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V.

18 of 32

Page 19

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Page 20

Table 11. Test data

[2]

tPHL, tPLH

pulse

< 2 ns

6 ns

50 pF

1 k

open

[2]

tPZH, tPHZ

VCC

< 2 ns

6 ns

50 pF

1 k

VEE

[2]

tPZL, tPLZ

VEE

< 2 ns

6 ns

50 pF

1 k

VCC

[1] tr = tf = 6 ns; when measuring fmax, there is no constraint to tr and tf with 50 % duty factor. [2] VI values: a) For 74HC4053: VI = VCC b) For 74HCT4053: VI = 3 V

11.1 Additional dynamic characteristics

Table 12. Additional dynamic characteristics Recommended conditions and typical values; GND = 0 V; Tamb = 25 C; CL = 50 pF. Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nYn or nZ, whichever is assigned as an output. Symbol

Parameter

Conditions

Min Typ Max Unit

fi = 1 kHz; RL = 10 k; see Figure 16

sine-wave distortion

dsin

Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = 2.25 V

• 0.04 -

%

Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = 4.5 V

• 0.02 -

%

fi = 10 kHz; RL = 10 k; see Figure 16 Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = 2.25 V

• 0.12 -

%

Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = 4.5 V

• 0.06 -

%

RL = 600 ; fi = 1 MHz; see Figure 17

isolation (OFF-state)

iso

[1] -

VCC = 2.25 V; VEE = 2.25 V

50 -

dB

[1] -

VCC = 4.5 V; VEE = 4.5 V

50 -

dB

between two switches/multiplexers;

Xtalk

crosstalk

RL = 600 ; fi = 1 MHz; see Figure 18

[1] -

VCC = 2.25 V; VEE = 2.25 V

60 -

dB

[1] -

VCC = 4.5 V; VEE = 4.5 V

60 -

dB

peak-to-peak value; between control and any

crosstalk voltage

Vct

switch; RL = 600 ; fi = 1 MHz; E or Sn square wave between VCC and GND; tr = tf = 6 ns; see Figure 19 VCC = 4.5 V; VEE = 0 V

• 110 -

mV

VCC = 4.5 V; VEE = 4.5 V

• 220 -

mV

RL = 50 ; see Figure 20

3 dB frequency response

f(3dB)

[2] -

VCC = 2.25 V; VEE = 2.25 V

160 -

MHz

[2] -

VCC = 4.5 V; VEE = 4.5 V

170 -

MHz

[1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 ). [2] Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 ).

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Page 21

21 of 32

Page 22

22 of 32

Page 23

23 of 32

Page 24

12. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

ME

D

A2 A

A1

L

c

e

w M

Z

b1

(e ) 1

b

b2

MH

9

16

pin 1 index

E

1

8

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

95-01-14

SOT38-4

03-02-13

Fig 21. Package outline SOT38-4 (DIP16)

24 of 32

Page 25

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A X

c

y

HE

v M A

Z

16

9

Q

A2

A (A ) 3

A1

pin 1 index

θ Lp L

1

8

e

detail X

w M bp

0 2.5 5 mm scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT109-1

076E07

MS-012

03-02-19

Fig 22. Package outline SOT109-1 (SO16)

25 of 32

Page 26

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A X

c

y

HE

v M A

Z

9

16

Q

A2

A (A )

A1

3

pin 1 index

θ Lp L

8

1

detail X

w M bp

e

0 2.5 5 mm scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

MO-150

SOT338-1

03-02-19

Fig 23. Package outline SOT338-1 (SSOP16)

26 of 32

Page 27

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

E

A

D

X

c

y

HE

v M A

Z

9

16

Q (A )

A2

3 A

A1

pin 1 index

θ Lp L

1

8

detail X

w M bp

e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT403-1

MO-153

03-02-18

Fig 24. Package outline SOT403-1 (TSSOP16)

27 of 32

Page 28

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT763-1

16 terminals; body 2.5 x 3.5 x 0.85 mm

A B

D

A A1

E

c

detail X

terminal 1 index area

C

terminal 1

e1

index area

y

y1 C

e

v M C A B

b

w M C

2

7

L

1

8

Eh

e

16

9

15

10

Dh

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Fig 25. Package outline SOT763-1 (DHVQFN16)

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Page 29

13. Abbreviations

Table 13. Abbreviations Acronym

Description

CMOS

Complementary Metal-Oxide Semiconductor

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

14. Revision history

Table 14. Revision history

Change notice

Document ID

Release date

Data sheet status

74HC_HCT4053 v.8

20120719

-

• CDM added to features.

Modifications: 74HC_HCT4053 v.7

20111213

-

• Legal pages updated.

Modifications: 74HC_HCT4053 v.6

20110511

-

74HC_HCT4053 v.5

20110118

-

74HC_HCT4053 v.4

20060509

-

74HC_HCT4053 v.3

20060315

-

74HC_HCT4053_CNV v.2 19901201

Product specification

-

Supersedes 74HC_HCT4053 v.7

74HC_HCT4053 v.6

74HC_HCT4053 v.5 74HC_HCT4053 v.4 74HC_HCT4053 v.3 74HC_HCT4053_CNV v.2 -

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15. Legal information

15.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

30 of 32

Page 31

Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

16. Contact information

For more information, please visit: http://www.nxp.com

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, please send an email to: salesaddresses@nxp.com

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17. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

9 Recommended operating conditions. . . . . . . . 6 10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 11.1 Additional dynamic characteristics . . . . . . . . . 20 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 29 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 29 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 16 Contact information. . . . . . . . . . . . . . . . . . . . . 31 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2012.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 July 2012 Document identifier: 74HC_HCT4053