74HC4052 PHILIPS

Document overview

  • PDF pages: 27

Technical content

Page 1

INTEGRATED CIRCUITS

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FEATURES

  • Wide analog input voltage range from −5 V to +5 V
  • Low ON-resistance: – 80 Ω (typical) at VCC − VEE = 4.5 V – 70 Ω (typical) at VCC − VEE = 6.0 V – 60 Ω (typical) at VCC − VEE = 9.0 V
  • Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals
  • Typical “break before make” built in
  • Complies with JEDEC standard no. 7A
  • ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V.
  • Specified from −40 °C to +85 °C and −40 °C to +125 °C.

APPLICATIONS

  • Analog multiplexing and demultiplexing
  • Digital multiplexing and demultiplexing
  • Signal gating.

FUNCTION TABLE

DESCRIPTION

The 74HC4052 and 74HCT4052 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4052B. They are specified in compliance with JEDEC standard no. 7A. The 74HC4052 and 74HCT4052 are dual 4-channel analog multiplexers or demultiplexers with common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ). The common channel select logics include two digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0 and S1. When pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins S0

and S1. VCC and GND are the supply voltage pins for the digital control inputs (pins S0, S1, and E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4052 and 4.5 V to 5.5 V for 74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC − VEE may not exceed 10.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).

Column 1 Column 2 Column 3 Column 4
INPUT(1) CHANNEL BETWEEN
E S1 S0
L L L nY0 and nZ
L L H nY1 and nZ
L H L nY2 and nZ
L H H nY3 and nZ
H X X none

Note 1. H = HIGH voltage level L = LOW voltage level X = don’t care.

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QUICK REFERENCE DATA

VEE = GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
74HC4052 74HCT4052
t /t PZH PZL turn-on time E or Sn to V os C = 15 pF; R = 1 kΩ; L L V = 5 V CC 28 18 ns
t /t PHZ PLZ turn-off time E or Sn to V os C = 15 pF; R = 1 kΩ; L L V = 5 V CC 21 13 ns
C I input capacitance 3.5 3.5 pF
C PD power dissipation capacitance per switch notes 1 and 2 57 57 pF
C S maximum switch capacitance independent (Y) 5 5 pF
common (Z) 12 12 pF

Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ[(CL + CS) × VCC2 × fo] where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; CS = maximum switch capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; Σ[(CL + CS) × VCC2 × fo] = sum of the outputs. 2. For 74HC4052 the condition is VI = GND to VCC For 74HCT4052 the condition is VI = GND to VCC − 1.5 V.

ORDERING INFORMATION

TYPE NUMBER PACKAGE
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74HC4052D −40 °C to +125 °C 16 SO16 plastic SOT109-3
74HCT4052D −40 °C to +125 °C 16 SO16 plastic SOT109-3
74HC4052DB −40 °C to +125 °C 16 SSOP16 plastic SOT338-1
74HCT4052DB −40 °C to +125 °C 16 SSOP16 plastic SOT338-1
74HC4052N −40 °C to +125 °C 16 DIP16 plastic SOT38-9
74HCT4052N −40 °C to +125 °C 16 DIP16 plastic SOT38-9
74HC4052PW −40 °C to +125 °C 16 TSSOP16 plastic SOT403-1
74HC4052BQ −40 °C to +125 °C 16 DHVQFN16 plastic SOT763-1
74HCT4052BQ −40 °C to +125 °C 16 DHVQFN16 plastic SOT763-1

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PINNING

PIN SYMBOL DESCRIPTION
1 2Y0 independent input or output
2 2Y2 independent input or output
3 2Z common input or output
4 2Y3 independent input or output
5 2Y1 independent input or output
6 E enable input (active LOW)
7 V EE negative supply voltage
8 GND ground (0 V)
9 S1 select logic input
10 S0 select logic input
11 1Y3 independent input or output
12 1Y0 independent input or output
13 1Z common input or output
14 1Y1 independent input or output
15 1Y2 independent input or output
16 V CC positive supply voltage
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LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to VEE = GND (ground = 0 V); note 1.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V CC supply voltage −0.5 +11.0 V
I IK input diode current V < −0.5 V or V > V + 0.5 V I I CC − ±20 mA
I SK switch diode current V < −0.5 V or V > V + 0.5 V S S CC − ±20 mA
I S switch current −0.5 V < V < V + 0.5 V S CC − ±25 mA
I EE V current EE − ±20 mA
I ; I CC GND V or GND current CC − ±50 mA
T stg storage temperature −65 +150 °C
P tot power dissipation T = −40 °C to +125 °C; note amb − 500 mW
P S power dissipation per switch − 100 mW

Notes 1. To avoid drawing VCC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into pins nZ, no VCC current will flow out of pins nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed VCC or VEE. 2. For DIP16 packages: above 70 °C derate linearly with 12 mW/K. For SO16 packages: above 70 °C derate linearly with 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C derate linearly with 4.5 mW/K.

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RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS 74HC4052 74HCT4052 UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
V CC supply voltage see Figs 7 and 8 V −GND CC V −V CC EE 2.0 2.0 5.0 5.0 10.0 10.0 4.5 2.0 5.0 5.0 5.5 10.0 V V
V I input voltage GND − V CC GND − V CC V
V S switch voltage V EE − V CC V EE − V CC V
T amb operating ambient temperature see DC and AC characteristics per device −40 +25 +85 −40 +25 +85 °C
−40 − +125 −40 − +125 °C
t, t r f input rise and fall times V = 2.0 V CC − 6.0 1000 − 6.0 500 ns
V = 4.5 V CC − 6.0 500 − 6.0 500 ns
V = 6.0 V CC − 6.0 400 − 6.0 500 ns
V = 10.0 V CC − 6.0 250 − 6.0 500 ns
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DC CHARACTERISTICS

Family 74HC4052 Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input; Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output; voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER V (V) CC V (V) EE
T = −40 °C to +85 °C; note 1 amb
V IH HIGH-level input voltage 2.0 − 1.5 1.2 − V
4.5 − 3.15 2.4 − V
6.0 − 4.2 3.2 − V
9.0 − 6.3 4.7 − V
V IL LOW-level input voltage 2.0 − − 0.8 0.5 V
4.5 − − 2.1 1.35 V
6.0 − − 2.8 1.8 V
9.0 − − 4.3 2.7 V
I LI input leakage current V = V or GND I CC 6.0 0 − − ±1.0 µA
10.0 0 − − ±2.0 µA
I S(OFF) analog switch OFF-state current V = V or V IL; I IH V S= V −V EE; see Fig.9 CC per channel all channels 10.0 10.0 0 0 − − − − ±1.0 ±2.0 µA µA
I S(ON) analog switch ON-state current V = V or V IL; I IH V S= V −V EE; see Fig.10 CC 10.0 0 − − ±2.0 µA
I CC quiescent supply current V = V or GND; I CC V = V or V CC; is EE V = V or V os CC EE 6.0 0 − − 80.0 µA
10.0 0 − − 160.0 µA

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SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER V (V) CC V (V) EE
T = −40 °C to +125 °C amb
V IH HIGH-level input voltage 2.0 − 1.5 − − V
4.5 − 3.15 − − V
6.0 − 4.2 − − V
9.0 − 6.3 − − V
V IL LOW-level input voltage 2.0 − − − 0.5 V
4.5 − − − 1.35 V
6.0 − − − 1.8 V
9.0 − − − 2.7 V
I LI input leakage current V = V or GND I CC 6.0 0 − − ±1.0 µA
10.0 0 − − ±2.0 µA
I S(OFF) analog switch OFF-state current V = V or V IL; I IH V S= V −V EE; see Fig.9 CC per channel all channels 10.0 10.0 0 0 − − − − ±1.0 ±2.0 µA µA
I S(ON) analog switch ON-state current V = V or V IL; I IH V S= V −V EE; see Fig.10 CC 10.0 0 − − ±2.0 µA
I CC quiescent supply current V = V or GND; I CC V = V or V CC; is EE V = V or V os CC EE 6.0 0 − − 160 µA
10.0 0 − − 320.0 µA

Note 1. All typical values are measured at Tamb = 25 °C.

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Family 74HCT4052 Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input; Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output; voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER V (V) CC V (V) EE
T = −40 °C to +85 °C; note 1 amb
V IH HIGH-level input voltage 4.5 to 5.5 − 2.0 1.6 − V
V IL LOW-level input voltage 4.5 to 5.5 − − 1.2 0.8 V
I LI input leakage current V = V or GND I CC 5.5 0 − − ±1.0 µA
I S(OFF) analog switch OFF-state current V = V or V IL; I IH V S= V −V EE; see Fig.9 CC per channel all channels 10.0 10.0 0 0 − − − − ±1.0 ±2.0 µA µA
I S(ON) analog switch ON-state current V = V or V IL; I IH V S= V −V EE; see Fig.10 CC 10.0 0 − − ±2.0 µA
I CC quiescent supply current V = V or GND; I CC V = V or V CC; is EE V = V or V os CC EE 5.5 0 − − 80.0 µA
5.0 −5.0 − − 160.0 µA
∆I CC additional quiescent supply current per input V = V −2.1 V; other inputs I CC at V or GND CC 4.5 to 5.5 0 − 45 202.5 µA
T = −40 °C to +125 °C amb
V IH HIGH-level input voltage 4.5 to 5.5 − 2.0 − − V
V IL LOW-level input voltage 4.5 to 5.5 − − − 0.8 V
I LI input leakage current V = V or GND I CC 5.5 0 − − ±1.0 µA
I S(OFF) analog switch OFF-state current V = V or V IL; I IH V S= V −V EE; see Fig.9 CC per channel all channels 10.0 10.0 0 0 − − − − ±1.0 ±2.0 µA µA
I S(ON) analog switch ON-state current V = V or V IL; I IH V S= V −V EE; see Fig.10 CC 10.0 0 − − ±2.0 µA
I CC quiescent supply current V = V or GND; I CC V = V or V CC; is EE V = V or V os CC EE 5.5 0 − − 160.0 µA
5.0 −5.0 − − 320.0 µA
∆I CC additional quiescent supply current per input V = V −2.1 V; other inputs I CC at V or GND CC 4.5 to 5.5 0 − − 220.5 µA

Note 1. All typical values are measured at Tamb = 25 °C.

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Resistance RON for 74HC4052 and 74HCT4052 Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input; see notes 1 and 2; see Fig.11.

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER V (V) CC V (V) EE I (µA) S
T = −40 °C to +85 °C; note 3 amb
R ON(peak) ON-resistance (peak) V = V to V EE; is CC V = V or V I IH IL 2.0 0 100 − − − Ω
4.5 0 1000 − 100 225 Ω
6.0 0 1000 − 90 200 Ω
4.5 −4.5 1000 − 70 165 Ω
R ON(rail) ON-resistance (rail) V = V EE; is V = V or V I IH IL 2.0 0 100 − 150 − Ω
4.5 0 1000 − 80 175 Ω
6.0 0 1000 − 70 150 Ω
4.5 −4.5 1000 − 60 130 Ω
V = V CC; is V = V or V I IH IL 2.0 0 100 − 150 − Ω
4.5 0 1000 − 90 200 Ω
6.0 0 1000 − 80 175 Ω
4.5 −4.5 1000 − 65 150 Ω
∆R ON maximum ON-resistance difference between any two channels V = V to V EE; is CC V = V or V I IH IL 2.0 0 − − − − Ω
4.5 0 − − 9 − Ω
6.0 0 − − 8 − Ω
4.5 −4.5 − − 6 − Ω
T = −40 °C to +125 °C amb
R ON(peak) ON-resistance (peak) V = V to V EE; is CC V = V or V I IH IL 2.0 0 100 − − − Ω
4.5 0 1000 − − 270 Ω
6.0 0 1000 − − 240 Ω
4.5 −4.5 1000 − − 195 Ω
R ON(rail) ON-resistance (rail) V = V EE; is V = V or V I IH IL 2.0 0 100 − − − Ω
4.5 0 1000 − − 210 Ω
6.0 0 1000 − − 180 Ω
4.5 −4.5 1000 − − 160 Ω
V = V CC; is V = V or V I IH IL 2.0 0 100 − − − Ω
4.5 0 1000 − − 240 Ω
6.0 0 1000 − − 210 Ω
4.5 −4.5 1000 − − 180 Ω

Notes 1. For 74HC4052: VCC − GND or VCC − VEE = 2.0, 4.5, 6.0 and 9.0 V; for 74HCT4052: VCC − GND = 4.5 and 5.5 V, VCC − VEE = 2.0, 4.5, 6.0 and 9.0 V. 2. When supply voltages (VCC − VEE) near 2.0 V the analog switch ON-resistance becomes extremely non-linear. When using a supply of 2 V, it is recommended to use these devices only for transmitting digital signals. 3. All typical values are measured at Tamb = 25 °C.

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AC CHARACTERISTICS

Type 74HC4052 GND = 0 V; tr = tf = 6 ns; CL = 50 pF.

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER V (V) CC V (V) EE
T = −40 °C to +85 °C; note 1 amb
t /t PHL PLH propagation delay V to V is os R = ∞; see Fig.19 L 2.0 0 − 14 75 ns
4.5 0 − 5 15 ns
6.0 0 − 4 13 ns
4.5 −4.5 − 4 10 ns
t /t PZH PZL turn-on time E, Sn to V os R = ∞; see Figs 20, L 22 and 21 2.0 0 − 105 405 ns
4.5 0 − 38 81 ns
6.0 0 − 30 69 ns
4.5 −4.5 − 26 58 ns
t /t PHZ PLZ turn-off time E, Sn to V os R = 1 kΩ; see Figs 20, L 22 and 21 2.0 0 − 74 315 ns
4.5 0 − 27 63 ns
6.0 0 − 22 54 ns
4.5 −4.5 − 22 48 ns
T = −40 °C to +125 °C amb
t /t PHL PLH propagation delay V to V is os R = ∞; see Fig.19 L 2.0 0 − − 90 ns
4.5 0 − − 18 ns
6.0 0 − − 15 ns
4.5 −4.5 − − 12 ns
t /t PZH PZL turn-on time E, Sn to V os R = ∞; see Figs 20, L 22 and 21 2.0 0 − − 490 ns
4.5 0 − − 98 ns
6.0 0 − − 83 ns
4.5 −4.5 − − 69 ns
t /t PHZ PLZ turn-off time E, Sn to V os R = 1 kΩ; see Figs 20, L 22 and 21 2.0 0 − − 375 ns
4.5 0 − − 75 ns
6.0 0 − − 64 ns
4.5 −4.5 − − 57 ns

Note 1. All typical values are measured at Tamb = 25 °C.

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Type 74HCT4052 GND = 0 V; tr = tf = 6 ns; CL = 50 pF.

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER V (V) CC V (V) EE
T = −40 °C to +85 °C; note 1 amb
t /t PHL PLH propagation delay V to V is os R = ∞; see Fig.19 L 4.5 0 − 5 15 ns
4.5 −4.5 − 4 10 ns
t /t PZH PZL turn-on time E, Sn to V os R = 1 kΩ; see Figs 20, L 22 and 21 4.5 0 − 41 88 ns
4.5 −4.5 − 28 60 ns
t t PHZ PLZ turn-off time E, Sn to V os R = 1 kΩ; see Figs 20, L 22 and 21 4.5 0 − 26 63 ns
4.5 −4.5 − 21 48 ns
T = −40 °C to +125 °C amb
t /t PHL PLH propagation delay V to V is os R = ∞; see Fig.19 L 4.5 0 − − 18 ns
4.5 −4.5 − − 12 ns
t /t PZH PZL turn-on time E, Sn to V os R = 1 kΩ; see Figs 20, L 22 and 21 4.5 0 − − 105 ns
4.5 −4.5 − − 72 ns
t /t PHZ PLZ turn-off time E, Sn to V os R = 1 kΩ; see Figs 20, L 22 and 21 4.5 0 − − 75 ns
4.5 −4.5 − − 57 ns

Note 1. All typical values are measured at Tamb = 25 °C.

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Type 74HC4052 and 74HCT4052 Recommended conditions and typical values; GND = 0 V; Tamb = 25 °C; CL = 50 pF. Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nYn or nZ, whichever is assigned as an output.

SYMBOL PARAMETER TEST CONDITIONS TYP. UNIT
OTHER V is(p-p) (V) V (V) CC V (V) EE
d sin sine-wave distortion f = 1 kHz; R = 10 kΩ; L see Fig.13 4.0 2.25 −2.25 0.04 %
8.0 4.5 −4.5 0.02 %
f = 10 kHz; R = 10 kΩ; L see Fig.13 4.0 2.25 −2.25 0.12 %
8.0 4.5 −4.5 0.06 %
α OFF(feedthr) switch OFF signal feed-through R = 600 Ω; f = 1 MHz; L see Figs 14 and 15 note 1 2.25 −2.25 −50 dB
4.5 −4.5 −50 dB
α ct(s) crosstalk between two switches/multiplexers R = 600 Ω; f = 1 MHz; L see Fig.16 note 1 2.25 −2.25 −60 dB
4.5 −4.5 −60 dB
V ct(p-p) crosstalk voltage between control and any switch (peak-to-peak value) R = 600 Ω; f = 1 MHz; E or Sn, L square-wave between V and CC GND, t = t = 6 ns; see Fig.17 r f − 4.5 0 110 mV
4.5 −4.5 220 mV
f max minimum frequency response (−3dB) R = 50 Ω; see Figs 13 and 18 L note 2 2.25 −2.25 170 MHz
4.5 −4.5 180 MHz
C S maximum switch capacitance independent (Y) − − − 5 pF
common (Z) − − − 12 pF

Notes 1. Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 Ω). 2. Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 Ω).

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AC WAVEFORMS

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tW

handbook, full pagewidth

amplitude

90% negative

VM

input pulse

10%

0 V

tTHL (tf)

tTLH (tr)

tTLH (tr)

tTHL (tf) amplitude

90% positive

VM

input pulse

10%

0 V

tW

MNB059

Column 1 Column 2 Column 3 Column 4 Column 5
FAMILY AMPLITUDE V M t and t r f
f ; PULSE WIDTH max OTHER
74HC4052 V CC 50 % < 2 ns 6 ns
74HCT4052 3.0 V 1.3 V < 2 ns 6 ns

Fig.21 Input pulse definitions.

handbook, full pagewidth

VCC switch open

VCC Vis

RL

VI

VO

PULSE

D.U.T.

GENERATOR

CL

RT

GND VEE MNB058

Column 1 Column 2 Column 3
TEST SWITCH V is
t PZH V EE V CC
t PZL V CC V EE
t PHZ V EE V CC
t PLZ V CC V EE
other open pulse

Definitions for test circuit: RL = load resistance CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance ZO of the pulse generator. tr = tf = 6 ns; when measuring fmax, there is no constraint to tr and tf with 50 % duty factor.

Fig.22 Test circuit for measuring AC performance.

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PACKAGE OUTLINES

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-9

ME

D

A2 A

A1

L

c

b1

e

w M

Z

(e1) MH

b

b2 9

16

pin 1 index

E

1

8

0 5 10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

UNIT A max. A1 min. A2 max. b b1 b2 c D(1) E(1) e e1 L ME MH w Z(1) max.
mm 4.32 0.38 3.56 1.65 1.40 0.51 0.41 1.14 0.76 0.36 0.20 19.3 18.8 6.45 6.24 2.54 7.62 3.81 2.92 8.23 7.62 9.40 8.38 0.254 0.76
inches 0.17 0.015 0.14 0.065 0.055 0.020 0.016 0.045 0.030 0.014 0.008 0.76 0.74 0.254 0.246 0.1 0.3 0.150 0.115 0.324 0.300 0.37 0.33 0.01 0.03

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

97-07-24

SOT38-9

03-03-12

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SO16: plastic small outline package; 16 leads; body width 3.9 mm; body thickness 1.47 mm

SOT109-3

D

E

A X

c

y

HE

v M A

Z

16

9

A2

A (A ) 3

A1

pin 1 index

θ Lp L

1

8

e

detail X

w M bp

0 2.5 5 mm scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ
mm 0 1.75 0 .25 .10 1.55 1.40 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.25 0.25 0.1 0.7 0.3 8o 0o
inches 0 0.069 0 .010 .004 0.061 0.055 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 0.244 0.228 0.041 0.039 0.016 0.01 0.01 0.004 0.028 0.012

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

98-12-23

SOT109-3

MS-012AC

03-02-19

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SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A X

c

y

HE

v M A

Z

9

16

Q

A2

A (A )

A1

3

pin 1 index

θ Lp L

8

1

detail X

w M bp

e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A max. A 1 A 2 A 3 bp c D(1) E (1) e H E L Lp Q v w y Z(1) θ
mm 2 0.21 1 0.05 1 .80 .65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o 0o

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT338-1

MO-150

03-02-19

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TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

E

A

D

X

c

y

HE

v M A

Z

9

16

Q (A )

A2

3 A

A1

pin 1 index

θ Lp L

1

8

detail X

w M bp

e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z(1) θ
mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT403-1

MO-153

03-02-18

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DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT763-1

16 terminals; body 2.5 x 3.5 x 0.85 mm

A B

D

A A1

E

c

detail X

terminal 1 index area

C

terminal 1

e1

index area

y

y1 C

e

v M C A B

b

w M C

2

7

L

1

8

Eh

e

16

9

15

10

Dh

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A(1) max. A1 b c D(1) Dh E(1) Eh e e1 L v w y y1
mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Column 1 Column 2 Column 3 Column 4 Column 5 Column 6 Column 7 Column 8
OUTLINE VERSION REFERENCES EUROPEAN PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT763-1 - - - MO-241 - - - 02-10-17 03-01-27

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DATA SHEET STATUS

Column 1 Column 2 Column 3 Column 4
LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product.
III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

DEFINITIONS

Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

DISCLAIMERS

Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Page 27

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA76

© Koninklijke Philips Electronics N.V. 2004

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

R44/04/pp27

Date of release: 2004 Nov 11

Document order number: 9397 750 14189

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