74HCT4040N

74HC4040 PHILIPS

Document overview

• PDF pages: 24

Technical content

Page 1

1. General description

The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A.

The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP.

A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP.

Each counter stage is a static toggle flip-flop.

2. Features

I Multiple package options I Complies with JEDEC standard no. 7A I ESD protection: N HBM JESD22-A114-C exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from −40 °C to +85 °C and from −40 °C to +125 °C

3. Applications

I Frequency dividing circuits I Time delay circuits I Control counters

4. Quick reference data

Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Symbol

Parameter

Type 74HC4040 tPHL, tPLH

propagation delay CP to Q0 Qn to Qn+1

Conditions

Min Typ Max Unit

CL = 15 pF; VCC = 5 V

• 14 -

ns

CL = 15 pF; VCC = 5 V

• 8 - ns

Page 2

Table 1: Quick reference data …continued GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Symbol

Parameter

fmax

maximum operating frequency input capacitance

Ci

power dissipation

CPD

capacitance

Type 74HCT4040 tPHL, tPLH

propagation delay CP to Q0 Qn to Qn+1 maximum operating

fmax

frequency input capacitance

Ci

power dissipation

CPD

capacitance

Conditions

Min Typ Max Unit

CL = 15 pF; VCC = 5 V

• 90 -

MHz

• 3.5 -

pF

VI = GND to VCC

• 20 -

pF

CL = 15 pF; VCC = 5 V

• 16 -

ns

CL = 15 pF; VCC = 5 V

• 8 - ns

CL = 15 pF; VCC = 5 V

• 79 -

MHz

• 3.5 -

pF

VI = GND to VCC − 1.5 V

• 20 -

pF

[1] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑(CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V.

5. Ordering information

Table 2: Ordering information

74HC4040N

−40 °C to +125 °C

DIP16

long body

74HC4040D

−40 °C to +125 °C

SO16

74HC4040DB −40 °C to +125 °C

SSOP16

plastic dual in-line package; 16 leads (300 mil);

SOT38-1

plastic small outline package; 16 leads; body

SOT109-1

width 3.9 mm plastic shrink small outline package; 16 leads; body

SOT338-1

width 5.3 mm

TSSOP16 plastic thin shrink small outline package; 16 leads;

74HC4040PW −40 °C to +125 °C

SOT403-1

body width 4.4 mm

DHVQFN16 plastic dual in-line compatible thermal enhanced

74HC4040BQ −40 °C to +125 °C

74HCT4040N −40 °C to +125 °C

DIP16

long body

74HCT4040D −40 °C to +125 °C

SO16

SOT763-1

very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm plastic dual in-line package; 16 leads (300 mil);

SOT38-1

plastic small outline package; 16 leads; body

SOT109-1

width 3.9 mm

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Page 3

Table 2: Ordering information …continued

74HCT4040DB −40 °C to +125 °C

SSOP16

plastic shrink small outline package; 16 leads; body

SOT338-1

width 5.3 mm

TSSOP16 plastic thin shrink small outline package; 16 leads;

74HCT4040PW −40 °C to +125 °C

SOT403-1

body width 4.4 mm

DHVQFN16 plastic dual in-line compatible thermal enhanced

74HCT4040BQ −40 °C to +125 °C

SOT763-1

very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm

6. Functional diagram

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Page 4

7. Pinning information

7.1 Pinning

Q11 Q5 Q4 Q6 Q3 Q2 Q1 GND

001aad583

Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16

terminal 1 index area

VCC

Q5 2

15 Q10

Q10

Q4 3

14 Q9

Q9

4

13

Q6

Q7

Q7

4040 Q3 5

12 Q8

Q8 MR

Q2 6

11 MR GND(1)

CP

Q1 7

10 CP

Q0

001aad584

Transparent top view

(1) The substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input Fig 6. Pin configuration DHVQFN16

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Page 5

7.2 Pin description

Table 3: Pin description Symbol

Pin

Q11

1

output 11

Q5

2

output 5

Q4

3

output 4

Q6

4

output 6

Q3

5

output 3

Q2

6

output 2

Q1

7

output 1

GND

8

Q0

9

output 0

CP

10

MR

11

Q8

12

output 8

Q7

13

output 7

Q9

14

output 9

Q10

15

output 10

16

VCC

8. Functional description

8.1 Function table

Table 4: Function table

Description

ground (0 V)

clock input (HIGH-to-LOW, edge-triggered) master reset input (active HIGH)

positive supply voltage

L

no change

↑

L

count

↓ X

H

L

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition.

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Page 6

8.2 Timing diagram

9. Limiting values

Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Max Unit

supply voltage

−0.5 +7

V

VCC input diode current

VI < −0.5 V or VI > VCC + 0.5 V

• ±20 mA

IIK output diode current

VI < −0.5 V or VI > VCC + 0.5 V

• ±20 mA

IOK output source or sink current

−0.5 V < VO < VCC + 0.5 V

• ±25 mA

IO quiescent supply current

• ±50 mA

ICC ground current

• ±50 mA

IGND storage temperature

−65 +150 °C

Tstg

[1]

power dissipation

Tamb = −40 °C to +125 °C

Ptot

DIP16 package

• 750 mW

SO16, SSOP16, TSSOP16 and

• 500 mW

DHVQFN16 packages

[1] For DIP16 packages: above 70 °C, Ptot derates linearly with 12 mW/K. For SO16, SSOP16, TSSOP16 and DHVQFN16 packages, above 70 °C, Ptot derates linearly with 8 mW/K.

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Page 7

10. Recommended operating conditions

Table 6: Recommended operating conditions Symbol

Parameter

Conditions

Min Typ Max Unit

type 74HC4040

supply voltage

2.0 5.0 6.0 V

VCC

input voltage

0 - VCC V

VI

output voltage

0 - VCC V

VO

see Section 11 and 12 per device

ambient temperature

−40 -

+125 °C

Tamb

except for Schmitt-trigger inputs

tr, tf

input rise and fall times

VCC = 2.0 V

• - 1000 ns

VCC = 4.5 V

• 6.0 500 ns

VCC = 6.0 V

• - 400 ns

type 74HCT4040

supply voltage

4.5 5.0 5.5 V

VCC

input voltage

0 - VCC V

VI

output voltage

0 - VCC V

VO

see Section 11 and 12 per device

ambient temperature

−40 -

+125 °C

Tamb

except for Schmitt-trigger inputs

tr, tf

input rise and fall times

VCC = 2.0 V

• - - ns

VCC = 4.5 V

• 6.0 500 ns

VCC = 6.0 V

• - - ns

11. Static characteristics

Table 7: Static characteristics for 74HC4040 Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Typ Max Unit

Tamb = 25 °C

HIGH-level input voltage

VCC = 2.0 V

1.5 1.2 - V

VIH

VCC = 4.5 V

3.15 2.4 - V

VCC = 6.0 V

4.2 3.2 - V

LOW-level input voltage

VCC = 2.0 V

• 0.8 0.5 V

VIL

VCC = 4.5 V

• 2.1 1.35 V

VCC = 6.0 V

• 2.8 1.8 V

HIGH-level output voltage

VI = VIH or VIL

VOH

IO = −20 µA; VCC = 2.0 V

1.9 2.0 - V

IO = −20 µA; VCC = 4.5 V

4.4 4.5 - V

IO = −20 µA; VCC = 6.0 V

5.9 6.0 - V

IO = −4.0 mA; VCC = 4.5 V

3.98 4.32 - V

IO = −5.2 mA; VCC = 6.0 V

5.48 5.81 - V

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Page 8

Table 7: Static characteristics for 74HC4040 …continued Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Typ Max Unit

VOL

LOW-level output voltage

VI = VIH or VIL IO = 20 µA; VCC = 2.0 V

• 0 0.1 V

IO = 20 µA; VCC = 4.5 V

• 0 0.1 V

IO = 20 µA; VCC = 6.0 V

• 0 0.1 V

IO = 4.0 mA; VCC = 4.5 V

• 0.15 0.26 V

IO = 5.2 mA; VCC = 6.0 V

• 0.16 0.26 V

input leakage current

VI = VCC or GND; VCC = 6.0 V

• - 0.1 µA

ILl

quiescent supply current

VI = VCC or GND; IO = 0 A;

ICC

• - 8.0 µA

VCC = 6.0 V

input capacitance

• 3.5 - pF

CI Tamb = −40 °C to +85 °C

HIGH-level input voltage

VCC = 2.0 V

1.5 - - V

VIH

VCC = 4.5 V

3.15 - - V

VCC = 6.0 V

4.2 - - V

LOW-level input voltage

VCC = 2.0 V

• - 0.5 V

VIL

VCC = 4.5 V

• - 1.35 V

VCC = 6.0 V

• - 1.8 V

HIGH-level output voltage

VI = VIH or VIL

VOH

IO = −20 µA; VCC = 2.0 V

1.9 - - V

IO = −20 µA; VCC = 4.5 V

4.4 - - V

IO = −20 µA; VCC = 6.0 V

5.9 - - V

IO = −4.0 mA; VCC = 4.5 V

3.84 - - V

IO = −5.2 mA; VCC = 6.0 V;

5.34 - - V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 20 µA; VCC = 2.0 V

• - 0.1 V

IO = 20 µA; VCC = 4.5 V

• - 0.1 V

IO = 20 µA; VCC = 6.0 V

• - 0.1 V

IO = 4.0 mA; VCC = 4.5 V

• - 0.33 V

IO = 5.2 mA; VCC = 6.0 V

• - 0.33 V

input leakage current

VI = VCC or GND; VCC = 6.0 V

• - 1.0 µA

ILl

• - 80.0 µA

quiescent supply current

VI = VCC or GND; IO = 0 A;

ICC

VCC = 6.0 V

Tamb = −40 °C to +125 °C

HIGH-level input voltage

VCC = 2.0 V

1.5 - - V

VIH

VCC = 4.5 V

3.15 - - V

VCC = 6.0 V

4.2 - - V

LOW-level input voltage

VCC = 2.0 V

• - 0.5 V

VIL

VCC = 4.5 V

• - 1.35 V

VCC = 6.0 V

• - 1.8 V

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Page 9

Table 7: Static characteristics for 74HC4040 …continued Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Typ Max Unit

VOH

HIGH-level output voltage

VI = VIH or VIL IO = −20 µA; VCC = 2.0 V

1.9 - - V

IO = −20 µA; VCC = 4.5 V

4.4 - - V

IO = −20 µA; VCC = 6.0 V

5.9 - - V

IO = −4.0 mA; VCC = 4.5 V

3.7 - - V

IO = −5.2 mA; VCC = 6.0 V;

5.2 - - V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 20 µA; VCC = 2.0 V

• - 0.1 V

IO = 20 µA; VCC = 4.5 V

• - 0.1 V

IO = 20 µA; VCC = 6.0 V

• - 0.1 V

IO = 4.0 mA; VCC = 4.5 V

• - 0.4 V

IO = 5.2 mA; VCC = 6.0 V

• - 0.4 V

input leakage current

VI = VCC or GND; VCC = 6.0 V

• - 1.0 µA

ILl

quiescent supply current

VI = VCC or GND; IO = 0 A;

• - 160.0 µA

ICC

VCC = 6.0 V

Table 8: Static characteristics for 74HCT4040 Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Typ Max Unit

Tamb = 25 °C

HIGH-level input voltage

VCC = 4.5 V to 5.5 V

2.0 1.6 - V

VIH

LOW-level input voltage

VCC = 4.5 V to 5.5 V

• 1.2 0.8 V

VIL

HIGH-level output voltage

VI = VIH or VIL

VOH

IO = −20 µA; VCC = 4.5 V

4.4 4.5 - V

IO = −4.0 mA; VCC = 4.5 V

3.98 4.32 - V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 20 µA; VCC = 4.5 V

• 0 0.1 V

IO = 4.0 mA; VCC = 4.5 V

• 0.15 0.26 V

input leakage current

VI = VCC or GND; VCC = 5.5 V

• - 0.1 µA

ILl

quiescent supply current

VI = VCC or GND; IO = 0 A;

• - 8.0 µA

ICC

VCC = 5.5 V

additional quiescent supply

VI = VCC − 2.1 V; VCC = 4.5 V

∆ICC

current

to 5.5 V; IO = 0 A CP

• 85 306 µA

MR

• 110 396 µA

input capacitance

• 3.5 - pF

CI Tamb = −40 °C to +85 °C

HIGH-level input voltage

VCC = 4.5 V to 5.5 V

2.0 - - V

VIH

LOW-level input voltage

VCC = 4.5 V to 5.5 V

• - 0.8 V

VIL

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Page 10

Table 8: Static characteristics for 74HCT4040 …continued Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Typ Max Unit

VOH

HIGH-level output voltage

VI = VIH or VIL IO = −20 µA; VCC = 4.5 V

4.4 - - V

IO = −4.0 mA; VCC = 4.5 V

3.84 - - V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 20 µA; VCC = 4.5 V

• - 0.1 V

IO = 4.0 mA; VCC = 4.5 V

• - 0.33 V

input leakage current

VI = VCC or GND; VCC = 5.5 V

• - 1.0 µA

ILl

quiescent supply current

VI = VCC or GND; IO = 0 A;

• - 80.0 µA

ICC

VCC = 5.5 V

additional quiescent supply

VI = VCC − 2.1 V; VCC = 4.5 V

∆ICC

current

to 5.5 V; IO = 0 A CP

• - 383 µA

MR

• - 495 µA

Tamb = −40 °C to +125 °C

HIGH-level input voltage

VCC = 4.5 V to 5.5 V

2.0 - - V

VIH

LOW-level input voltage

VCC = 4.5 V to 5.5 V

• - 0.8 V

VIL

HIGH-level output voltage

VI = VIH or VIL

VOH

IO = −20 µA; VCC = 4.5 V

4.4 - - V

IO = −4.0 mA; VCC = 4.5 V

3.7 - - V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 20 µA; VCC = 4.5 V

• - 0.1 V

IO = 4.0 mA; VCC = 4.5 V

• - 0.4 V

input leakage current

VI = VCC or GND; VCC = 5.5 V

• - 1.0 µA

ILl

quiescent supply current

VI = VCC or GND; IO = 0 A;

• - 160.0 µA

ICC

VCC = 5.5 V

additional quiescent supply

VI = VCC − 2.1 V; VCC = 4.5 V

∆ICC

current

to 5.5 V; IO = 0 A CP

• - 417 µA

MR

• - 539 µA

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Page 11

12. Dynamic characteristics

Table 9: Dynamic characteristics for type 74HC4040 GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol

Parameter

Conditions

Min Typ Max Unit

Tamb = 25 °C tPHL, tPLH

propagation delay CP to Q0

see Figure 8 VCC = 2.0 V; CL = 50 pF

• 47 150 ns

VCC = 4.5 V; CL = 50 pF

• 17 30 ns

VCC = 5.0 V; CL = 15 pF

• 14 - ns

VCC = 6.0 V; CL = 50 pF

• 14 26 ns

see Figure 8

propagation delay Qn to Qn+1

VCC = 2.0 V; CL = 50 pF

• 28 100 ns

VCC = 4.5 V; CL = 50 pF

• 10 20 ns

VCC = 5.0 V; CL = 15 pF

• 8 - ns

VCC = 6.0 V; CL = 50 pF

• 8 17 ns

propagation delay MR to Qn

see Figure 8

tPHL

VCC =2.0 V; CL = 50 pF

• 61 185 ns

VCC = 4.5 V; CL = 50 pF

• 22 37 ns

VCC = 6.0 V; CL = 50 pF

• 18 31 ns

tTHL, tTLH

output transition time

see Figure 8 VCC = 2.0 V; CL = 50 pF

• 19 75 ns

VCC = 4.5 V; CL = 50 pF

• 7 15 ns

VCC = 6.0 V; CL = 50 pF

• 6 13 ns

clock pulse width HIGH or LOW

see Figure 8

tW

VCC = 2.0 V; CL = 50 pF

80 14 - ns

VCC = 4.5 V; CL = 50 pF

16 5 - ns

VCC = 6.0 V; CL = 50 pF

14 4 - ns

see Figure 8

master reset pulse width; HIGH

VCC = 2.0 V; CL = 50 pF

80 22 - ns

VCC = 4.5 V; CL = 50 pF

16 8 - ns

VCC = 6.0 V; CL = 50 pF

14 6 - ns

recovery time MR to CP

see Figure 8

trec

VCC = 2.0 V; CL = 50 pF

50 8 - ns

VCC = 4.5 V; CL = 50 pF

10 3 - ns

VCC = 6.0 V; CL = 50 pF

9 2 - ns

maximum operating frequency

see Figure 8

fmax

VCC = 2.0 V; CL = 50 pF

6.0 27 - MHz

VCC = 4.5 V; CL = 50 pF

30 82 - MHz

VCC = 5.0 V; CL = 15 pF

• 90 - MHz

VCC = 6.0 V; CL = 50 pF

35 98 - MHz

power dissipation capacitance

• 20 - pF

CPD

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Page 12

Table 9: Dynamic characteristics for type 74HC4040 …continued GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol

Parameter

Conditions

Min Typ Max Unit

Tamb = −40 °C to +85 °C tPHL, tPLH

propagation delay CP to Q0

see Figure 8 VCC = 2.0 V; CL = 50 pF

• - 190 ns

VCC = 4.5 V; CL = 50 pF

• - 38 ns

VCC = 6.0 V; CL = 50 pF

• - 33 ns

see Figure 8

propagation delay Qn to Qn+1

VCC = 2.0 V; CL = 50 pF

• - 125 ns

VCC = 4.5 V; CL = 50 pF

• - 25 ns

VCC = 6.0 V; CL = 50 pF

• - 21 ns

propagation delay MR to Qn

see Figure 8

tPHL

VCC = 2.0 V; CL = 50 pF

• - 230 ns

VCC = 4.5 V; CL = 50 pF

• - 46 ns

VCC = 6.0 V; CL = 50 pF

• - 39 ns

tTHL, tTLH

output transition time

see Figure 8 VCC = 2.0 V; CL = 50 pF

• - 95 ns

VCC = 4.5 V; CL = 50 pF

• - 19 ns

VCC = 6.0 V; CL = 50 pF

• - 16 ns

clock pulse width HIGH or LOW

see Figure 8

tW

VCC = 2.0 V; CL = 50 pF

100 - - ns

VCC = 4.5 V; CL = 50 pF

20 - - ns

VCC = 6.0 V; CL = 50 pF

17 - - ns

see Figure 8

master reset pulse width; HIGH

VCC = 2.0 V; CL = 50 pF

100 - - ns

VCC = 4.5 V; CL = 50 pF

20 - - ns

VCC = 6.0 V; CL = 50 pF

17 - - ns

recovery time MR to CP

see Figure 8

trec

VCC = 2.0 V; CL = 50 pF

65 - - ns

VCC = 4.5 V; CL = 50 pF

13 - - ns

VCC = 6.0 V; CL = 50 pF

11 - - ns

maximum operating frequency

see Figure 8

fmax

VCC = 2.0 V; CL = 50 pF

4.8 - - MHz

VCC = 4.5 V; CL = 50 pF

24 - - MHz

VCC = 6.0 V; CL = 50 pF

28 - - MHz

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Page 13

Table 9: Dynamic characteristics for type 74HC4040 …continued GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol

Parameter

Conditions

Min Typ Max Unit

Tamb = −40 °C to +125 °C tPHL, tPLH

propagation delay CP to Q0

see Figure 8 VCC = 2.0 V; CL = 50 pF

• - 225 ns

VCC = 4.5 V; CL = 50 pF

• - 45 ns

VCC = 6.0 V; CL = 50 pF

• - 38 ns

see Figure 8

propagation delay Qn to Qn+1

VCC = 2.0 V; CL = 50 pF

• - 150 ns

VCC = 4.5 V; CL = 50 pF

• - 30 ns

VCC = 6.0 V; CL = 50 pF

• - 26 ns

propagation delay MR to Qn

see Figure 8

tPHL

VCC = 2.0 V; CL = 50 pF

• - 280 ns

VCC = 4.5 V; CL = 50 pF

• - 56 ns

VCC = 6.0 V; CL = 50 pF

• - 48 ns

tTHL, tTLH

output transition time

see Figure 8 VCC = 2.0 V; CL = 50 pF

• - 110 ns

VCC = 4.5 V; CL = 50 pF

• - 22 ns

VCC = 6.0 V; CL = 50 pF

• - 19 ns

clock pulse width HIGH or LOW

see Figure 8

tW

VCC = 2.0 V; CL = 50 pF

120 - - ns

VCC = 4.5 V; CL = 50 pF

24 - - ns

VCC = 6.0 V; CL = 50 pF

20 - - ns

see Figure 8

master reset pulse width; HIGH

VCC = 2.0 V; CL = 50 pF

120 - - ns

VCC = 4.5 V; CL = 50 pF

24 - - ns

VCC = 6.0 V; CL = 50 pF

20 - - ns

recovery time MR to CP

see Figure 8

trec

VCC = 2.0 V; CL = 50 pF

75 - - ns

VCC = 4.5 V; CL = 50 pF

15 - - ns

VCC = 6.0 V; CL = 50 pF

13 - - ns

maximum operating frequency

see Figure 8

fmax

VCC = 2.0 V; CL = 50 pF

4.0 - - MHz

VCC = 4.5 V; CL = 50 pF

20 - - MHz

VCC = 6.0 V; CL = 50 pF

24 - - MHz

[1] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑(CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V.

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Page 14

Table 10: Dynamic characteristics for type 74HCT4040 GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol

Parameter

Conditions

Min Typ Max Unit

Tamb = 25 °C tPHL, tPLH

propagation delay CP to Q0

see Figure 8 VCC = 4.5 V; CL = 50 pF

• 19 40 ns

VCC = 5.0 V; CL = 15 pF

• 16 - ns

see Figure 8

propagation delay Qn to Qn+1

VCC = 4.5 V; CL = 50 pF

• 10 20 ns

VCC = 5.0 V; CL = 15 pF

• 8 - ns

propagation delay MR to Qn

VCC = 4.5 V; CL = 50 pF;

• 23 45 ns

tPHL

see Figure 8;

tTHL, tTLH

output transition time

VCC = 4.5 V; CL = 50 pF;

• 7 15 ns

see Figure 8;

clock pulse width HIGH or LOW

VCC = 4.5 V; CL = 50 pF;

16 7 - ns

tW

see Figure 8; VCC = 4.5 V; CL = 50 pF;

16 6 - ns

master reset pulse width; HIGH

see Figure 8;

recovery time MR to CP

VCC = 4.5 V; CL = 50 pF;

10 2 - ns

trec

see Figure 8;

maximum operating frequency

see Figure 8

fmax

VCC = 4.5 V; CL = 50 pF

30 72 - MHz

VCC = 5.0 V; CL = 15 pF

• 79 - MHz

[1] -

power dissipation capacitance

20 - pF

CPD

per package

Tamb = −40 °C to +85 °C tPHL, tPLH

propagation delay CP to Q0

VCC = 4.5 V; CL = 50 pF;

• - 50 ns

see Figure 8; VCC = 4.5 V; CL = 50 pF;

• - 25 ns

propagation delay Qn to Qn+1

see Figure 8;

propagation delay MR to Qn

VCC = 4.5 V; CL = 50 pF;

• - 56 ns

tPHL

see Figure 8;

tTHL, tTLH

output transition time

VCC = 4.5 V; CL = 50 pF;

• - 19 ns

see Figure 8;

clock pulse width HIGH or LOW

VCC = 4.5 V; CL = 50 pF;

20 - - ns

tW

see Figure 8; VCC = 4.5 V; CL = 50 pF;

20 - - ns

master reset pulse width; HIGH

see Figure 8;

recovery time MR to CP

VCC = 4.5 V; CL = 50 pF;

13 - - ns

trec

see Figure 8;

maximum operating frequency

VCC = 4.5 V; CL = 50 pF;

24 - - MHz

fmax

see Figure 8;

Tamb = −40 °C to +125 °C tPHL, tPLH

propagation delay CP to Q0

VCC = 4.5 V; CL = 50 pF;

• - 60 ns

see Figure 8; VCC = 4.5 V; CL = 50 pF;

• - 30 ns

propagation delay Qn to Qn+1

see Figure 8

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Page 15

Table 10: Dynamic characteristics for type 74HCT4040 …continued GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9. Symbol

Parameter

Conditions

Min Typ Max Unit

tPHL

propagation delay MR to Qn

VCC = 4.5 V; CL = 50 pF;

• - 68 ns

see Figure 8

tTHL, tTLH

output transition time

VCC = 4.5 V; CL = 50 pF;

• - 22 ns

see Figure 8

clock pulse width HIGH or LOW

VCC = 4.5 V; CL = 50 pF;

24 - - ns

tW

see Figure 8 VCC = 4.5 V; CL = 50 pF;

24 - - ns

master reset pulse width; HIGH

see Figure 8

recovery time MR to CP

VCC = 4.5 V; CL = 50 pF;

15 - - ns

trec

see Figure 8

maximum operating frequency

VCC = 4.5 V; CL = 50 pF;

20 - - MHz

fmax

see Figure 8

[1] CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑(CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V.

13. Waveforms

15 of 24

Page 16

16 of 24

Page 17

14. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil); long body

SOT38-1

ME

D

A2 A

A1

L

c

e

w M

Z

b1

(e ) 1

b

MH

9

16

pin 1 index

E

1

8

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

050G09

MO-001

SC-503-16

SOT38-1

03-02-13

Fig 10. Package outline SOT38-1 (DIP16)

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Page 18

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A X

c

y

HE

v M A

Z

16

9

Q

A2

A (A ) 3

A1

pin 1 index

θ Lp L

1

8

e

detail X

w M bp

0 2.5 5 mm scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT109-1

076E07

MS-012

03-02-19

Fig 11. Package outline SOT109-1 (SO16)

18 of 24

Page 19

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A X

c

y

HE

v M A

Z

9

16

Q

A2

A (A )

A1

3

pin 1 index

θ Lp L

8

1

detail X

w M bp

e

0 2.5 5 mm scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT338-1

MO-150

03-02-19

Fig 12. Package outline SOT338-1 (SSOP16)

19 of 24

Page 20

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

E

A

D

X

c

y

HE

v M A

Z

9

16

Q (A )

A2

3 A

A1

pin 1 index

θ Lp L

1

8

detail X

w M bp

e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT403-1

MO-153

03-02-18

Fig 13. Package outline SOT403-1 (TSSOP16)

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Page 21

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT763-1

16 terminals; body 2.5 x 3.5 x 0.85 mm

A B

D

A A1

E

c

detail X

terminal 1 index area

C

terminal 1

e1

index area

y

y1 C

e

v M C A B

b

w M C

2

7

L

1

8

Eh

e

16

9

15

10

Dh

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Fig 14. Package outline SOT763-1 (DHVQFN16)

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Page 22

15. Revision history

Table 11: Revision history Document ID

Release date

Data sheet

Change Doc.

Supersedes

status

notice number

20050914

Product data

• -

74HC_HCT4040_CNV_2

sheet

• The format of this data sheet has been redesigned to comply with the new presentation and

Modifications:

information standard of Philips Semiconductors

• Reference to family specifications is replaced by the actual information: Section 5 “Ordering information”, Section 7 “Pinning information”, Section 9 “Limiting values”, Section 10 “Recommended operating conditions”, Section 11 “Static characteristics”, Figure 9 “Test circuit”
• Section 14 “Package outline” (DHVQFN16) added

74HC_HCT4040_CNV_2 19901231

Product

• -

-

specification

22 of 24

Page 23

16. Data sheet status

Level Data sheet status [1] Product status [2] [3] Definition

This data sheet contains data from the objective specification for product development. Philips

I Objective data

Development

Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published

II Preliminary data

Qualification

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the

III Product data

Production

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

17. Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

18. Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors

20. Contact information

customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

19. Trademarks

Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners.

For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

23 of 24

Page 24

21. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 5

8.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 Timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . 6 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 Recommended operating conditions. . . . . . . . 7 11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 23

17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 18 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 20 Contact information . . . . . . . . . . . . . . . . . . . . 23

© Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Date of release: 14 September 2005 Document number: 74HC_HCT4040_3

Published in The Netherlands