74HCT3G14GD

74HC3G14 NXP

Document overview

• PDF pages: 18

Technical content

Page 1

1. General description

The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device.

The 74HC3G14; 74HCT3G14 provides three inverting buffers with Schmitt trigger inputs which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

2. Features

I Wide supply voltage range from 2.0 V to 6.0 V I High noise immunity I Low power dissipation I Balanced propagation delays I Unlimited input rise and fall times I Multiple package options I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from −40 °C to +85 °C and −40 °C to +125 °C

3. Applications

I Wave and pulse shaper for highly noisy environments I Astable multivibrators I Monostable multivibrators

4. Ordering information

Table 1. Ordering information

−40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads;

74HC3G14DP

SOT505-2

body width 3 mm; lead length 0.5 mm

74HCT3G14DP

−40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads;

74HC3G14DC

SOT765-1

body width 2.3 mm

74HCT3G14DC

−40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads;

74HC3G14GD

SOT996-2

8 terminals; UTLP based; body 3 × 2 × 0.5 mm

74HCT3G14GD

Page 2

5. Marking

Table 2. Marking Type number

Marking code

74HC3G14DP

H14

74HCT3G14DP

T14

74HC3G14DC

H14

74HCT3G14DC

T14

74HC3G14GD

H14

74HCT3G14GD

T14

6. Functional diagram

7. Pinning information

7.1 Pinning

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Page 3

7.2 Pin description

Table 3. Pin description Symbol

Pin

Description

1A, 2A, 3A

1, 3, 6

data input

GND

4

ground (0 V)

1Y, 2Y, 3Y

7, 5, 2

data output

8

supply voltage

VCC

8. Functional description

Table 4. Function table[1]

L

H

H

L

[1] H = HIGH voltage level; L = LOW voltage level.

9. Limiting values

Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Max Unit

supply voltage

−0.5 +7.0 V

VCC

[1] -

input clamping current

VI < −0.5 V or VI > VCC + 0.5 V

±20 mA

IIK

[1] -

output clamping current

VO < −0.5 V or VO > VCC + 0.5 V

±20 mA

IOK

[1] -

output current

VO = −0.5 V to VCC + 0.5 V

±25 mA

IO

[1] -

supply current

+50 mA

ICC

[1] −50

ground current

• mA

IGND storage temperature

−65 +150 °C

Tstg

[2] -

total power dissipation

300 mW

Ptot

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8U package: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.

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Page 4

10. Recommended operating conditions

Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V).

supply voltage

2.0 5.0 6.0 4.5 5.0 5.5 V

VCC input voltage

0 - VCC 0 - VCC V

VI output voltage

0 - VCC 0 - VCC V

VO ambient temperature

−40 +25 +125 −40 +25 +125 °C

Tamb

11. Static characteristics

Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C.

74HC3G14 HIGH-level

VI = VT+ or VT−

VOH output voltage

IO = −20 µA; VCC = 2.0 V

1.9 2.0 - 1.9 - 1.9 - V

IO = −20 µA; VCC = 4.5 V

4.4 4.5 - 4.4 - 4.4 - V

IO = −20 µA; VCC = 6.0 V

5.9 6.0 - 5.9 - 5.9 - V

IO = −4.0 mA; VCC = 4.5 V

4.18 4.32 - 4.13 - 3.7 - V

IO = −5.2 mA; VCC = 6.0 V

5.68 5.81 - 5.63 - 5.2 - V

LOW-level

VI = VT+ or VT−

VOL output voltage

IO = 20 µA; VCC = 2.0 V

• 0 0.1 - 0.1 - 0.1 V

IO = 20 µA; VCC = 4.5 V

• 0 0.1 - 0.1 - 0.1 V

IO = 20 µA; VCC = 6.0 V

• 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 4.5 V

• 0.15 0.26
• 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V

• 0.16 0.26
• 0.33 - 0.4 V

input leakage

VI = VCC or GND; VCC = 6.0 V

• - ±0.1 - ±1.0 - ±1.0 µA

II current supply current per input pin; VCC = 6.0 V; ICC

• - 1.0 - 10 - 20 µA

VI = VCC or GND; IO = 0 A;

input

• 2.0 - - - - - pF

CI capacitance

74HCT3G14

HIGH-level

VI = VT+ or VT−

VOH output voltage

IO = −20 µA; VCC = 4.5 V

4.4 4.5 - 4.4 - 4.4 - V

IO = −4.0 mA; VCC = 4.5 V

4.18 4.32 - 4.13 - 3.7 - V

LOW-level

VI = VIH or VIL

VOL output voltage

IO = 20 µA; VCC = 4.5 V

• 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 4.5 V

• 0.15 0.26
• 0.33 - 0.4 V

input leakage

VI = VCC or GND; VCC = 5.5 V

• - ±0.1 - ±1.0 - ±1.0 µA

II current

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Page 5

Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C.

ICC supply current per input pin; VCC = 5.5 V;

• - 1.0 - 10 - 20 µA

VI = VCC or GND; IO = 0 A;

additional

per input;

∆ICC

• - 300 - 375 - 410 µA

supply current VCC = 4.5 V to 5.5 V;

VI = VCC − 2.1 V; IO = 0 A

input

• 2.0 - - - - - pF

CI capacitance

Table 8. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.

74HC3G14 positive-going

see Figure 6, Figure 7

VT+ threshold voltage

VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V

negative-going

see Figure 6, Figure 7

VT− threshold voltage

VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V

hysteresis voltage

(VT+ − VT−); see Figure 6,

VH

Figure 7 and Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V

74HCT3G14

positive-going

see Figure 6, Figure 7

VT+ threshold voltage

VCC = 4.5 V VCC = 5.5 V

negative-going

see Figure 6, Figure 7

VT− threshold voltage

VCC = 4.5 V VCC = 5.5 V

hysteresis voltage

(VT+ − VT−); see Figure 6,

VH

Figure 7 and Figure 8 VCC = 4.5 V VCC = 5.5 V

1.00 1.18 1.50 1.00

1.50 1.50 V

2.30 2.60 3.15 2.30

3.15 3.15 V

3.00 3.46 4.20 3.00

4.20 4.20 V

0.30 0.60 0.90 0.30

0.90 0.90 V

1.13 1.47 2.00 1.13

2.00 2.00 V

1.50 2.06 2.60 1.50

2.60 2.60 V

0.30 0.60 1.00 0.30

1.00 1.00 V

0.60 1.13 1.40 0.60

1.40 1.40 V

0.80 1.40 1.70 0.80

1.70 1.70 V

1.20 1.58 1.90 1.20

1.90 1.90 V

1.40 1.78 2.10 1.40

2.10 2.10 V

0.50 0.87 1.20 0.50

1.20 1.20 V

0.60 1.11 1.40 0.60

1.40 1.40 V

0.40 0.71

• 0.40 - - V

0.40 0.67

• 0.40 - - V

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Page 6

11.1 Waveforms transfer characteristics

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Page 7

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Page 8

12. Dynamic characteristics

Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.

74HC3G14

[1]

propagation delay

nA to nY; see Figure 10

tpd

VCC = 2.0 V

• 53 125
• 155 190 ns

VCC = 4.5 V

• 16 25 - 31 38 ns

VCC = 6.0 V

• 13 21 - 26 32 ns

[2]

transition time

nY; see Figure 10

tt

VCC = 2.0 V

• 20 75 - 95 110 ns

VCC = 4.5 V

• 7 15 - 19 22 ns

VCC = 6.0 V

• 5 13 - 16 19 ns

[3]

power dissipation

VI = GND to VCC

• 10 - - - - pF

CPD capacitance

74HCT3G14

[1]

propagation delay

nA to nY; see Figure 10

tpd

VCC = 4.5 V

• 21 32 - 40 48 ns

[2]

transition time

nY; see Figure 10

tt

VCC = 4.5 V

• 6 15 - 19 22 ns

[3]

power dissipation

VI = GND to VCC − 1.5 V

• 10 - - - - pF

CPD capacitance

[1] tpd is the same as tPLH and tPHL [2] tt is the same as tTLH and tTHL [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs.

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Page 9

13. Waveforms

Table 10. Measurement points

74HC3G14

0.5VCC

0.5VCC

74HCT3G14

1.3 V

1.3 V

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Page 10

Table 11. Test data

74HC3G14

GND to VCC

≤ 6 ns

50 pF

1 kΩ

open

74HCT3G14

GND to 3.0 V

≤ 6 ns

50 pF

1 kΩ

open

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Page 11

14. Application information

The slow input rise and fall times cause additional power dissipation, which can be calculated using the following formula:

Padd = fi × (tr × ∆ICC(AV) + tf × ∆ICC(AV)) × VCC where: Padd = additional power dissipation (µW); fi = input frequency (MHz); tr = input rise time (ns); 10 % to 90 %; tf = input fall time (ns); 90 % to 10 %; ∆ICC(AV) = average additional supply current (µA). ∆ICC(AV) differs with positive or negative input transitions, as shown in Figure 12 and Figure 13.

An example of a relaxation circuit using the 74HC3G14/74HCT3G14 is shown in Figure 14.

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Page 12

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Page 13

15. Package outline

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

D

E

A X

c

HE

v M A

y

Z

5

8

A2 A

(A3)

A1

pin 1 index

θ Lp L

1

4

detail X

w M

e bp

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

02-01-16

SOT505-2

• - -

Fig 15. Package outline SOT505-2 (TSSOP8)

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Page 14

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm

SOT765-1

D

E

A X

c

y

HE

v M A

Z

5

8

Q

A2 A A1

(A3)

pin 1 index

θ Lp L

1

4

detail X

e

w M bp

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

02-06-07

SOT765-1

MO-187

Fig 16. Package outline SOT765-1 (VSSOP8)

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Page 15

XSON8U: plastic extremely thin small outline package; no leads;

SOT996-2

8 terminals; UTLP based; body 3 x 2 x 0.5 mm

B A

D

A

E

A1

detail X

terminal 1 index area

e1

C

C A B v M b e

L1

y

y1 C

w M C

1

4

L2

L

8

5

X

0 1 2 mm scale

DIMENSIONS (mm are the original dimensions)

Fig 17. Package outline SOT996-2 (XSON8U)

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Page 16

16. Abbreviations

Table 12. Abbreviations Acronym

Description

CMOS

Complementary Metal Oxide Semiconductor

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

17. Revision history

Table 13. Revision history Document ID

Release date

Data sheet status

Change notice

Supersedes

20090508

-

74HC_HCT3G14_2

• The format of this data sheet has been redesigned to comply with the new identity

Modifications:

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.
• Added type number 74HC3G14GD and 74HCT3G14GD (XSON8U package)

74HC_HCT3G14_2

20031104

Product specification

-

74HC_HCT3G14_1

74HC_HCT3G14_1

20020723

Product specification

-

-

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18. Legal information

18.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

18.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental

19. Contact information

For more information, please visit: http://www.nxp.com

damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, please send an email to: salesaddresses@nxp.com

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20. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Functional description . . . . . . . . . . . . . . . . . . . 3

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 10 Recommended operating conditions. . . . . . . . 4 11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 11.1 Waveforms transfer characteristics. . . . . . . . . . 6 12 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 Application information. . . . . . . . . . . . . . . . . . 11 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16 17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 19 Contact information. . . . . . . . . . . . . . . . . . . . . 17 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2009.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 May 2009 Document identifier: 74HC_HCT3G14_3