74HCT3G04 PHILIPS

Document overview

  • PDF pages: 17

Technical content

Page 1

INTEGRATED CIRCUITS

PDF page 1 diagram
PDF page 1 diagram
PDF page 1 diagram

Page 2

PDF page 2 diagram

FEATURES

  • Wide supply voltage range from 2.0 to 6.0 V
  • Symmetrical output impedance
  • High noise immunity
  • Low power dissipation
  • Balanced propagation delays
  • Very small 8 pins package
  • Output capability: standard
  • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns.

DESCRIPTION

The 74HC3G/HCT3G04 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). Specified in compliance with JEDEC standard no. 7. The 74HC3G/HCT3G04 provides three inverting buffers.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC3G04 HCT3G04
t /t PHL PLH propagation delay nA to nY C = 50 pF; V = 4.5 V L CC 8 10 ns
C I input capacitance 1.5 1.5 pF
C PD power dissipation capacitance per buffer notes 1 and 2 9 9 pF

Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total switching outputs; ∑ (CL × VCC2 × fo) = sum of outputs. 2. For HC3G04 the condition is VI = GND to VCC. For HCT3G04 the condition is VI = GND to VCC − 1.5 V.

FUNCTION TABLE

See note 1.

Column 1 Column 2
INPUT OUTPUT
nA nY
L H
H L

Note 1. H = HIGH voltage level; L = LOW voltage level.

Page 3

PDF page 3 diagram

ORDERING INFORMATION

TYPE NUMBER PACKAGE
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE MARKING
74HC3G04DP −40 to +125 °C 8 TSSOP8 plastic SOT505-2 H04
74HCT3G04DP −40 to +125 °C 8 TSSOP8 plastic SOT505-2 T04
74HC3G04DC −40 to +125 °C 8 VSSOP8 plastic SOT765-2 H04
74HCT3G04DC −40 to +125 °C 8 VSSOP8 plastic SOT765-2 T04

PINNING

PIN SYMBOL DESCRIPTION
1 1A data input 1A
2 3Y data output 3Y
3 2A data input 2A
4 GND ground (0 V)
5 2Y data output 2Y
6 3A data input 3A
7 1Y data output 1Y
8 V CC supply voltage
PDF page 3 diagram
PDF page 3 diagram

Page 4

PDF page 4 diagram
PDF page 4 diagram
PDF page 4 diagram

Page 5

Inverter

74HC3G04; 74HCT3G04

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS 74HC3G04 74HCT3G04 UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
V CC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
V I input voltage 0 − V CC 0 − V CC V
V O output voltage 0 − V CC 0 − V CC V
T amb operating ambient temperature see DC and AC characteristics per device −40 +25 +125 −40 +25 +125 °C
t, t r f input rise and fall times V = 2.0 V CC − − 1000 − − − ns
V = 4.5 V CC − 6.0 500 − 6.0 500 ns
V = 6.0 V CC − − 400 − − − ns

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V CC supply voltage −0.5 +7.0 V
I IK input diode current V < −0.5 V or V > V + 0.5 V; note 1 I I CC − ±20 mA
I OK output diode current V < −0.5 V or V > V + 0.5 V; note 1 O O CC − ±20 mA
I O output source or sink current −0.5 V < V < V + 0.5 V; note 1 O CC − 25 mA
I CC V or GND current CC note 1 − 50 mA
T stg storage temperature −65 +150 °C
P D power dissipation T = −40 to +125 °C; note 2 amb − 300 mW

Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 110 °C the value of PD derates linearly with 8 mW/K.

Page 6

Inverter

74HC3G04; 74HCT3G04

DC CHARACTERISTICS

Type 74HC3G04 At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER V (V) CC
T = 25 °C amb
V IH HIGH-level input voltage 2.0 1.5 1.2 − V
4.5 3.15 2.4 − V
6.0 4.2 3.2 − V
V IL LOW-level input voltage 2.0 − 0.8 0.5 V
4.5 − 2.1 1.35 V
6.0 − 2.8 1.8 V
V OH HIGH-level output voltage V = V or V I IH IL I = −20 µA O I = −20 µA O I = −20 µA O I = −4.0 mA O I = −5.2 mA O 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.32 5.81 − − − − − V V V V V
V OL LOW-level output voltage V = V or V I IH IL I = 20 µA O I = 20 µA O I = 20 µA O I = 4.0 mA O I = 5.2 mA O 2.0 4.5 6.0 4.5 6.0 − − − − − 0 0 0 0.15 0.16 0.1 0.1 0.1 0.26 0.26 V V V V V
I LI input leakage current V = V or GND I CC 6.0 − − ±0.1 µA
I CC quiescent supply current V = V or GND; I CC I = 0 O 6.0 − − 1.0 µA

Page 7

Inverter

74HC3G04; 74HCT3G04

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER V (V) CC
T = −40 to +85 °C amb
V IH HIGH-level input voltage 2.0 1.5 − − V
4.5 3.15 − − V
6.0 4.2 − − V
V IL LOW-level input voltage 2.0 − − 0.5 V
4.5 − − 1.35 V
6.0 − − 1.8 V
V OH HIGH-level output voltage V = V or V I IH IL I = −20 µA O I = −20 µA O I = −20 µA O I = −4.0 mA O I = −5.2 mA O 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 4.13 5.63 − − − − − − − − − − V V V V V
V OL LOW-level output voltage V = V or V I IH IL I = 20 µA O I = 20 µA O I = 20 µA O I = 4.0 mA O I = 5.2 mA O 2.0 4.5 6.0 4.5 6.0 − − − − − − − − − − 0.1 0.1 0.1 0.33 0.33 V V V V V
I LI input leakage current V = V or GND I CC 6.0 − − ±1.0 µA
I CC quiescent supply current V = V or GND; I CC I = 0 O 6.0 − − 10 µA

Page 8

PDF page 8 diagram
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER V (V) CC
T = −40 to +125 °C amb
V IH HIGH-level input voltage 2.0 1.5 − − V
4.5 3.15 − − V
6.0 4.2 − − V
V IL LOW-level input voltage 2.0 − − 0.5 V
4.5 − − 1.35 V
6.0 − − 1.8 V
V OH HIGH-level output voltage V = V or V I IH IL I = −20 µA O I = −20 µA O I = −20 µA O I = −4.0 mA O I = −5.2 mA O 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 3.7 5.2 − − − − − − − − − − V V V V V
V OL LOW-level output voltage V = V or V I IH IL I = 20 µA O I = 20 µA O I = 20 µA O I = 4.0 mA O I = 5.2 mA O 2.0 4.5 6.0 4.5 6.0 − − − − − − − − − − 0.1 0.1 0.1 0.4 0.4 V V V V V
I LI input leakage current V = V or GND I CC 6.0 − − ±1.0 µA
I CC quiescent supply current V = V or GND; I CC I = 0 O 6.0 − − 20 µA

Page 9

PDF page 9 diagram

Type 74HCT3G04 At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER V (V) CC
T = 25 °C amb
V IH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 − V
V IL LOW-level input voltage 4.5 to 5.5 − 1.2 0.8 V
V OH HIGH-level output voltage V = V or V I IH IL I = −20 µA O I = −4.0 mA O 4.5 4.5 4.4 4.18 4.5 4.32 − − V V
V OL LOW-level output voltage V = V or V I IH IL I = 20 µA O I = 4.0 mA O 4.5 4.5 − − 0 0.15 0.1 0.26 V V
I LI input leakage current V = V or GND I CC 5.5 − − ±0.1 µA
I CC quiescent supply current V = V or GND; I CC I = 0 O 5.5 − − 1.0 µA
∆I CC additional supply current per input V = V −2.1 V; I CC I = 0 O 4.5 to 5.5 − − 300 µA
T = −40 to +85 °C amb
V IH HIGH-level input voltage 4.5 to 5.5 2.0 − − V
V IL LOW-level input voltage 4.5 to 5.5 − − 0.8 V
V OH HIGH-level output voltage V = V or V I IH IL I = −20 µA O I = −4.0 mA O 4.5 4.5 4.4 4.13 − − − − V V
V OL LOW-level output voltage V = V or V I IH IL I = 20 µA O I = 4.0 mA O 4.5 4.5 − − − − 0.1 0.33 V V
I LI input leakage current V = V or GND I CC 5.5 − − ±1.0 µA
I CC quiescent supply current V = V or GND; I CC I = 0 O 5.5 − − 10 µA
∆I CC additional supply current per input V = V −2.1 V; I CC I = 0 O 4.5 to 5.5 − − 375 µA

Page 10

PDF page 10 diagram
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER V (V) CC
T = −40 to +125 °C amb
V IH HIGH-level input voltage 4.5 to 5.5 2.0 − − V
V IL LOW-level input voltage 4.5 to 5.5 − − 0.8 V
V OH HIGH-level output voltage V = V or V I IH IL I = −20 µA O I = −4.0 mA O 4.5 4.5 4.4 3.7 − − − − V V
V OL LOW-level output voltage V = V or V I IH IL I = 20 µA O I = 4.0 mA O 4.5 4.5 − − − − 0.1 0.4 V V
I LI input leakage current V = V or GND I CC 5.5 − − ±1.0 µA
I CC quiescent supply current V = V or GND; I CC I = 0 O 5.5 − − 20 µA
∆I CC additional supply current per input V = V −2.1 V; I CC I = 0 O 4.5 to 5.5 − − 410 µA

Page 11

PDF page 11 diagram

AC CHARACTERISTICS

Type 74HC3G04 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF.

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS V (V) CC
T = 25 °C amb
t /t PHL PLH propagation delay nA to nY see Figs 5 and 6 2.0 − 22 75 ns
4.5 − 8 15 ns
6.0 − 6 13 ns
t /t THL TLH output transition time see Figs 5 and 6 2.0 − 18 75 ns
4.5 − 6 15 ns
6.0 − 5 13 ns
T = −40 to +85 °C amb
t /t PHL PLH propagation delay nA to nY see Figs 5 and 6 2.0 − − 90 ns
4.5 − − 18 ns
6.0 − − 16 ns
t /t THL TLH output transition time see Figs 5 and 6 2.0 − − 95 ns
4.5 − − 19 ns
6.0 − − 16 ns
T = −40 to +125 °C amb
t /t PHL PLH propagation delay nA to nY see Figs 5 and 6 2.0 − − 110 ns
4.5 − − 22 ns
6.0 − − 20 ns
t /t THL TLH output transition time see Figs 5 and 6 2.0 − − 125 ns
4.5 − − 25 ns
6.0 − − 20 ns

Page 12

PDF page 12 diagram

Type 74HCT3G04 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF.

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS V (V) CC
T = 25 °C amb
t /t PHL PLH propagation delay nA to nY see Figs 5 and 6 4.5 − 10 18 ns
t /t THL TLH output transition time see Figs 5 and 6 4.5 − 6 15 ns
T = −40 to +85 °C amb
t /t PHL PLH propagation delay nA to nY see Figs 5 and 6 4.5 − − 23 ns
t /t THL TLH output transition time see Figs 5 and 6 4.5 − − 19 ns
T = −40 to +125 °C amb
t /t PHL PLH propagation delay nA to nY see Figs 5 and 6 4.5 − − 29 ns
t /t THL TLH output transition time see Figs 5 and 6 4.5 − − 22 ns

AC WAVEFORMS

PDF page 12 diagram

Page 13

Inverter

74HC3G04; 74HCT3G04

S1 VCC

handbook, full pagewidth

open

VCC

GND RL = 1 kΩ

VI

VO

PULSE

D.U.T.

GENERATOR

CL =

RT

50 pF

MNA742

Column 1 Column 2
TEST S 1
t /t PLH PHL open
t /t PLZ PZL V CC
t /t PHZ PZH GND

Definitions for test circuit: CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig.6 Load circuitry for switching times.

Page 14

PDF page 14 diagram

PACKAGE OUTLINES

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

D

E

A X

c

HE

v M A

y

Z

5

8

A2 A

(A3)

A1

pin 1 index

θ Lp L

1

4

detail X

w M

e bp

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ
mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0°

Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

02-01-16

SOT505-2

  • - -

Page 15

Inverter

74HC3G04; 74HCT3G04

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm

SOT765-1

D

E

A X

c

y

HE

v M A

Z

5

8

Q

A2 A A1

(A3)

pin 1 index

θ Lp L

1

4

detail X

e

w M bp

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ
mm 1 0.15 0 0.00 0 .85 .60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0°

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

02-06-07

SOT765-1

MO-187

Page 16

PDF page 16 diagram

DATA SHEET STATUS

Column 1 Column 2 Column 3 Column 4
LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product.
III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

DEFINITIONS

Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

DISCLAIMERS

Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Page 17

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA75

© Koninklijke Philips Electronics N.V. 2003

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

613508/02/pp17

Date of release: 2003 Oct 30

Document order number: 9397 750 10568

PDF page 17 diagram