74HC393 PHILIPS
Document overview
- PDF pages: 7
Technical content
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FEATURES
- Two 4-bit binary counters with individual clocks
- Divide-by any binary module up to 28 in one package
- Two master resets to clear each 4-bit counter individually
- Output capability: standard
- ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (1MR and 2MR) inputs to each counter. The operation of each half of the “393” is the same as the “93” except no external clock connections are required. The counters are triggered by a HIGH-to-LOW transition of the clock inputs. The counter outputs are internally connected to provide clock inputs to succeeding stages. The outputs of the ripple counter do not change synchronously and should not be used for high-speed address decoding. The master resets are active-HIGH asynchronous inputs to each 4-bit counter identified by the “1” and “2” in the pin description.
A HIGH level on the nMR input overrides the clock and sets the outputs LOW.
| SYMBOL | PARAMETER | CONDITIONS | TYPICAL | UNIT | |
|---|---|---|---|---|---|
| HC | HCT | ||||
| t / t PHL PLH | propagation delay nCP to nQ 0 nQ to nQ n+1 nMR to nQ n | C = 15 pF; V = 5 V L CC | 12 5 11 | 20 6 15 | ns ns ns |
| f max | maximum clock frequency | 99 | 53 | MHz | |
| C I | input capacitance | 3.5 | 3.5 | pF | |
| C PD | power dissipation capacitance per counter | notes 1 and 2 | 23 | 25 | pF |
Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
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PIN DESCRIPTION
| PIN NO. | SYMBOL | NAME AND FUNCTION |
|---|---|---|
| 1, 13 2, 12 3, 4, 5, 6, 11, 10, 9, 8 7 14 | 1CP, 2CP 1MR, 2MR 1Q to 1Q 3, 2Q to 2Q 0 0 3 GND V CC | clock inputs (HIGH-to-LOW, edge-triggered) asynchronous master reset inputs (active HIGH) flip-flop outputs ground (0 V) positive supply voltage |
Fig.2 Logic symbol.
Fig.1 Pin configuration.
Fig.3 IEC logic symbol.
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Fig.4 Functional diagram.
Fig.6 Logic diagram (one counter).
Fig.5 State diagram.
COUNT SEQUENCE FOR 1 COUNTER
| Column 1 | Column 2 | Column 3 | Column 4 | Column 5 |
|---|---|---|---|---|
| COUNT | OUTPUTS | |||
| Q 0 | Q 1 | Q 2 | Q 3 | |
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 | L H L H L H L H L H L H L H L H | L L H H L L H H L L H H L L H H | L L L L H H H H L L L L H H H H | L L L L L L L L H H H H H H H H |
Notes 1. H = HIGH voltage level L = LOW voltage level
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DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
| SYMBOL | PARAMETER | T (°C) amb | UNIT | TEST CONDITIONS | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HC | V CC (V) | WAVEFORMS | |||||||||
| +25 | −40 to +85 | −40 to +125 | |||||||||
| min. | typ. | max. | min. | max. | min. | max. | |||||
| t / t PHL PLH | propagation delay nCP to nQ 0 | 41 15 12 | 125 25 21 | 155 31 26 | 190 38 32 | ns | 2.0 4.5 6.0 | Fig.7 | |||
| t / t PHL PLH | propagation delay nQ to nQ n n+1 | 14 5 4 | 45 9 8 | 55 11 9 | 70 14 12 | ns | 2.0 4.5 6.0 | Fig.7 | |||
| t PHL | propagation delay nMR to nQ n | 39 14 11 | 140 28 24 | 175 35 30 | 210 42 36 | ns | 2.0 4.5 6.0 | Fig.8 | |||
| t / t THL TLH | output transition time | 19 7 6 | 75 15 13 | 95 19 16 | 110 22 19 | ns | 2.0 4.5 6.0 | Fig.7 | |||
| t W | clock pulse width HIGH or LOW | 80 16 14 | 17 6 5 | 100 20 17 | 120 24 20 | ns | 2.0 4.5 6.0 | Fig.7 | |||
| t W | master reset pulse width; HIGH | 80 16 14 | 19 7 6 | 100 20 17 | 120 24 20 | ns | 2.0 4.5 6.0 | Fig.8 | |||
| t rem | removal time nMR to nCP | 5 5 5 | 3 1 1 | 5 5 5 | 5 5 5 | ns | 2.0 4.5 6.0 | Fig.8 | |||
| f max | maximum clock pulse frequency | 6 30 35 | 30 90 107 | 5 24 28 | 4 20 24 | MHz | 2.0 4.5 6.0 | Fig.7 |
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DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI
Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
| INPUT | UNIT LOAD COEFFICIENT |
|---|---|
| 1CP 2CP 1MR 2MR | 0.4 0.4 1.0 1.0 |
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
| SYMBOL | PARAMETER | T (°C) amb | UNIT | TEST CONDITIONS | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HCT | V CC (V) | WAVEFORMS | |||||||||
| +25 | −40 to +85 | −40 to +125 | |||||||||
| min. | typ. | max. | min. | max. | min. | max. | |||||
| t / t PHL PLH | propagation delay nCP to nQ 0 | 15 | 25 | 31 | 38 | ns | 4.5 | Fig.7 | |||
| t / t PHL PLH | propagation delay nQ to nQ n n+1 | 6 | 10 | 13 | 15 | ns | 4.5 | Fig.7 | |||
| t PHL | propagation delay nMR to nQ n | 18 | 32 | 40 | 48 | ns | 4.5 | Fig.8 | |||
| t / t THL TLH | output transition time | 7 | 15 | 19 | 22 | ns | 4.5 | Fig.7 | |||
| t W | clock pulse width HIGH or LOW | 19 | 11 | 24 | 29 | ns | 4.5 | Fig.7 | |||
| t W | master reset pulse width; HIGH | 16 | 6 | 20 | 24 | ns | 4.5 | Fig.8 | |||
| t rem | removal time nMR to nCP | 5 | 0 | 5 | 5 | ns | 4.5 | Fig.8 | |||
| f max | maximum clock pulse frequency | 27 | 48 | 22 | 18 | MHz | 4.5 | Fig.7 |
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