74HCT393DB

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Document overview

• PDF pages: 21

Technical content

Page 1

1. General description

The 74HC393; 7474HCT393 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A HIGH on nMR clears the counter stages and forces the outputs LOW, independent of the state of nCP. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

 Input levels:  For 74HC393: CMOS level  For 74HCT393: TTL level  Complies with JEDEC standard no. 7A  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V.  Two 4-bit binary counters with individual clocks  Divide by any binary module up to 28 in one package  Two master resets to clear each 4-bit counter individually

3. Ordering information

Table 1. Ordering information

plastic dual in-line package; 14 leads (300 mil)

74HC393N

40 C to +125 C DIP14

SOT27-1

74HCT393N

plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

74HC393D

40 C to +125 C SO14

74HCT393D

plastic shrink small outline package; 14 leads; body width

74HC393DB 40 C to +125 C SSOP14

SOT337-1

5.3 mm

74HCT393DB 74HC393PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body

SOT402-1

width 4.4 mm

74HCT393PW 74HC393BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin

SOT762-1

quad flat package; no leads; 14 terminals;

74HCT393BQ

body 2.5  3  0.85 mm

Page 2

4. Functional diagram

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Page 3

5. Pinning information

5.1 Pinning

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Page 4

5.2 Pin description

Table 2. Pin description Symbol

Pin

Description

clock input (HIGH-to-LOW, edge-triggered)

1

1CP

asynchronous master reset input (active HIGH)

1MR

2

1Q0

3

flip-flop output

1Q1

4

flip-flop output

1Q2

5

flip-flop output

1Q3

6

flip-flop output

GND

7

ground (0 V)

2Q3

8

flip-flop output

2Q2

9

flip-flop output

2Q1

10

flip-flop output

2Q0

11

flip-flop output asynchronous master reset input (active HIGH)

2MR

12

clock input (HIGH-to-LOW, edge-triggered)

13

2CP

14

supply voltage

VCC

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Page 5

6. Functional description

Table 3. Count sequence for one counter [1]

0

L

L

L

L

1

H

L

L

L

2

L

H

L

L

3

H

H

L

L

4

L

L

H

L

5

H

L

H

L

6

L

H

H

L

7

H

H

H

L

8

L

L

L

H

9

H

L

L

H

10

L

H

L

H

11

H

H

L

H

12

L

L

H

H

13

H

L

H

H

14

L

H

H

H

15

H

H

H

H

[1] H = HIGH voltage level; L = LOW voltage level.

7. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Max Unit

supply voltage

0.5 +7 V

VCC

input clamping current

VI < 0.5 V or VI > VCC + 0.5 V

• 20 mA

IIK

output clamping current

VO < 0.5 V or VO > VCC + 0.5 V

• 20 mA

IOK

output current

VO = 0.5 V to VCC + 0.5 V

• 25 mA

IO

supply current

• ±50 mA

ICC

ground current

• 50 mA

IGND

storage temperature

65 +150 C

Tstg

[1] -

total power dissipation

DIP14 package

750 mW

Ptot

[2] -

500 mW

SO14, SSOP14, TSSOP14 and DHVQFN14 package

[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.

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Page 6

8. Recommended operating conditions

Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V)

supply voltage

2.0 5.0 6.0 4.5 5.0 5.5 V

VCC input voltage

0 - VCC 0 - VCC V

VI output voltage

0 - VCC 0 - VCC V

VO ambient temperature

40 +25 +125 40

+25 +125 C

Tamb

VCC = 2.0 V

• - 625 - - - ns/V

t/V input transition rise and fall rate

VCC = 4.5 V

• 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V

• - 83 - - - ns/V

9. Static characteristics

Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

74HC393 HIGH-level

VCC = 2.0 V

1.5 1.2 - 1.5 - 1.5 - V

VIH input voltage

VCC = 4.5 V

3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V

4.2 3.2 - 4.2 - 4.2 - V

LOW-level

VCC = 2.0 V

• 0.8 0.5
• 0.5 - 0.5 V

VIL input voltage

VCC = 4.5 V

• 2.1 1.35
• 1.35 - 1.35 V

VCC = 6.0 V

• 2.8 1.8
• 1.8 - 1.8 V

HIGH-level

VI = VIH or VIL

VOH output voltage

IO = 20 A; VCC = 2.0 V

1.9 2.0 - 1.9 - 1.9 - V

IO = 20 A; VCC = 4.5 V

4.4 4.5 - 4.4 - 4.4 - V

IO = 20 A; VCC = 6.0 V

5.9 6.0 - 5.9 - 5.9 - V

IO = 4.0 mA; VCC = 4.5 V

3.98 4.32 - 3.84 - 3.7 - V

IO = 5.2 mA; VCC = 6.0 V

5.48 5.81 - 5.34 - 5.2 - V

LOW-level

VI = VIH or VIL

VOL output voltage

IO = 20 A; VCC = 2.0 V

• 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 4.5 V

• 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 6.0 V

• 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 4.5 V

• 0.15 0.26
• 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V

• 0.16 0.26
• 0.33 - 0.4 V
• - 0.1 - 0.1 - 0.1 A

input leakage

VI = VCC or GND;

II

VCC = 6.0 V

current

• - 8.0 - 80 - 160 A

supply current

VI = VCC or GND; IO = 0 A;

ICC

VCC = 6.0 V

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Page 7

Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

CI input

• 3.5 -

pF

capacitance 74HCT393 HIGH-level

VCC = 4.5 V to 5.5 V

2.0 1.6 - 2.0 - 2.0 - V

VIH input voltage LOW-level

VCC = 4.5 V to 5.5 V

• 1.2 0.8
• 0.8 - 0.8 V

VIL input voltage VOH HIGH-level

VI = VIH or VIL; VCC = 4.5 V

output voltage

IO = 20 A

4.4 4.5 - 4.4 - 4.4 - V

IO = 6 mA

3.98 4.32 - 3.84 - 3.7 - V

LOW-level

VI = VIH or VIL; VCC = 4.5 V

VOL output voltage

IO = 20 A

• 0 0.1 - 0.1 - 0.1 V

IO = 6.0 mA

• 0.15 0.26
• 0.33 - 0.4 V

input leakage

VI = VCC or GND;

• - 0.1 - 1.0 - 1.0 A

II current

VCC = 5.5 V

• - 8.0 - 80 - 160 A

supply current

VI = VCC or GND; IO = 0 A;

ICC

VCC = 5.5 V

additional

VI = VCC  2.1 V;

ICC supply current other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V; IO = 0 A

• 40 144
• 180 - 196 A

per input pin; nCP per input pin; nMR

• 100 360
• 450 - 490 A

input

• 3.5 -

pF

CI capacitance

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Page 8

10. Dynamic characteristics

Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.

74HC393

[1]

propagation nCP to nQ0; see Figure 9 tpd delay

VCC = 2.0 V

• 41 125 -

155 - 190 ns

VCC = 4.5 V

• 15 25 -

31 - 38 ns

VCC = 5 V; CL = 15 pF

• 12 - - - - - ns

VCC = 6.0 V

• 12 21 -

26 - 32 ns

[1]

nQx to nQ(x1); see Figure 9 VCC = 2.0 V

• 14 45 -

55 - 70 ns

VCC = 4.5 V

• 5 9 - 11 - 14 ns

VCC = 5 V; CL = 15 pF

• 5 - - - - - ns

VCC = 6.0 V

• 4 8 - 9 - 12 ns

HIGH to

nMR to nQx; see Figure 10

tPHL LOW

VCC = 2.0 V

• 39 140 -

175 - 210 ns

propagation

VCC = 4.5 V

• 14 28 -

35 - 42 ns

delay

VCC = 5 V; CL = 15 pF

• 11 - - - - - ns

VCC = 6.0 V

• 11 24 -

30 - 36 ns

[2]

transition

Qn; see Figure 9

tt time

VCC = 2.0 V

• 19 75 -

95 - 110 ns

VCC = 4.5 V

• 7 15 -

19 - 22 ns

VCC = 6.0 V

• 6 13 -

16 - 19 ns

pulse width nCP HIGH or LOW; tW

see Figure 9 VCC = 2.0 V

80 17 - 100 - 120 - ns

VCC = 4.5 V

16 6 - 20 - 24 - ns

VCC = 6.0 V

14 5 - 17 - 20 - ns

nMR HIGH; see Figure 10 VCC = 2.0 V

80 19 - 100 - 120 - ns

VCC = 4.5 V

16 7 - 20 - 24 - ns

VCC = 6.0 V

14 6 - 17 - 20 - ns

recovery

nMR to nCP; see Figure 10

trec time

VCC = 2.0 V

5 3 - 5 - 5 - ns

VCC = 4.5 V

5 1 - 5 - 5 - ns

VCC = 6.0 V

5 1 - 5 - 5 - ns

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Page 9

Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.

maximum see Figure 9 fclk(max) clock

VCC = 2.0 V

6 30 - 5

• 4 - MHz

frequency

VCC = 4.5 V

30 90 - 24

• 20 - MHz

VCC = 5 V; CL = 15 pF

• 99 - - - - - MHz

VCC = 6.0 V

35 107 -

28

24 - MHz

[3]

CL = 50 pF; f = 1 MHz;

power

• 23 - - - - - pF

CPD dissipation VI = GND to VCC capacitance 74HCT393

[1]

propagation nCP to nQ0; see Figure 9 tpd delay

VCC = 4.5 V

• 15 25 -

31 - 38 ns

VCC = 5 V; CL = 15 pF

• 20 - - - - - ns

[1]

nQx to nQ(x1); see Figure 9 VCC = 4.5 V

• 6 10 -

13 - 15 ns

VCC = 5 V; CL = 15 pF

• 6 - - - - - ns

HIGH to

nMR to nQx; see Figure 10

tPHL LOW

VCC = 4.5 V

• 18 32 -

40 - 48 ns

propagation

VCC = 5 V; CL = 15 pF

• 15 - - - - - ns

delay

[2]

tt transition

Qn; see Figure 9

time

VCC = 4.5 V

• 7 15 -

19 - 22 ns

pulse width nCP HIGH or LOW; tW

see Figure 9 VCC = 4.5 V

19 11 - 24 - 29 - ns

nMR HIGH; see Figure 10 VCC = 4.5 V

16 6 - 20 - 24 - ns

recovery

nMR to nCP;

trec time

see Figure 10 VCC = 4.5 V

5 0 - 5 - 5 - ns

maximum see Figure 9 fclk(max) clock

VCC = 4.5 V

27 48 - 22 - 18 - MHz

frequency

VCC = 5 V; CL = 15 pF

• 53 - - - - - MHz

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Page 10

Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.

[3]

CL = 50 pF; f = 1 MHz;

CPD power

• 25 - - - - - pF

dissipation VI = GND to VCC capacitance

[1] tpd is the same as tPLH and tPHL. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs.

10.1 Waveforms

Table 8. Measurement points

74HC393

0.5VCC

0.5VCC

74HCT393

1.3 V

1.3 V

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Table 9. Test data

74HC393

VCC

6 ns

15 pF, 50 pF

74HCT393

3 V

6 ns

15 pF, 50 pF

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11. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

D

E

A X

c

y

HE

v M A

Z

8

14

Q

A2

A (A ) 3

A1

pin 1 index

θ Lp L

7

1

e

detail X

w M bp

0 2.5 5 mm scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

Fig 12. Package outline SOT108-1 (SO14)

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Page 14

DIP14: plastic dual in-line package; 14 leads (300 mil)

SOT27-1

ME

D

A2 A

A1

L

c

e

w M

Z

b1

(e ) 1

b

MH

8

14

pin 1 index

E

1

7

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

Fig 13. Package outline SOT27-1 (DIP14)

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Page 15

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm

SOT337-1

D

E

A X

c

y

HE

v M A

Z

8

14

Q

A2

A (A )

A1

3

pin 1 index

θ Lp L

7

1

detail X

w M bp

e

0 2.5 5 mm scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

MO-150

SOT337-1

03-02-19

Fig 14. Package outline SOT337-1 (SSOP14)

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TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

E

A

D

X

c

y

HE

v M A

Z

8

14

Q (A )

A2

3 A

A1

pin 1 index

θ Lp L

1

7

detail X

w M bp

e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT402-1

MO-153

03-02-18

Fig 15. Package outline SOT402-1 (TSSOP14)

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Page 17

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT762-1

14 terminals; body 2.5 x 3 x 0.85 mm

B A

D

A A1

E

c

detail X

terminal 1 index area

C

terminal 1

e1

index area

y

y1 C

e

v M C A B

b

w M C

2

6

L

1

7

Eh

e

14

8

13

9 Dh

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Fig 16. Package outline SOT762-1 (DHVQFN14)

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12. Abbreviations

Table 10. Abbreviations table Acronym

Description

CMOS

Complementary Metal Oxide Semiconductor

TTL

Transistor-Transistor Logic

LSTTL

Low-power Schottky Transistor-Transistor Logic

DUT

Device Under Test

13. Revision history

Table 11. Revision history

Change notice

Document ID

Release date

Data sheet status

Supersedes

74HC_HCT393 v.4

20130516

-

74HC_HCT393 v.3

• The format of this data sheet has been redesigned to comply with the new identity

Modifications:

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

74HC_HCT393 v.3

20050906

-

74HC_HCT393_CNV v.2

74HC_HCT393_CNV v.2

19901201

Product specification -

-

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14. Legal information

14.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

14.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

14.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

15. Contact information

For more information, please visit: http://www.nxp.com

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, please send an email to: salesaddresses@nxp.com

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16. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Recommended operating conditions. . . . . . . . 6 9

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 10.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 12 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18 13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15 Contact information. . . . . . . . . . . . . . . . . . . . . 20 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2013.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 May 2013 Document identifier: 74HC_HCT393