74HCT374DB Datasheet PDF & Specifications

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74HC374 PHILIPS

Document overview

PDF pages: 8

Technical content

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Octal D-type ﬂip-ﬂop; positive

edge-trigger; 3-state

FEATURES

3-state non-inverting outputs for bus oriented applications
8-bit positive, edge-triggered register
Common 3-state output enable input
Independent register and 3-state buffer operation
Output capability: bus driver
ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The 74HC/HCT374 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops.

The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The “374” is functionally identical to the “534”, but has non-inverting outputs.

SYMBOL	PARAMETER	CONDITIONS	TYPICAL		UNIT
			HC	HCT
t / t PHL PLH	propagation delay CP to Q n	C = 15 pF; V = 5 V L CC	15	13	ns
f max	maximum clock frequency		77	48	MHz
C I	input capacitance		3.5	3.5	pF
C PD	power dissipation capacitance per flip-flop	notes 1 and 2	17	17	pF

Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

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PIN DESCRIPTION

PIN NO.	SYMBOL	NAME AND FUNCTION
1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20	OE Q to Q 0 7 D to D 0 7 GND CP V CC	3-state output enable input (active LOW) 3-state flip-flop outputs data inputs ground (0 V) clock input (LOW-to-HIGH, edge-triggered) positive supply voltage

Fig.2 Logic symbol.

Fig.1 Pin configuration.

Fig.3 IEC logic symbol.

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FUNCTION TABLE

Column 1	Column 2	Column 3	Column 4	Column 5	Column 6
OPERATING MODES	INPUTS			INTERNAL FLIP-FLOPS	OUTPUTS
	OE	CP	D n		Q to Q 0 7
load and read register	L L	↑ ↑	l h	L H	L H
load register and disable outputs	H H	↑ ↑	l h	L H	Z Z

Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = high impedance OFF-state ↑ = LOW-to-HIGH CP transition

Fig.4 Functional diagram.

Fig.5 Logic diagram.

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DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

SYMBOL	PARAMETER	T (°C) amb							UNIT	TEST CONDITIONS
		74HC								V CC (V)	WAVEFORMS
		+25			−40 to +85		−40 to +125
		min.	typ.	max.	min.	max.	min.	max.
t / t PHL PLH	propagation delay CP to Q n		50 18 14	165 33 28		205 41 35		250 50 43	ns	2.0 4.5 6.0	Fig.6
t / t PZH PZL	3-state output enable time OE to Q n		41 15 12	150 30 26		190 38 33		225 45 38	ns	2.0 4.5 6.0	Fig.7
t / t PHZ PLZ	3-state output disable time OE to Q n		50 18 14	150 30 26		190 38 33		225 45 38	ns	2.0 4.5 6.0	Fig.7
t / t THL TLH	output transition time		14 5 4	60 12 10		75 15 13		90 18 15	ns	2.0 4.5 6.0	Fig.6
t W	clock pulse width HIGH or LOW	80 16 14	19 7 6		100 20 17		120 24 20		ns	2.0 4.5 6.0	Fig.6
t su	set-up time D to CP n	60 12 10	14 5 4		75 15 13		90 18 15		ns	2.0 4.5 6.0	Fig.8
t h	hold time D to CP n	5 5 5	−6 −2 −2		5 5 5		5 5 5		ns	2.0 4.5 6.0	Fig.8
f max	maximum clock pulse frequency	6.0 30 35	23 70 83		4.8 24 28		4.0 20 24		MHz	2.0 4.5 6.0	Fig.6

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DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI

Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT	UNIT LOAD COEFFICIENT
OE CP D n	1.25 0.90 0.35

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

SYMBOL	PARAMETER	T (°C) amb							UNIT	TEST CONDITIONS
		74HCT								V CC (V)	WAVEFORMS
		+25			−40 to +85		−40 to +125
		min.	typ.	max.	min.	max.	min.	max.
t / t PHL PLH	propagation delay CP to Q n		16	32		40		48	ns	4.5	Fig.6
t / t PZH PZL	3-state output enable time OE to Q n		16	30		38		45	ns	4.5	Fig.7
t / t PHZ PLZ	3-state output disable time OE to Q n		18	28		35		42	ns	4.5	Fig.7
t / t THL TLH	output transition time		5	12		15		18	ns	4.5	Fig.6
t W	clock pulse width HIGH or LOW	19	11		24		29		ns	4.5	Fig.6
t su	set-up time D to CP n	12	7		15		18		ns	4.5	Fig.8
t h	hold time D to CP n	5	−3		5		5		ns	4.5	Fig.8
f max	maximum clock pulse frequency	26	44		21		17		MHz	4.5	Fig.6

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Overview

74HCT374DB is listed in the IC category. Available datasheets include documents from NXP Semiconductors. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

Octal D-type flip-flop; positive edge-trigger; 3-state December 1990

Description