74HCT373DB

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Document overview

• PDF pages: 26

Technical content

Page 1

1. General description

The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.

The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches.

The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes.

When LE is LOW the latches store the information that was present at the D inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the highimpedance OFF-state. Operation of the OE input does not affect the state of the latches.

The 74HC373; 74HCT373 is functionally identical to:

• 74HC563; 74HCT563: but inverted outputs and different pin arrangement
• 74HC573; 74HCT573: but different pin arrangement

2. Features and benefits

 3-state non-inverting outputs for bus oriented applications  Common 3-state output enable input  Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573  ESD protection:  HBM JESD22-A114F exceeds 2 000 V  MM JESD22-A115-A exceeds 200 V  Specified from 40 C to +85 C and from 40 C to +125 C

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3. Ordering information

Table 1. Ordering information

plastic dual in-line package; 20 leads (300 mil)

74HC373N

40 C to +125 C DIP20

SOT146-1

74HCT373N

plastic small outline package; 20 leads;

74HC373D

40 C to +125 C SO20

SOT163-1

body width 7.5 mm

74HCT373D

plastic shrink small outline package; 20 leads;

74HC373DB 40 C to +125 C SSOP20

SOT339-1

body width 5.3 mm

74HCT373DB

plastic thin shrink small outline package; 20 leads;

74HC373PW 40 C to +125 C TSSOP20

SOT360-1

body width 4.4 mm

74HCT373PW 74HC373BQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very

SOT764-1

thin quad flat package; no leads; 20 terminals;

74HCT373BQ

body 2.5  4.5  0.85 mm

4. Functional diagram

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Page 4

5. Pinning information

5.1 Pinning

5.2 Pin description

Table 2. Pin description Symbol

Pin 1

OE Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

2, 5, 6, 9, 12, 15, 16, 19

D0, D1, D2, D3, D4, D5, D6, D7

3, 4, 7, 8, 13, 14, 17, 18

GND

10

LE

11 20

VCC

Description

3-state output enable input (active LOW) 3-state latch output data input ground (0 V) latch enable input (active HIGH) supply voltage

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Page 5

6. Functional description

6.1 Function table

Table 3. Function table[1]

Enable and read register

L

H

L

L

L

(transparent mode)

H

H

H

Latch and read register

L

L

l

L

L

h

H

H

Latch register and disable H

X

X

X

Z

outputs

[1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X = don’t care; Z = high-impedance OFF-state.

7. Limiting values

Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol

Parameter

Conditions

Min Max Unit

supply voltage

0.5 +7 V

VCC

input clamping current

VI < 0.5 V or VI > VCC + 0.5 V

• 20 mA

IIK

output clamping current

VO < 0.5 V or VO > VCC + 0.5 V

• 20 mA

IOK

output current

VO = 0.5 V to (VCC + 0.5 V)

• 35 mA

IO

supply current

• +70 mA

ICC

ground current

• 70 mA

IGND

storage temperature

65 +150 C

Tstg

total power dissipation

Ptot

[1] -

750 mW

DIP20 package

[2] -

500 mW

SO20 package

[3]

500 mW

SSOP20 package

[3]

500 mW

TSSOP20 package

[4] -

500 mW

DHVQFN20 package

[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO20: Ptot derates linearly with 8 mW/K above 70 C. [3] For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C. [4] For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C.

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8. Recommended operating conditions

Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V)

supply voltage

2.0 5.0 6.0 4.5 5.0 5.5 V

VCC input voltage

0 - VCC 0 - VCC V

VI output voltage

0 - VCC 0 - VCC V

VO ambient temperature

40 +25 +125 40

+25 +125 C

Tamb

VCC = 2.0 V

• - 625 - - - ns/V

t/V input transition rise and fall rate

VCC = 4.5 V

• 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V

• - 83 - - - ns/V

9. Static characteristics

Table 6. Static characteristics 74HC373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 25 C HIGH-level input voltage

VCC = 2.0 V

1.5 1.2 - V

VIH

VCC = 4.5 V

3.15 2.4

• V

VCC = 6.0 V

4.2 3.2 - V

LOW-level input voltage

VCC = 2.0 V

• 0.8 0.5 V

VIL

VCC = 4.5 V

• 2.1 1.35 V

VCC = 6.0 V

• 2.8 1.8 V

HIGH-level output voltage

VI = VIH or VIL

• - -

VOH

IO = 20 A; VCC = 2.0 V

1.9 2.0 - V

IO = 20 A; VCC = 4.5 V

4.4 4.5 - V

IO = 20 A; VCC = 6.0 V

5.9 6.0 - V

IO = 6.0 mA; VCC = 4.5 V

3.98 4.32 -

V

IO = 7.8 mA; VCC = 6.0 V

5.48 5.81 -

V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 20 A; VCC = 2.0 V

• 0 0.1 V

IO = 20 A; VCC = 4.5 V

• 0 0.1 V

IO = 20 A; VCC = 6.0 V

• 0 0.1 V

IO = 6.0 mA; VCC = 4.5 V

• 0.15 0.26 V

IO = 7.8 mA; VCC = 6.0 V

• 0.16 0.26 V

input leakage current

VI = VCC or GND; VCC = 6.0 V

• - 0.1 A

II

• - 0.5 A

OFF-state output current

VI = VIH or VIL; VCC = 6.0 V;

IOZ

VO = VCC or GND

• - 8.0 A

supply current

VCC = 6.0 V; IO = 0 A;

ICC

VI = VCC or GND

CI input capacitance

• 3.5 - pF

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Table 6. Static characteristics 74HC373 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 40 C to +85 C HIGH-level input voltage

VCC = 2.0 V

1.5 - - V

VIH

VCC = 4.5 V

3.15 -

• V

VCC = 6.0 V

4.2 - - V

LOW-level input voltage

VCC = 2.0 V

• - 0.5 V

VIL

VCC = 4.5 V

• - 1.35 V

VCC = 6.0 V

• - 1.8 V

HIGH-level output voltage

VI = VIH or VIL

VOH

IO = 20 A; VCC = 2.0 V

1.9 - - V

IO = 20 A; VCC = 4.5 V

4.4 - - V

IO = 20 A; VCC = 6.0 V

5.9 - - V

IO = 6.0 mA; VCC = 4.5 V

3.84 -

• V

IO = 7.8 mA; VCC = 6.0 V

5.34 -

• V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 20 A; VCC = 2.0 V

• - 0.1 V

IO = 20 A; VCC = 4.5 V

• - 0.1 V

IO = 20 A; VCC = 6.0 V

• - 0.1 V

IO = 6.0 mA; VCC = 4.5 V

• - 0.33 V

IO = 7.8 mA; VCC = 6.0 V

• - 0.33 V

input leakage current

VI = VCC or GND; VCC = 6.0 V

• - 1.0 A

II OFF-state output current

VI = VIH or VIL; VCC = 6.0 V;

• - 5.0 A

IOZ

VO = VCC or GND

• 80 A

supply current

VCC = 6.0 V; IO = 0 A;

ICC

VI = VCC or GND

Tamb = 40 C to +125 C HIGH-level input voltage

VCC = 2.0 V

1.5 - - V

VIH

VCC = 4.5 V

3.15 -

• V

VCC = 6.0 V

4.2 - - V

LOW-level input voltage

VCC = 2.0 V

• - 0.5 V

VIL

VCC = 4.5 V

• - 1.35 V

VCC = 6.0 V

• - 1.8 V

HIGH-level output voltage

VI = VIH or VIL

VOH

IO = 20 A; VCC = 2.0 V

1.9 - - V

IO = 20 A; VCC = 4.5 V

4.4 - - V

IO = 20 A; VCC = 6.0 V

5.9 - - V

IO = 6.0 mA; VCC = 4.5 V

3.7 - - V

IO = 7.8 mA; VCC = 6.0 V

5.2 - - V

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Page 8

Table 6. Static characteristics 74HC373 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Typ Max Unit

VOL LOW-level output voltage

VI = VIH or VIL IO = 20 A; VCC = 2.0 V

• - 0.1 V

IO = 20 A; VCC = 4.5 V

• - 0.1 V

IO = 20 A; VCC = 6.0 V

• - 0.1 V

IO = 6.0 mA; VCC = 4.5 V

• - 0.4 V

IO = 7.8 mA; VCC = 6.0 V

• - 0.4 V

input leakage current

VI = VCC or GND; VCC = 6.0 V

• - 1.0 A

II OFF-state output current

VI = VIH or VIL; VCC = 6.0 V;

• - 10.0 A

IOZ

VO = VCC or GND

supply current

VCC = 6.0 V; IO = 0 A;

• - 160 A

ICC

VI = VCC or GND

Table 7. Static characteristics 74HCT373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 25 C HIGH-level input voltage

VCC = 4.5 V to 5.5 V

2.0 1.6 - V

VIH LOW-level input voltage

VCC = 4.5 V to 5.5 V

• 1.2 0.8 V

VIL HIGH-level output voltage

VI = VIH or VIL

VOH

IO = 20 A; VCC = 4.5 V

4.4 4.5 - V

IO = 6.0 mA; VCC = 4.5 V

3.98 4.32 -

V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 20 A; VCC = 4.5 V

• 0.0 0.1 V

IO = 6.0 mA; VCC = 4.5 V

• 0.16 0.26 V

input leakage current

VI = VCC or GND; VCC = 5.5 V

• - 0.1 A

II

• - 0.5 A

OFF-state output current

VI = VIH or VIL; VCC = 5.5 V;

IOZ

VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A

ICC

• - 8.0 A

supply current

VI = VCC or GND; IO = 0 A; VCC = 5.5 V

additional supply current

VI = VCC  2.1 V;

ICC

other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A Dn

• 30 108 A

LE

• 150 540 A
• 100 360 A

OE

input capacitance

• 3.5 - pF

CI Tamb = 40 C to +85 C HIGH-level input voltage

VCC = 4.5 V to 5.5 V

2.0 - - V

VIH LOW-level input voltage

VCC = 4.5 V to 5.5 V

• - 0.8 V

VIL

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Table 7. Static characteristics 74HCT373 …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter

Conditions

Min Typ Max Unit

VOH HIGH-level output voltage

VI = VIH or VIL IO = 20 A; VCC = 4.5 V

4.4 - - V

IO = 6.0 A; VCC = 4.5 V

3.84 -

• V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 20 A; VCC = 4.5 V

• - 0.1 V

IO = 6.0 mA; VCC = 4.5 V

• - 0.33 V

input leakage current

VI = VCC or GND; VCC = 5.5 V

• - 1.0 A

II OFF-state output current

VI = VIH or VIL; VCC = 5.5 V;

• - 5.0 A

IOZ

VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A

• - 80 A

supply current

VI = VCC or GND; IO = 0 A;

ICC

VCC = 5.5 V

ICC additional supply current

VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A Dn

• - 135 A

LE

• - 675 A
• - 450 A

OE

Tamb = 40 C to +125 C VIH HIGH-level input voltage

VCC = 4.5 V to 5.5 V

2.0 - - V

LOW-level input voltage

VCC = 4.5 V to 5.5 V

• - 0.8 V

VIL HIGH-level output voltage

VI = VIH or VIL

VOH

IO = 20 A; VCC = 4.5 V

4.4 - - V

IO = 6.0 mA; VCC = 4.5 V

3.7 - - V

LOW-level output voltage

VI = VIH or VIL

VOL

IO = 20 A; VCC = 4.5 V

• - 0.1 V

IO = 6.0 mA; VCC = 4.5 V

• - 0.4 V

input leakage current

VI = VCC or GND; VCC = 5.5 V

• - 1.0 A

II OFF-state output current

VI = VIH or VIL; VCC = 5.5 V;

• - 10 A

IOZ

VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A

• - 160 A

supply current

VI = VCC or GND; IO = 0 A;

ICC

VCC = 5.5 V

ICC additional supply current

VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A Dn

• - 147 A

LE

• - 735 A
• - 490 A

OE

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10. Dynamic characteristics

Table 8. Dynamic characteristics 74HC373 Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 25 C

[1]

propagation delay

Dn to Qn; see Figure 8

tpd

VCC = 2.0 V

• 41 150 ns

VCC = 4.5 V

• 15 30 ns

VCC = 5 V; CL = 15 pF

• 12 - ns

VCC = 6.0 V

• 12 26 ns

LE to Qn; see Figure 9 VCC = 2.0 V

• 50 175 ns

VCC = 4.5 V

• 18 35 ns

VCC = 5 V; CL = 15 pF

• 15 - ns

VCC = 6.0 V

• 14 30 ns

[2]

enable time

OE to Qn; see Figure 10

ten

VCC = 2.0 V

• 44 150 ns

VCC = 4.5 V

• 16 30 ns

VCC = 6.0 V

• 13 26 ns

[3]

disable time

OE to Qn; see Figure 10

tdis

VCC = 2.0 V

• 47 150 ns

VCC = 4.5 V

• 17 30 ns

VCC = 6.0 V

• 14 26 ns

[4]

transition time

Qn; see Figure 8 and Figure 9

tt

VCC = 2.0 V

• 14 60 ns

VCC = 4.5 V

• 5 12 ns

VCC = 6.0 V

• 4 10 ns

pulse width

LE HIGH; see Figure 9

tW

VCC = 2.0 V

80 17 - ns

VCC = 4.5 V

16 6 - ns

VCC = 6.0 V

14 5 - ns

set-up time

Dn to LE; see Figure 11

tsu

VCC = 2.0 V

50 14 - ns

VCC = 4.5 V

10 5 - ns

VCC = 6.0 V

9 4 - ns

hold time

Dn to LE; see Figure 11

th

VCC = 2.0 V

+5 8 - ns

VCC = 4.5 V

+5 3 - ns

VCC = 6.0 V

+5 2 - ns

[5] -

power dissipation capacitance

per latch; VI = GND to VCC

45 - pF

CPD

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Page 11

Table 8. Dynamic characteristics 74HC373 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 40 C to +85 C

[1]

propagation delay

Dn to Qn; see Figure 8

tpd

VCC = 2.0 V

• - 190 ns

VCC = 4.5 V

• - 38 ns

VCC = 6.0 V

• - 33 ns

LE to Qn; see Figure 9 VCC = 2.0 V

• - 220 ns

VCC = 4.5 V

• - 44 ns

VCC = 6.0 V

• - 37 ns

[2]

enable time

OE to Qn; see Figure 10

ten

VCC = 2.0 V

• - 190 ns

VCC = 4.5 V

• - 38 ns

VCC = 6.0 V

• - 33 ns

[3]

disable time

OE to Qn; see Figure 10

tdis

VCC = 2.0 V

• - 190 ns

VCC = 4.5 V

• - 38 ns

VCC = 6.0 V

• - 33 ns

[4]

transition time

Qn; see Figure 8 and Figure 9

tt

VCC = 2.0 V

• - 75 ns

VCC = 4.5 V

• - 15 ns

VCC = 6.0 V

• - 13 ns

pulse width

LE HIGH; see Figure 9

tW

VCC = 2.0 V

100 - - ns

VCC = 4.5 V

20 - - ns

VCC = 6.0 V

17 - - ns

set-up time

Dn to LE; see Figure 11

tsu

VCC = 2.0 V

65 - - ns

VCC = 4.5 V

13 - - ns

VCC = 6.0 V

11 - - ns

hold time

Dn to LE; see Figure 11

th

VCC = 2.0 V

5 - - ns

VCC = 4.5 V

5 - - ns

VCC = 6.0 V

5 - - ns

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Page 12

Table 8. Dynamic characteristics 74HC373 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 40 C to +125 C

[1]

propagation delay

Dn to Qn; see Figure 8

tpd

VCC = 2.0 V

• - 225 ns

VCC = 4.5 V

• - 45 ns

VCC = 6.0 V

• - 38 ns

LE to Qn; see Figure 9 VCC = 2.0 V

• - 265 ns

VCC = 4.5 V

• - 53 ns

VCC = 6.0 V

• - 45 ns

[2]

enable time

OE to Qn; see Figure 10

ten

VCC = 2.0 V

• - 225 ns

VCC = 4.5 V

• - 45 ns

VCC = 6.0 V

• - 38 ns

[3]

disable time

OE to Qn; see Figure 10

tdis

VCC = 2.0 V

• - 225 ns

VCC = 4.5 V

• - 45 ns

VCC = 6.0 V

• - 38 ns

[4]

transition time

Qn; see Figure 8 and Figure 9

tt

VCC = 2.0 V

• - 90 ns

VCC = 4.5 V

• - 18 ns

VCC = 6.0 V

• - 15 ns

pulse width

LE HIGH; see Figure 9

tW

VCC = 2.0 V

120 - - ns

VCC = 4.5 V

24 - - ns

VCC = 6.0 V

20 - - ns

set-up time

Dn to LE; see Figure 11

tsu

VCC = 2.0 V

75 - - ns

VCC = 4.5 V

15 - - ns

VCC = 6.0 V

13 - - ns

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Page 13

Table 8. Dynamic characteristics 74HC373 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter

Conditions

Min Typ Max Unit

th hold time

Dn to LE; see Figure 11 VCC = 2.0 V

5 - - ns

VCC = 4.5 V

5 - - ns

VCC = 6.0 V

5 - - ns

[1] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs.

Table 9. Dynamic characteristics 74HCT373 Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 25 C

[1]

propagation delay

Dn to Qn; see Figure 8

tpd

VCC = 4.5 V

• 17 30 ns

VCC = 5 V; CL = 15 pF

• 14 - ns

LE to Qn; see Figure 9 VCC = 4.5 V

• 16 32 ns

VCC = 5 V; CL = 15 pF

• 13 - ns

[2]

enable time

OE to Qn; see Figure 10

ten

VCC = 4.5 V

• 19 32 ns

[3]

disable time

OE to Qn; see Figure 10

tdis

VCC = 4.5 V

• 18 30 ns

[4]

transition time

Qn; see Figure 8 and Figure 9

tt

VCC = 4.5 V

• 5 12 ns

pulse width

LE HIGH; see Figure 9

tW

VCC = 4.5 V

16 4 - ns

set-up time

Dn to LE; see Figure 11

tsu

VCC = 4.5 V

12 6 - ns

hold time

Dn to LE; see Figure 11

th

VCC = 4.5 V

4 1 - ns

[5] -

power dissipation capacitance

per latch;

41 - pF

CPD

VI = GND to (VCC  1.5 V)

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Page 14

Table 9. Dynamic characteristics 74HCT373 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter

Conditions

Min Typ Max Unit

Tamb = 40 C to +85 C

[1]

propagation delay

Dn to Qn; see Figure 8

tpd

VCC = 4.5 V

• - 38 ns

LE to Qn; see Figure 9 VCC = 4.5 V

• - 40 ns

[2]

enable time

OE to Qn; see Figure 10

ten

VCC = 4.5 V

• - 40 ns

[3]

disable time

OE to Qn; see Figure 10

tdis

VCC = 4.5 V

• - 38 ns

[4]

transition time

Qn; see Figure 8 and Figure 9

tt

VCC = 4.5 V

• - 15 ns

pulse width

LE HIGH; see Figure 9

tW

VCC = 4.5 V

20 - - ns

set-up time

Dn to LE; see Figure 11

tsu

VCC = 4.5 V

15 - - ns

hold time

Dn to LE; see Figure 11

th

VCC = 4.5 V

4 - - ns

Tamb = 40 C to +125 C

[1]

propagation delay

Dn to Qn; see Figure 8

tpd

VCC = 4.5 V

• - 45 ns

LE to Qn; see Figure 9 VCC = 4.5 V

• - 48 ns

[2]

enable time

OE to Qn; see Figure 10

ten

VCC = 4.5 V

• - 48 ns

[3]

disable time

OE to Qn; see Figure 10

tdis

VCC = 4.5 V

• - 45 ns

[4]

transition time

Qn; see Figure 8 and Figure 9

tt

VCC = 4.5 V

• - 18 ns

pulse width

LE HIGH; see Figure 9

tW

VCC = 4.5 V

24 - - ns

set-up time Dn to LE

Dn to LE; see Figure 11

tsu

VCC = 4.5 V

18 - - ns

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Page 15

Table 9. Dynamic characteristics 74HCT373 …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter

Conditions

Min Typ Max Unit

Dn to LE; see Figure 11

th hold time Dn to LE

VCC = 4.5 V

4 - - ns

[1] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs.

11. Waveforms

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Page 16

Table 10. Measurement points

74HC373

0.5VCC

0.5VCC

74HCT373

1.3 V

1.3 V

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Page 17

Table 11. Test data

74HC373

VCC

6 ns

15 pF, 50 pF

1 k

open

GND

VCC

74HCT373

3 V

6 ns

15 pF, 50 pF

1 k

open

GND

VCC

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Page 18

12. Package outline

DIP20: plastic dual in-line package; 20 leads (300 mil)

SOT146-1

ME

D

A2 A

A1

L

c

e

w M

Z

b1

(e ) 1

b

MH

11

20

pin 1 index

E

1

10

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

Fig 13. Package outline SOT146-1 (DIP20)

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Page 19

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A X

c

HE

y

v M A

Z

20

11

Q

A2

A (A )

A1

3

pin 1 index

θ Lp L

10

1

detail X

e

w M bp

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

Fig 14. Package outline SOT163-1 (SO20)

19 of 26

Page 20

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm

SOT339-1

D

E

A X

c

HE

v M A

y

Z

20

11

Q

A2

A (A )

A1

3

pin 1 index

θ Lp L

1

10

detail X

w M bp

e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT339-1

MO-150

03-02-19

Fig 15. Package outline SOT339-1 (SSOP20)

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Page 21

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

E

A

D

X

c

HE

v M A

y

Z

11

20

Q

A2

(A ) A 3

A1

pin 1 index

θ Lp L

1

10

detail X

w M bp

e

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

ISSUE DATE

VERSION

PROJECTION

IEC

JEDEC

JEITA

99-12-27

SOT360-1

MO-153

03-02-19

Fig 16. Package outline SOT360-1 (TSSOP20)

21 of 26

Page 22

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

SOT764-1

20 terminals; body 2.5 x 4.5 x 0.85 mm

B A

D

A A1

E

c

detail X

terminal 1 index area

C

terminal 1

e1

index area

y

y1 C

e

v M C A B

b

w M C

2

9

L

1

10

Eh

e

20

11

19

12

Dh

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Fig 17. Package outline SOT764-1 (DHVQFN20)

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Page 23

13. Abbreviations

Table 12. Abbreviations Acronym

Description

CMOS

Complementary Metal Oxide Semiconductor

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 13. Revision history

Change notice

Document ID

Release date Data sheet status

74HC_HCT373 v.5

20111213

-

• Legal pages updated.

Modifications: 74HC_HCT373 v.4

20100903

-

74HC_HCT373 v.3

20060120

-

74HC_HCT373_CNV v.2 19970827

Product specification

-

Supersedes 74HC_HCT373 v.4

74HC_HCT373 v.3 74HC_HCT373_CNV v.2 -

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Page 24

15. Legal information

15.1 Data sheet status

Document status[1][2]

Product status[3]

Definition This document contains data from the objective specification for product development.

Objective [short] data sheet

Development

This document contains data from the preliminary specification.

Preliminary [short] data sheet Qualification

This document contains the product specification.

Product [short] data sheet

Production

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

24 of 26

Page 25

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

16. Contact information

For more information, please visit: http://www.nxp.com

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For sales office addresses, please send an email to: salesaddresses@nxp.com

25 of 26

Page 26

17. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Recommended operating conditions. . . . . . . . 6 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 24 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 16 Contact information. . . . . . . . . . . . . . . . . . . . . 25 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2011.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 December 2011 Document identifier: 74HC_HCT373